2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 704446 # Simulator instruction rate (inst/s)
4 host_mem_usage 275648 # Number of bytes of host memory used
5 host_seconds 125.40 # Real time elapsed on the host
6 host_tick_rate 9716991 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 88340674 # Number of instructions simulated
9 sim_seconds 0.001219 # Number of seconds simulated
10 sim_ticks 1218558003 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
54 system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
55 system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
56 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
57 system.cpu.dcache.overall_hits 34685672 # number of overall hits
58 system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
59 system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
60 system.cpu.dcache.overall_misses 204343 # number of overall misses
61 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
62 system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
63 system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
64 system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
65 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
66 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
67 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
68 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
69 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
70 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
71 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
72 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
73 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
74 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
75 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
76 system.cpu.dcache.replacements 200247 # number of replacements
77 system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
78 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
79 system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
80 system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
81 system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
82 system.cpu.dcache.writebacks 147714 # number of writebacks
83 system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
84 system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
85 system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
86 system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
87 system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
88 system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
89 system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
90 system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
91 system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
92 system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
93 system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
94 system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
95 system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
96 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
97 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
98 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
99 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
100 system.cpu.icache.cache_copies 0 # number of cache copies performed
101 system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
102 system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
103 system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
104 system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
105 system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
106 system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
107 system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
108 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
109 system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
110 system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
111 system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
112 system.cpu.icache.fast_writes 0 # number of fast writes performed
113 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
114 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
115 system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
116 system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
117 system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
118 system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
119 system.cpu.icache.overall_hits 88264239 # number of overall hits
120 system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
121 system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
122 system.cpu.icache.overall_misses 76436 # number of overall misses
123 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
124 system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
125 system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
126 system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
127 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
128 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
129 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
130 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
131 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
132 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
133 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
134 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
135 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
136 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
137 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
138 system.cpu.icache.replacements 74391 # number of replacements
139 system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
140 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
141 system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
142 system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
143 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
144 system.cpu.icache.writebacks 0 # number of writebacks
145 system.cpu.idle_fraction 0 # Percentage of idle cycles
146 system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
147 system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
148 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
149 system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
150 system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
151 system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
152 system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
153 system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
154 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
155 system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
156 system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
157 system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
158 system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
159 system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
160 system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
161 system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
162 system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
163 system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
164 system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
165 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
166 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
167 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
168 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
169 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
170 system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
171 system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
172 system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
173 system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
174 system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
175 system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
176 system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
177 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
178 system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
179 system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
180 system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
181 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
182 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
183 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
184 system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
185 system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
186 system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
187 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
188 system.cpu.l2cache.overall_hits 259377 # number of overall hits
189 system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
190 system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
191 system.cpu.l2cache.overall_misses 169116 # number of overall misses
192 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
193 system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
194 system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
195 system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
196 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
197 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
198 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
199 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
200 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
201 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
202 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
203 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
204 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
205 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
206 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
207 system.cpu.l2cache.replacements 135910 # number of replacements
208 system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
209 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
210 system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
211 system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
212 system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
213 system.cpu.l2cache.writebacks 115911 # number of writebacks
214 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
215 system.cpu.numCycles 1218558003 # number of cpu cycles simulated
216 system.cpu.num_insts 88340674 # Number of instructions executed
217 system.cpu.num_refs 35224019 # Number of memory references
218 system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
220 ---------- End Simulation Statistics ----------
projects / gem5.git / blob