2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 1067183 # Simulator instruction rate (inst/s)
4 host_mem_usage 254708 # Number of bytes of host memory used
5 host_seconds 94.30 # Real time elapsed on the host
6 host_tick_rate 571936208 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 100632437 # Number of instructions simulated
9 sim_seconds 0.053932 # Number of seconds simulated
10 sim_ticks 53932162000 # Number of ticks simulated
11 system.cpu.dtb.accesses 0 # DTB accesses
12 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
13 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
14 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
15 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
16 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
17 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
18 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
19 system.cpu.dtb.hits 0 # DTB hits
20 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
21 system.cpu.dtb.inst_hits 0 # ITB inst hits
22 system.cpu.dtb.inst_misses 0 # ITB inst misses
23 system.cpu.dtb.misses 0 # DTB misses
24 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
25 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
26 system.cpu.dtb.read_accesses 0 # DTB read accesses
27 system.cpu.dtb.read_hits 0 # DTB read hits
28 system.cpu.dtb.read_misses 0 # DTB read misses
29 system.cpu.dtb.write_accesses 0 # DTB write accesses
30 system.cpu.dtb.write_hits 0 # DTB write hits
31 system.cpu.dtb.write_misses 0 # DTB write misses
32 system.cpu.idle_fraction 0 # Percentage of idle cycles
33 system.cpu.itb.accesses 0 # DTB accesses
34 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
35 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
36 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
37 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
38 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
39 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
40 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
41 system.cpu.itb.hits 0 # DTB hits
42 system.cpu.itb.inst_accesses 0 # ITB inst accesses
43 system.cpu.itb.inst_hits 0 # ITB inst hits
44 system.cpu.itb.inst_misses 0 # ITB inst misses
45 system.cpu.itb.misses 0 # DTB misses
46 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
47 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
48 system.cpu.itb.read_accesses 0 # DTB read accesses
49 system.cpu.itb.read_hits 0 # DTB read hits
50 system.cpu.itb.read_misses 0 # DTB read misses
51 system.cpu.itb.write_accesses 0 # DTB write accesses
52 system.cpu.itb.write_hits 0 # DTB write hits
53 system.cpu.itb.write_misses 0 # DTB write misses
54 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
55 system.cpu.numCycles 107864325 # number of cpu cycles simulated
56 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
57 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58 system.cpu.num_busy_cycles 107864325 # Number of busy cycles
59 system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
60 system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
61 system.cpu.num_fp_insts 56 # number of float instructions
62 system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
63 system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
64 system.cpu.num_func_calls 3287514 # number of times a function call or return occured
65 system.cpu.num_idle_cycles 0 # Number of idle cycles
66 system.cpu.num_insts 100632437 # Number of instructions executed
67 system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
68 system.cpu.num_int_insts 91472788 # number of integer instructions
69 system.cpu.num_int_register_reads 261951567 # number of times the integer registers were read
70 system.cpu.num_int_register_writes 73126599 # number of times the integer registers were written
71 system.cpu.num_load_insts 27307109 # Number of load instructions
72 system.cpu.num_mem_refs 47862848 # number of memory refs
73 system.cpu.num_store_insts 20555739 # Number of store instructions
74 system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
76 ---------- End Simulation Statistics ----------
projects / gem5.git / blob