2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 480067 # Simulator instruction rate (inst/s)
4 host_mem_usage 157016 # Number of bytes of host memory used
5 host_seconds 283.81 # Real time elapsed on the host
6 host_tick_rate 698858124 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 136246936 # Number of instructions simulated
9 sim_seconds 0.198342 # Number of seconds simulated
10 sim_ticks 198341876000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
21 system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
22 system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency
23 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency
24 system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
25 system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles
26 system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
27 system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
28 system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles
29 system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
30 system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
31 system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
32 system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency
33 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency
34 system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
35 system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles
36 system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
37 system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
38 system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles
39 system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
40 system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
41 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
42 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
43 system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
44 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
45 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
46 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
47 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
48 system.cpu.dcache.cache_copies 0 # number of cache copies performed
49 system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
50 system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency
51 system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
52 system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
53 system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles
54 system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
55 system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
56 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
57 system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles
58 system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
59 system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
60 system.cpu.dcache.fast_writes 0 # number of fast writes performed
61 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
62 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
63 system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
64 system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency
65 system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
66 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
67 system.cpu.dcache.overall_hits 57944942 # number of overall hits
68 system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles
69 system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
70 system.cpu.dcache.overall_misses 150663 # number of overall misses
71 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
72 system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles
73 system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
74 system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
75 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
76 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
77 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
78 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
79 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
80 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
81 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
82 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
83 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
84 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
85 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
86 system.cpu.dcache.replacements 146582 # number of replacements
87 system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
88 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
89 system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use
90 system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
91 system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit.
92 system.cpu.dcache.writebacks 107279 # number of writebacks
93 system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
94 system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency
95 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency
96 system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
97 system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles
98 system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
99 system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
100 system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles
101 system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
102 system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
103 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
104 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
105 system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks.
106 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
107 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
108 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
109 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
110 system.cpu.icache.cache_copies 0 # number of cache copies performed
111 system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
112 system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency
113 system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
114 system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
115 system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles
116 system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
117 system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
118 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
119 system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles
120 system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
121 system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
122 system.cpu.icache.fast_writes 0 # number of fast writes performed
123 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
124 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
125 system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
126 system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency
127 system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
128 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
129 system.cpu.icache.overall_hits 136059913 # number of overall hits
130 system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles
131 system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
132 system.cpu.icache.overall_misses 187024 # number of overall misses
133 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
134 system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles
135 system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
136 system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
137 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
138 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
139 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
140 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
141 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
142 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
143 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
144 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
145 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
146 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
147 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
148 system.cpu.icache.replacements 184976 # number of replacements
149 system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
150 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
151 system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use
152 system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
153 system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit.
154 system.cpu.icache.writebacks 0 # number of writebacks
155 system.cpu.idle_fraction 0 # Percentage of idle cycles
156 system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
157 system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency
158 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency
159 system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
160 system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles
161 system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
162 system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
163 system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles
164 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
165 system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
166 system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
167 system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits
168 system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses
169 system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses
170 system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses
171 system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses
172 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
173 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
174 system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks.
175 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
176 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
177 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
178 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
179 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
180 system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
181 system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency
182 system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
183 system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
184 system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles
185 system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
186 system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
187 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
188 system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles
189 system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
190 system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
191 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
192 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
193 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
194 system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
195 system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency
196 system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
197 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
198 system.cpu.l2cache.overall_hits 309728 # number of overall hits
199 system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles
200 system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
201 system.cpu.l2cache.overall_misses 135187 # number of overall misses
202 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
203 system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles
204 system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
205 system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
206 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
207 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
208 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
209 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
210 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
211 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
212 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
213 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
214 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
215 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
216 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
217 system.cpu.l2cache.replacements 101911 # number of replacements
218 system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
219 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
220 system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use
221 system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
222 system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit.
223 system.cpu.l2cache.writebacks 82918 # number of writebacks
224 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
225 system.cpu.numCycles 198341876000 # number of cpu cycles simulated
226 system.cpu.num_insts 136246936 # Number of instructions executed
227 system.cpu.num_refs 58111522 # Number of memory references
228 system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
230 ---------- End Simulation Statistics ----------
projects / gem5.git / blob