2 ---------- Begin Simulation Statistics ----------
3 global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
4 global.BPredUnit.BTBHits 236329759 # Number of BTB hits
5 global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups
6 global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions.
7 global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect
8 global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted
9 global.BPredUnit.lookups 265702680 # Number of BP lookups
10 global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target.
11 host_inst_rate 104740 # Simulator instruction rate (inst/s)
12 host_mem_usage 154596 # Number of bytes of host memory used
13 host_seconds 16574.74 # Real time elapsed on the host
14 host_tick_rate 38540500 # Simulator tick rate (ticks/s)
15 memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads.
16 memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores.
17 memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit.
18 memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit.
19 sim_freq 1000000000000 # Frequency of simulated ticks
20 sim_insts 1736043781 # Number of instructions simulated
21 sim_seconds 0.638799 # Number of seconds simulated
22 sim_ticks 638798750000 # Number of ticks simulated
23 system.cpu.commit.COM:branches 214632552 # Number of branches committed
24 system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached
25 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
26 system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle.samples 1240430038
28 system.cpu.commit.COM:committed_per_cycle.min_value 0
38 system.cpu.commit.COM:committed_per_cycle.max_value 8
39 system.cpu.commit.COM:committed_per_cycle.end_dist
41 system.cpu.commit.COM:count 1819780126 # Number of instructions committed
42 system.cpu.commit.COM:loads 445666361 # Number of loads committed
43 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
44 system.cpu.commit.COM:refs 606571343 # Number of memory references committed
45 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
46 system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted
47 system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
48 system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
49 system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit
50 system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
51 system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
52 system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction
53 system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads
54 system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses)
55 system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency
56 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency
57 system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits
58 system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles
59 system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses
60 system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses
61 system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits
62 system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles
63 system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses
64 system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses
65 system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
66 system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency
67 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency
68 system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits
69 system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles
70 system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses
71 system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses
72 system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses
75 system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses
76 system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked
77 system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked
78 system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks.
79 system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked
80 system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked
81 system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked
83 system.cpu.dcache.cache_copies 0 # number of cache copies performed
84 system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses
85 system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency
86 system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
87 system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits
88 system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles
89 system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses
90 system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses
91 system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits
92 system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles
93 system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses
94 system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses
95 system.cpu.dcache.fast_writes 0 # number of fast writes performed
96 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
97 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses
99 system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency
100 system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
101 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
102 system.cpu.dcache.overall_hits 609102856 # number of overall hits
103 system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles
104 system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses
105 system.cpu.dcache.overall_misses 11929003 # number of overall misses
106 system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits
107 system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles
108 system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses
109 system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses
110 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
111 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
112 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
113 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
114 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
115 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
116 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
117 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
118 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
119 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
120 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
121 system.cpu.dcache.replacements 9171759 # number of replacements
122 system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks.
123 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
124 system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use
125 system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks.
126 system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit.
127 system.cpu.dcache.writebacks 2245633 # number of writebacks
128 system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked
129 system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction
130 system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch
131 system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode
132 system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle
133 system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running
134 system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing
135 system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode
136 system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking
137 system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered
138 system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched
139 system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked
140 system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed
141 system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed
142 system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing
143 system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle
144 system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss
145 system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken
146 system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle
147 system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
148 system.cpu.fetch.rateDist.samples 1277597526
149 system.cpu.fetch.rateDist.min_value 0
159 system.cpu.fetch.rateDist.max_value 8
160 system.cpu.fetch.rateDist.end_dist
162 system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses)
163 system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency
164 system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency
165 system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits
166 system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles
167 system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses
169 system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits
170 system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles
171 system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
172 system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses
173 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
174 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
175 system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks.
176 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
177 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
178 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
179 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
180 system.cpu.icache.cache_copies 0 # number of cache copies performed
181 system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses
182 system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency
183 system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
184 system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits
185 system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles
186 system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
187 system.cpu.icache.demand_misses 947 # number of demand (read+write) misses
188 system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
189 system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles
190 system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
191 system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses
192 system.cpu.icache.fast_writes 0 # number of fast writes performed
193 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
194 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
195 system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses
196 system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency
197 system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
198 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
199 system.cpu.icache.overall_hits 277956896 # number of overall hits
200 system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles
201 system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
202 system.cpu.icache.overall_misses 947 # number of overall misses
203 system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits
204 system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles
205 system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
206 system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses
207 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
208 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
209 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
210 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
211 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
212 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
213 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
214 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
215 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
216 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
217 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
218 system.cpu.icache.replacements 1 # number of replacements
219 system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks.
220 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
221 system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use
222 system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks.
223 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224 system.cpu.icache.writebacks 0 # number of writebacks
225 system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling
226 system.cpu.iew.EXEC:branches 231142223 # Number of branches executed
227 system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed
228 system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate
229 system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed
230 system.cpu.iew.EXEC:stores 168419462 # Number of stores executed
231 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
232 system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value
233 system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back
234 system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back
235 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
236 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
237 system.cpu.iew.WB:producers 991749121 # num instructions producing a value
238 system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle
239 system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit
240 system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute
241 system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking
242 system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions
243 system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions
244 system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch
245 system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions
246 system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ
247 system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed
248 system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute
249 system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions
250 system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall
251 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
252 system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall
253 system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing
254 system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking
255 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
256 system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked
257 system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores
258 system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed
259 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
260 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
261 system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations
262 system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
263 system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed
264 system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed
265 system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations
266 system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly
267 system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly
268 system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle
269 system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads
270 system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued
271 system.cpu.iq.ISSUE:FU_type_0.start_dist
272 (null) 0 0.00% # Type of FU issued
273 IntAlu 1224165146 65.09% # Type of FU issued
274 IntMult 78 0.00% # Type of FU issued
275 IntDiv 0 0.00% # Type of FU issued
276 FloatAdd 199 0.00% # Type of FU issued
277 FloatCmp 15 0.00% # Type of FU issued
278 FloatCvt 141 0.00% # Type of FU issued
279 FloatMult 13 0.00% # Type of FU issued
280 FloatDiv 24 0.00% # Type of FU issued
281 FloatSqrt 0 0.00% # Type of FU issued
282 MemRead 487297898 25.91% # Type of FU issued
283 MemWrite 169129941 8.99% # Type of FU issued
284 IprAccess 0 0.00% # Type of FU issued
285 InstPrefetch 0 0.00% # Type of FU issued
286 system.cpu.iq.ISSUE:FU_type_0.end_dist
287 system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested
288 system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst)
289 system.cpu.iq.ISSUE:fu_full.start_dist
290 (null) 0 0.00% # attempts to use FU when none available
291 IntAlu 753308 5.08% # attempts to use FU when none available
292 IntMult 0 0.00% # attempts to use FU when none available
293 IntDiv 0 0.00% # attempts to use FU when none available
294 FloatAdd 0 0.00% # attempts to use FU when none available
295 FloatCmp 0 0.00% # attempts to use FU when none available
296 FloatCvt 0 0.00% # attempts to use FU when none available
297 FloatMult 0 0.00% # attempts to use FU when none available
298 FloatDiv 0 0.00% # attempts to use FU when none available
299 FloatSqrt 0 0.00% # attempts to use FU when none available
300 MemRead 10126775 68.23% # attempts to use FU when none available
301 MemWrite 3961138 26.69% # attempts to use FU when none available
302 IprAccess 0 0.00% # attempts to use FU when none available
303 InstPrefetch 0 0.00% # attempts to use FU when none available
304 system.cpu.iq.ISSUE:fu_full.end_dist
305 system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
306 system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526
307 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
317 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
318 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
320 system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate
321 system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec)
322 system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued
323 system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
324 system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling
325 system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued
326 system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
327 system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph
328 system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses)
329 system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency
330 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency
331 system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits
332 system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles
333 system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses
334 system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses
335 system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles
336 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses
337 system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses
338 system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses)
339 system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits
340 system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses
341 system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses
342 system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses
343 system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses
344 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
345 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
346 system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks.
347 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
348 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
349 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
350 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
351 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
352 system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses
353 system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency
354 system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
355 system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits
356 system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles
357 system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses
358 system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses
359 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
360 system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles
361 system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses
362 system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses
363 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
364 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
365 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
366 system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses
367 system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency
368 system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
369 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
370 system.cpu.l2cache.overall_hits 9224685 # number of overall hits
371 system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles
372 system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses
373 system.cpu.l2cache.overall_misses 2197691 # number of overall misses
374 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
375 system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles
376 system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses
377 system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses
378 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
379 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
380 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
381 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
382 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
383 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
384 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
385 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
386 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
387 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
388 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
389 system.cpu.l2cache.replacements 2135792 # number of replacements
390 system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks.
391 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
392 system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use
393 system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks.
394 system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit.
395 system.cpu.l2cache.writebacks 1039396 # number of writebacks
396 system.cpu.numCycles 1277597526 # number of cpu cycles simulated
397 system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking
398 system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
399 system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full
400 system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle
401 system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full
402 system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full
403 system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made
404 system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename
405 system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed
406 system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running
407 system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing
408 system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking
409 system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing
410 system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst
411 system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed
412 system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer
413 system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed
414 system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself
415 system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
417 ---------- End Simulation Statistics ----------
projects / gem5.git / blob