2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 154101 # Simulator instruction rate (inst/s)
4 host_mem_usage 217652 # Number of bytes of host memory used
5 host_seconds 11181.42 # Real time elapsed on the host
6 host_tick_rate 57496303 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1723073854 # Number of instructions simulated
9 sim_seconds 0.642891 # Number of seconds simulated
10 sim_ticks 642890553000 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 223193937 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 259593204 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 340 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 18005065 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target.
19 system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted
20 system.cpu.commit.branches 213462366 # Number of branches committed
21 system.cpu.commit.bw_lim_events 57604302 # number cycles where commit BW limit reached
22 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
23 system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions
24 system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards
25 system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit
26 system.cpu.commit.committed_per_cycle::samples 1166659925 # Number of insts commited each cycle
27 system.cpu.commit.committed_per_cycle::mean 1.476929 # Number of insts commited each cycle
28 system.cpu.commit.committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle
29 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
30 system.cpu.commit.committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle
31 system.cpu.commit.committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle
32 system.cpu.commit.committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle
33 system.cpu.commit.committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle
34 system.cpu.commit.committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle
35 system.cpu.commit.committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle
36 system.cpu.commit.committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle
37 system.cpu.commit.committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle
38 system.cpu.commit.committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle
39 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
40 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
41 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
42 system.cpu.commit.committed_per_cycle::total 1166659925 # Number of insts commited each cycle
43 system.cpu.commit.count 1723073872 # Number of instructions committed
44 system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
45 system.cpu.commit.function_calls 13665177 # Number of function calls committed.
46 system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
47 system.cpu.commit.loads 485926772 # Number of loads committed
48 system.cpu.commit.membars 62 # Number of memory barriers committed
49 system.cpu.commit.refs 660773819 # Number of memory references committed
50 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
51 system.cpu.committedInsts 1723073854 # Number of Instructions Simulated
52 system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated
53 system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction
54 system.cpu.cpi_total 0.746214 # CPI: Total CPI of All Threads
55 system.cpu.dcache.LoadLockedReq_accesses 65 # number of LoadLockedReq accesses(hits+misses)
56 system.cpu.dcache.LoadLockedReq_avg_miss_latency 27333.333333 # average LoadLockedReq miss latency
57 system.cpu.dcache.LoadLockedReq_hits 62 # number of LoadLockedReq hits
58 system.cpu.dcache.LoadLockedReq_miss_latency 82000 # number of LoadLockedReq miss cycles
59 system.cpu.dcache.LoadLockedReq_miss_rate 0.046154 # miss rate for LoadLockedReq accesses
60 system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
61 system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
62 system.cpu.dcache.ReadReq_accesses 501584612 # number of ReadReq accesses(hits+misses)
63 system.cpu.dcache.ReadReq_avg_miss_latency 15160.364798 # average ReadReq miss latency
64 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11507.023204 # average ReadReq mshr miss latency
65 system.cpu.dcache.ReadReq_hits 493452712 # number of ReadReq hits
66 system.cpu.dcache.ReadReq_miss_latency 123282570500 # number of ReadReq miss cycles
67 system.cpu.dcache.ReadReq_miss_rate 0.016212 # miss rate for ReadReq accesses
68 system.cpu.dcache.ReadReq_misses 8131900 # number of ReadReq misses
69 system.cpu.dcache.ReadReq_mshr_hits 482613 # number of ReadReq MSHR hits
70 system.cpu.dcache.ReadReq_mshr_miss_latency 88020523000 # number of ReadReq MSHR miss cycles
71 system.cpu.dcache.ReadReq_mshr_miss_rate 0.015250 # mshr miss rate for ReadReq accesses
72 system.cpu.dcache.ReadReq_mshr_misses 7649287 # number of ReadReq MSHR misses
73 system.cpu.dcache.StoreCondReq_accesses 63 # number of StoreCondReq accesses(hits+misses)
74 system.cpu.dcache.StoreCondReq_hits 63 # number of StoreCondReq hits
75 system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
76 system.cpu.dcache.WriteReq_avg_miss_latency 23758.689113 # average WriteReq miss latency
77 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20868.683162 # average WriteReq mshr miss latency
78 system.cpu.dcache.WriteReq_hits 168021895 # number of WriteReq hits
79 system.cpu.dcache.WriteReq_miss_latency 108438268431 # number of WriteReq miss cycles
80 system.cpu.dcache.WriteReq_miss_rate 0.026446 # miss rate for WriteReq accesses
81 system.cpu.dcache.WriteReq_misses 4564152 # number of WriteReq misses
82 system.cpu.dcache.WriteReq_mshr_hits 2672149 # number of WriteReq MSHR hits
83 system.cpu.dcache.WriteReq_mshr_miss_latency 39483611148 # number of WriteReq MSHR miss cycles
84 system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
85 system.cpu.dcache.WriteReq_mshr_misses 1892003 # number of WriteReq MSHR misses
86 system.cpu.dcache.avg_blocked_cycles::no_mshrs 3136.287441 # average number of cycles each access was blocked
87 system.cpu.dcache.avg_blocked_cycles::no_targets 20750 # average number of cycles each access was blocked
88 system.cpu.dcache.avg_refs 69.327600 # Average number of references to valid blocks.
89 system.cpu.dcache.blocked::no_mshrs 24979 # number of cycles access was blocked
90 system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
91 system.cpu.dcache.blocked_cycles::no_mshrs 78341324 # number of cycles access was blocked
92 system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked
93 system.cpu.dcache.cache_copies 0 # number of cache copies performed
94 system.cpu.dcache.demand_accesses 674170659 # number of demand (read+write) accesses
95 system.cpu.dcache.demand_avg_miss_latency 18251.409094 # average overall miss latency
96 system.cpu.dcache.demand_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
97 system.cpu.dcache.demand_hits 661474607 # number of demand (read+write) hits
98 system.cpu.dcache.demand_miss_latency 231720838931 # number of demand (read+write) miss cycles
99 system.cpu.dcache.demand_miss_rate 0.018832 # miss rate for demand accesses
100 system.cpu.dcache.demand_misses 12696052 # number of demand (read+write) misses
101 system.cpu.dcache.demand_mshr_hits 3154762 # number of demand (read+write) MSHR hits
102 system.cpu.dcache.demand_mshr_miss_latency 127504134148 # number of demand (read+write) MSHR miss cycles
103 system.cpu.dcache.demand_mshr_miss_rate 0.014153 # mshr miss rate for demand accesses
104 system.cpu.dcache.demand_mshr_misses 9541290 # number of demand (read+write) MSHR misses
105 system.cpu.dcache.fast_writes 0 # number of fast writes performed
106 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
107 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
108 system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context
109 system.cpu.dcache.occ_percent::0 0.997826 # Average percentage of cache occupancy
110 system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses
111 system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency
112 system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
113 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
114 system.cpu.dcache.overall_hits 661474607 # number of overall hits
115 system.cpu.dcache.overall_miss_latency 231720838931 # number of overall miss cycles
116 system.cpu.dcache.overall_miss_rate 0.018832 # miss rate for overall accesses
117 system.cpu.dcache.overall_misses 12696052 # number of overall misses
118 system.cpu.dcache.overall_mshr_hits 3154762 # number of overall MSHR hits
119 system.cpu.dcache.overall_mshr_miss_latency 127504134148 # number of overall MSHR miss cycles
120 system.cpu.dcache.overall_mshr_miss_rate 0.014153 # mshr miss rate for overall accesses
121 system.cpu.dcache.overall_mshr_misses 9541290 # number of overall MSHR misses
122 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
123 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.cpu.dcache.replacements 9537194 # number of replacements
125 system.cpu.dcache.sampled_refs 9541290 # Sample count of references to valid blocks.
126 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
127 system.cpu.dcache.tagsinuse 4087.096656 # Cycle average of tags in use
128 system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks.
129 system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit.
130 system.cpu.dcache.writebacks 3122149 # number of writebacks
131 system.cpu.decode.BlockedCycles 127119222 # Number of cycles decode is blocked
132 system.cpu.decode.BranchMispred 630 # Number of times decode detected a branch misprediction
133 system.cpu.decode.BranchResolved 46145837 # Number of times decode resolved a branch
134 system.cpu.decode.DecodedInsts 2344585205 # Number of instructions handled by decode
135 system.cpu.decode.IdleCycles 578307676 # Number of cycles decode is idle
136 system.cpu.decode.RunCycles 449658106 # Number of cycles decode is running
137 system.cpu.decode.SquashCycles 70439042 # Number of cycles decode is squashing
138 system.cpu.decode.SquashedInsts 2261 # Number of squashed instructions handled by decode
139 system.cpu.decode.UnblockCycles 11574920 # Number of cycles decode is unblocking
140 system.cpu.dtb.accesses 0 # DTB accesses
141 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
142 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
143 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
144 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
145 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
146 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
147 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
148 system.cpu.dtb.hits 0 # DTB hits
149 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
150 system.cpu.dtb.inst_hits 0 # ITB inst hits
151 system.cpu.dtb.inst_misses 0 # ITB inst misses
152 system.cpu.dtb.misses 0 # DTB misses
153 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
154 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
155 system.cpu.dtb.read_accesses 0 # DTB read accesses
156 system.cpu.dtb.read_hits 0 # DTB read hits
157 system.cpu.dtb.read_misses 0 # DTB read misses
158 system.cpu.dtb.write_accesses 0 # DTB write accesses
159 system.cpu.dtb.write_hits 0 # DTB write hits
160 system.cpu.dtb.write_misses 0 # DTB write misses
161 system.cpu.fetch.Branches 296310364 # Number of branches that fetch encountered
162 system.cpu.fetch.CacheLines 276394619 # Number of cache lines fetched
163 system.cpu.fetch.Cycles 469857260 # Number of cycles fetch has run and was not squashing or blocked
164 system.cpu.fetch.IcacheSquashes 5099612 # Number of outstanding Icache misses that were squashed
165 system.cpu.fetch.Insts 2155595751 # Number of instructions fetch has processed
166 system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
167 system.cpu.fetch.SquashCycles 18544487 # Number of cycles fetch has spent squashing
168 system.cpu.fetch.branchRate 0.230452 # Number of branch fetches per cycle
169 system.cpu.fetch.icacheStallCycles 276394619 # Number of cycles fetch is stalled on an Icache miss
170 system.cpu.fetch.predictedBranches 240965250 # Number of branches that fetch has predicted taken
171 system.cpu.fetch.rate 1.676487 # Number of inst fetches per cycle
172 system.cpu.fetch.rateDist::samples 1237098966 # Number of instructions fetched each cycle (Total)
173 system.cpu.fetch.rateDist::mean 1.930612 # Number of instructions fetched each cycle (Total)
174 system.cpu.fetch.rateDist::stdev 2.884681 # Number of instructions fetched each cycle (Total)
175 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
176 system.cpu.fetch.rateDist::0 767241756 62.02% 62.02% # Number of instructions fetched each cycle (Total)
177 system.cpu.fetch.rateDist::1 33244799 2.69% 64.71% # Number of instructions fetched each cycle (Total)
178 system.cpu.fetch.rateDist::2 58987586 4.77% 69.47% # Number of instructions fetched each cycle (Total)
179 system.cpu.fetch.rateDist::3 61314807 4.96% 74.43% # Number of instructions fetched each cycle (Total)
180 system.cpu.fetch.rateDist::4 46983054 3.80% 78.23% # Number of instructions fetched each cycle (Total)
181 system.cpu.fetch.rateDist::5 54993105 4.45% 82.67% # Number of instructions fetched each cycle (Total)
182 system.cpu.fetch.rateDist::6 53020195 4.29% 86.96% # Number of instructions fetched each cycle (Total)
183 system.cpu.fetch.rateDist::7 18334456 1.48% 88.44% # Number of instructions fetched each cycle (Total)
184 system.cpu.fetch.rateDist::8 142979208 11.56% 100.00% # Number of instructions fetched each cycle (Total)
185 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
186 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
187 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
188 system.cpu.fetch.rateDist::total 1237098966 # Number of instructions fetched each cycle (Total)
189 system.cpu.fp_regfile_reads 39 # number of floating regfile reads
190 system.cpu.fp_regfile_writes 31 # number of floating regfile writes
191 system.cpu.icache.ReadReq_accesses 276394619 # number of ReadReq accesses(hits+misses)
192 system.cpu.icache.ReadReq_avg_miss_latency 34658.288770 # average ReadReq miss latency
193 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34406.030856 # average ReadReq mshr miss latency
194 system.cpu.icache.ReadReq_hits 276393684 # number of ReadReq hits
195 system.cpu.icache.ReadReq_miss_latency 32405500 # number of ReadReq miss cycles
196 system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
197 system.cpu.icache.ReadReq_misses 935 # number of ReadReq misses
198 system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
199 system.cpu.icache.ReadReq_mshr_miss_latency 24531500 # number of ReadReq MSHR miss cycles
200 system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
201 system.cpu.icache.ReadReq_mshr_misses 713 # number of ReadReq MSHR misses
202 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
203 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
204 system.cpu.icache.avg_refs 387648.925666 # Average number of references to valid blocks.
205 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
206 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
207 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
208 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
209 system.cpu.icache.cache_copies 0 # number of cache copies performed
210 system.cpu.icache.demand_accesses 276394619 # number of demand (read+write) accesses
211 system.cpu.icache.demand_avg_miss_latency 34658.288770 # average overall miss latency
212 system.cpu.icache.demand_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
213 system.cpu.icache.demand_hits 276393684 # number of demand (read+write) hits
214 system.cpu.icache.demand_miss_latency 32405500 # number of demand (read+write) miss cycles
215 system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
216 system.cpu.icache.demand_misses 935 # number of demand (read+write) misses
217 system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
218 system.cpu.icache.demand_mshr_miss_latency 24531500 # number of demand (read+write) MSHR miss cycles
219 system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
220 system.cpu.icache.demand_mshr_misses 713 # number of demand (read+write) MSHR misses
221 system.cpu.icache.fast_writes 0 # number of fast writes performed
222 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
223 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
224 system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context
225 system.cpu.icache.occ_percent::0 0.281945 # Average percentage of cache occupancy
226 system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses
227 system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency
228 system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
229 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
230 system.cpu.icache.overall_hits 276393684 # number of overall hits
231 system.cpu.icache.overall_miss_latency 32405500 # number of overall miss cycles
232 system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
233 system.cpu.icache.overall_misses 935 # number of overall misses
234 system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
235 system.cpu.icache.overall_mshr_miss_latency 24531500 # number of overall MSHR miss cycles
236 system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
237 system.cpu.icache.overall_mshr_misses 713 # number of overall MSHR misses
238 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
239 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
240 system.cpu.icache.replacements 8 # number of replacements
241 system.cpu.icache.sampled_refs 713 # Sample count of references to valid blocks.
242 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
243 system.cpu.icache.tagsinuse 577.423416 # Cycle average of tags in use
244 system.cpu.icache.total_refs 276393684 # Total number of references to valid blocks.
245 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
246 system.cpu.icache.writebacks 0 # number of writebacks
247 system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling
248 system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute
249 system.cpu.iew.exec_branches 233410057 # Number of branches executed
250 system.cpu.iew.exec_nop 371 # number of nop insts executed
251 system.cpu.iew.exec_rate 1.517006 # Inst execution rate
252 system.cpu.iew.exec_refs 747857641 # number of memory reference insts executed
253 system.cpu.iew.exec_stores 187754946 # Number of stores executed
254 system.cpu.iew.exec_swp 0 # number of swp insts executed
255 system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking
256 system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions
257 system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions
258 system.cpu.iew.iewDispSquashedInsts 5945884 # Number of squashed instructions skipped by dispatch
259 system.cpu.iew.iewDispStoreInsts 225252424 # Number of dispatched store instructions
260 system.cpu.iew.iewDispatchedInsts 2211114719 # Number of instructions dispatched to IQ
261 system.cpu.iew.iewExecLoadInsts 560102695 # Number of load instructions executed
262 system.cpu.iew.iewExecSquashedInsts 21129397 # Number of squashed instructions skipped in execute
263 system.cpu.iew.iewExecutedInsts 1950537549 # Number of executed instructions
264 system.cpu.iew.iewIQFullEvents 1433857 # Number of times the IQ has become full, causing a stall
265 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
266 system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall
267 system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing
268 system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking
269 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
270 system.cpu.iew.lsq.thread0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked
271 system.cpu.iew.lsq.thread0.forwLoads 54506765 # Number of loads that had data forwarded from stores
272 system.cpu.iew.lsq.thread0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed
273 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
274 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
275 system.cpu.iew.lsq.thread0.memOrderViolation 734835 # Number of memory ordering violations
276 system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
277 system.cpu.iew.lsq.thread0.squashedLoads 140151655 # Number of loads squashed
278 system.cpu.iew.lsq.thread0.squashedStores 50405377 # Number of stores squashed
279 system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations
280 system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly
281 system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly
282 system.cpu.iew.wb_consumers 2256424150 # num instructions consuming a value
283 system.cpu.iew.wb_count 1928710637 # cumulative count of insts written-back
284 system.cpu.iew.wb_fanout 0.551017 # average fanout of values written-back
285 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
286 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
287 system.cpu.iew.wb_producers 1243327288 # num instructions producing a value
288 system.cpu.iew.wb_rate 1.500030 # insts written-back per cycle
289 system.cpu.iew.wb_sent 1934940770 # cumulative count of insts sent to commit
290 system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads
291 system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes
292 system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle
293 system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads
294 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
295 system.cpu.iq.FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued
296 system.cpu.iq.FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued
297 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
298 system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued
299 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
300 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
301 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
302 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
303 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
304 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
305 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
306 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
307 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
308 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
309 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
310 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
311 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
312 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
313 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
314 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
315 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
316 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
317 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
318 system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued
319 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued
320 system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued
321 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
322 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
323 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
324 system.cpu.iq.FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued
325 system.cpu.iq.FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued
326 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
327 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
328 system.cpu.iq.FU_type_0::total 1971666946 # Type of FU issued
329 system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
330 system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads
331 system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses
332 system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes
333 system.cpu.iq.fu_busy_cnt 20875026 # FU busy when requested
334 system.cpu.iq.fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst)
335 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
336 system.cpu.iq.fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available
337 system.cpu.iq.fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available
338 system.cpu.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
339 system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
340 system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
341 system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
342 system.cpu.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
343 system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
344 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
353 system.cpu.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
354 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
355 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
356 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
357 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
358 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
359 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
360 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
361 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
362 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
363 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
365 system.cpu.iq.fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available
366 system.cpu.iq.fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available
367 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
368 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
369 system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses
370 system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads
371 system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses
372 system.cpu.iq.int_inst_queue_writes 2696699928 # Number of integer instruction queue writes
373 system.cpu.iq.iqInstsAdded 2211113711 # Number of instructions added to the IQ (excludes non-spec)
374 system.cpu.iq.iqInstsIssued 1971666946 # Number of instructions issued
375 system.cpu.iq.iqNonSpecInstsAdded 637 # Number of non-speculative instructions added to the IQ
376 system.cpu.iq.iqSquashedInstsExamined 484979968 # Number of squashed instructions iterated over during squash; mainly for profiling
377 system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued
378 system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
379 system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph
380 system.cpu.iq.issued_per_cycle::samples 1237098966 # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::mean 1.593783 # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::total 1237098966 # Number of insts issued each cycle
397 system.cpu.iq.rate 1.533439 # Inst issue rate
398 system.cpu.itb.accesses 0 # DTB accesses
399 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
400 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
401 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
402 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
403 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
404 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
405 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
406 system.cpu.itb.hits 0 # DTB hits
407 system.cpu.itb.inst_accesses 0 # ITB inst accesses
408 system.cpu.itb.inst_hits 0 # ITB inst hits
409 system.cpu.itb.inst_misses 0 # ITB inst misses
410 system.cpu.itb.misses 0 # DTB misses
411 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
412 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
413 system.cpu.itb.read_accesses 0 # DTB read accesses
414 system.cpu.itb.read_hits 0 # DTB read hits
415 system.cpu.itb.read_misses 0 # DTB read misses
416 system.cpu.itb.write_accesses 0 # DTB write accesses
417 system.cpu.itb.write_hits 0 # DTB write hits
418 system.cpu.itb.write_misses 0 # DTB write misses
419 system.cpu.l2cache.ReadExReq_accesses 1892006 # number of ReadExReq accesses(hits+misses)
420 system.cpu.l2cache.ReadExReq_avg_miss_latency 34501.539320 # average ReadExReq miss latency
421 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.195670 # average ReadExReq mshr miss latency
422 system.cpu.l2cache.ReadExReq_hits 979915 # number of ReadExReq hits
423 system.cpu.l2cache.ReadExReq_miss_latency 31468543500 # number of ReadExReq miss cycles
424 system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses
425 system.cpu.l2cache.ReadExReq_misses 912091 # number of ReadExReq misses
426 system.cpu.l2cache.ReadExReq_mshr_miss_latency 28586022500 # number of ReadExReq MSHR miss cycles
427 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses
428 system.cpu.l2cache.ReadExReq_mshr_misses 912091 # number of ReadExReq MSHR misses
429 system.cpu.l2cache.ReadReq_accesses 7649997 # number of ReadReq accesses(hits+misses)
430 system.cpu.l2cache.ReadReq_avg_miss_latency 34318.289104 # average ReadReq miss latency
431 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.516872 # average ReadReq mshr miss latency
432 system.cpu.l2cache.ReadReq_hits 5630330 # number of ReadReq hits
433 system.cpu.l2cache.ReadReq_miss_latency 69311516000 # number of ReadReq miss cycles
434 system.cpu.l2cache.ReadReq_miss_rate 0.264009 # miss rate for ReadReq accesses
435 system.cpu.l2cache.ReadReq_misses 2019667 # number of ReadReq misses
436 system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
437 system.cpu.l2cache.ReadReq_mshr_miss_latency 62868927000 # number of ReadReq MSHR miss cycles
438 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264008 # mshr miss rate for ReadReq accesses
439 system.cpu.l2cache.ReadReq_mshr_misses 2019657 # number of ReadReq MSHR misses
440 system.cpu.l2cache.Writeback_accesses 3122149 # number of Writeback accesses(hits+misses)
441 system.cpu.l2cache.Writeback_hits 3122149 # number of Writeback hits
442 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3935.335196 # average number of cycles each access was blocked
443 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
444 system.cpu.l2cache.avg_refs 2.653954 # Average number of references to valid blocks.
445 system.cpu.l2cache.blocked::no_mshrs 3580 # number of cycles access was blocked
446 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
447 system.cpu.l2cache.blocked_cycles::no_mshrs 14088500 # number of cycles access was blocked
448 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
450 system.cpu.l2cache.demand_accesses 9542003 # number of demand (read+write) accesses
451 system.cpu.l2cache.demand_avg_miss_latency 34375.299564 # average overall miss latency
452 system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
453 system.cpu.l2cache.demand_hits 6610245 # number of demand (read+write) hits
454 system.cpu.l2cache.demand_miss_latency 100780059500 # number of demand (read+write) miss cycles
455 system.cpu.l2cache.demand_miss_rate 0.307248 # miss rate for demand accesses
456 system.cpu.l2cache.demand_misses 2931758 # number of demand (read+write) misses
457 system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
458 system.cpu.l2cache.demand_mshr_miss_latency 91454949500 # number of demand (read+write) MSHR miss cycles
459 system.cpu.l2cache.demand_mshr_miss_rate 0.307247 # mshr miss rate for demand accesses
460 system.cpu.l2cache.demand_mshr_misses 2931748 # number of demand (read+write) MSHR misses
461 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
462 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
463 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
464 system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context
465 system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context
466 system.cpu.l2cache.occ_percent::0 0.487988 # Average percentage of cache occupancy
467 system.cpu.l2cache.occ_percent::1 0.329914 # Average percentage of cache occupancy
468 system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses
469 system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency
470 system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
471 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
472 system.cpu.l2cache.overall_hits 6610245 # number of overall hits
473 system.cpu.l2cache.overall_miss_latency 100780059500 # number of overall miss cycles
474 system.cpu.l2cache.overall_miss_rate 0.307248 # miss rate for overall accesses
475 system.cpu.l2cache.overall_misses 2931758 # number of overall misses
476 system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
477 system.cpu.l2cache.overall_mshr_miss_latency 91454949500 # number of overall MSHR miss cycles
478 system.cpu.l2cache.overall_mshr_miss_rate 0.307247 # mshr miss rate for overall accesses
479 system.cpu.l2cache.overall_mshr_misses 2931748 # number of overall MSHR misses
480 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
481 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
482 system.cpu.l2cache.replacements 2919341 # number of replacements
483 system.cpu.l2cache.sampled_refs 2946667 # Sample count of references to valid blocks.
484 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
485 system.cpu.l2cache.tagsinuse 26801.023686 # Cycle average of tags in use
486 system.cpu.l2cache.total_refs 7820318 # Total number of references to valid blocks.
487 system.cpu.l2cache.warmup_cycle 143319905000 # Cycle when the warmup percentage was hit.
488 system.cpu.l2cache.writebacks 1216305 # number of writebacks
489 system.cpu.memDep0.conflictingLoads 95681801 # Number of conflicting loads.
490 system.cpu.memDep0.conflictingStores 90040335 # Number of conflicting stores.
491 system.cpu.memDep0.insertedLoads 626078428 # Number of loads inserted to the mem dependence unit.
492 system.cpu.memDep0.insertedStores 225252424 # Number of stores inserted to the mem dependence unit.
493 system.cpu.misc_regfile_reads 2884001507 # number of misc regfile reads
494 system.cpu.misc_regfile_writes 128 # number of misc regfile writes
495 system.cpu.numCycles 1285781107 # number of cpu cycles simulated
496 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
497 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
498 system.cpu.rename.BlockCycles 67172415 # Number of cycles rename is blocking
499 system.cpu.rename.CommittedMaps 1360917377 # Number of HB maps that are committed
500 system.cpu.rename.IQFullEvents 14851346 # Number of times rename has blocked due to IQ full
501 system.cpu.rename.IdleCycles 600335413 # Number of cycles rename is idle
502 system.cpu.rename.LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full
503 system.cpu.rename.ROBFullEvents 10242 # Number of times rename has blocked due to ROB full
504 system.cpu.rename.RenameLookups 6331353991 # Number of register rename lookups that rename has made
505 system.cpu.rename.RenamedInsts 2292668273 # Number of instructions processed by rename
506 system.cpu.rename.RenamedOperands 1803116545 # Number of destination operands rename has renamed
507 system.cpu.rename.RunCycles 438383597 # Number of cycles rename is running
508 system.cpu.rename.SquashCycles 70439042 # Number of cycles rename is squashing
509 system.cpu.rename.UnblockCycles 60752889 # Number of cycles rename is unblocking
510 system.cpu.rename.UndoneMaps 442199165 # Number of HB maps that are undone due to squashing
511 system.cpu.rename.fp_rename_lookups 393 # Number of floating rename lookups
512 system.cpu.rename.int_rename_lookups 6331353598 # Number of integer rename lookups
513 system.cpu.rename.serializeStallCycles 15610 # count of cycles rename stalled for serializing inst
514 system.cpu.rename.serializingInsts 650 # count of serializing insts renamed
515 system.cpu.rename.skidInsts 118137729 # count of insts added to the skid buffer
516 system.cpu.rename.tempSerializingInsts 645 # count of temporary serializing insts renamed
517 system.cpu.rob.rob_reads 3320275044 # The number of ROB reads
518 system.cpu.rob.rob_writes 4492885352 # The number of ROB writes
519 system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself
520 system.cpu.workload.num_syscalls 46 # Number of system calls
522 ---------- End Simulation Statistics ----------
projects / gem5.git / blob