2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 953941 # Simulator instruction rate (inst/s)
4 host_mem_usage 204484 # Number of bytes of host memory used
5 host_seconds 4877.84 # Real time elapsed on the host
6 host_tick_rate 1564863626 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 4653176258 # Number of instructions simulated
9 sim_seconds 7.633159 # Number of seconds simulated
10 sim_ticks 7633159262000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
54 system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency
55 system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
56 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
57 system.cpu.dcache.overall_hits 1668242528 # number of overall hits
58 system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles
59 system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
60 system.cpu.dcache.overall_misses 9470550 # number of overall misses
61 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
62 system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles
63 system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
64 system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses
65 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
66 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
67 system.cpu.dcache.replacements 9108982 # number of replacements
68 system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
69 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
70 system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use
71 system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
72 system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit.
73 system.cpu.dcache.writebacks 2244013 # number of writebacks
74 system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses)
75 system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
76 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
77 system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits
78 system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
79 system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
80 system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
81 system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
82 system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
83 system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
84 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
85 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
86 system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks.
87 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
88 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
89 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
90 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
91 system.cpu.icache.cache_copies 0 # number of cache copies performed
92 system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses
93 system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
94 system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
95 system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits
96 system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
97 system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
98 system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
99 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
100 system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
101 system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
102 system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
103 system.cpu.icache.fast_writes 0 # number of fast writes performed
104 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
105 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
106 system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses
107 system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
108 system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
109 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
110 system.cpu.icache.overall_hits 5658327439 # number of overall hits
111 system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
112 system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
113 system.cpu.icache.overall_misses 675 # number of overall misses
114 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
115 system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
116 system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
117 system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
118 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
119 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
120 system.cpu.icache.replacements 10 # number of replacements
121 system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
122 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
123 system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use
124 system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks.
125 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
126 system.cpu.icache.writebacks 0 # number of writebacks
127 system.cpu.idle_fraction 0 # Percentage of idle cycles
128 system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses)
129 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
130 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
131 system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles
132 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
133 system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses
134 system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles
135 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
136 system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses
137 system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses)
138 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
139 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
140 system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits
141 system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles
142 system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses
143 system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses
144 system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles
145 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses
146 system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses
147 system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses)
148 system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency
149 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
150 system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles
151 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
152 system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses
153 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles
154 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
155 system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses
156 system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses)
157 system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits
158 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
159 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
160 system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks.
161 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
162 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
163 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
164 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
165 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
166 system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses
167 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
168 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
169 system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits
170 system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles
171 system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses
172 system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses
173 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
174 system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles
175 system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses
176 system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses
177 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
178 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
179 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
180 system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses
181 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
182 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
183 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
184 system.cpu.l2cache.overall_hits 5328546 # number of overall hits
185 system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles
186 system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses
187 system.cpu.l2cache.overall_misses 3785207 # number of overall misses
188 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
189 system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles
190 system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses
191 system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses
192 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
193 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
194 system.cpu.l2cache.replacements 2772128 # number of replacements
195 system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
196 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
197 system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use
198 system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
199 system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit.
200 system.cpu.l2cache.writebacks 1199171 # number of writebacks
201 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
202 system.cpu.numCycles 15266318524 # number of cpu cycles simulated
203 system.cpu.num_insts 4653176258 # Number of instructions executed
204 system.cpu.num_refs 1677713078 # Number of memory references
205 system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
207 ---------- End Simulation Statistics ----------
projects / gem5.git / blob