tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 physmem=system.physmem
  13 work_begin_ckpt_count=0
  14 work_begin_cpu_id_exit=-1
  15 work_begin_exit_count=0
  16 work_cpus_ckpt_count=0
  17 work_end_ckpt_count=0
  18 work_end_exit_count=0
  19 work_item_id=-1
  20
  21 [system.cpu]
  22 type=DerivO3CPU
  23 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  24 BTBEntries=4096
  25 BTBTagSize=16
  26 LFSTSize=1024
  27 LQEntries=32
  28 LSQCheckLoads=true
  29 LSQDepCheckShift=4
  30 RASSize=16
  31 SQEntries=32
  32 SSITSize=1024
  33 activity=0
  34 backComSize=5
  35 cachePorts=200
  36 checker=Null
  37 choiceCtrBits=2
  38 choicePredictorSize=8192
  39 clock=500
  40 commitToDecodeDelay=1
  41 commitToFetchDelay=1
  42 commitToIEWDelay=1
  43 commitToRenameDelay=1
  44 commitWidth=8
  45 cpu_id=0
  46 decodeToFetchDelay=1
  47 decodeToRenameDelay=1
  48 decodeWidth=8
  49 defer_registration=false
  50 dispatchWidth=8
  51 do_checkpoint_insts=true
  52 do_statistics_insts=true
  53 dtb=system.cpu.dtb
  54 fetchToDecodeDelay=1
  55 fetchTrapLatency=1
  56 fetchWidth=8
  57 forwardComSize=5
  58 fuPool=system.cpu.fuPool
  59 function_trace=false
  60 function_trace_start=0
  61 globalCtrBits=2
  62 globalHistoryBits=13
  63 globalPredictorSize=8192
  64 iewToCommitDelay=1
  65 iewToDecodeDelay=1
  66 iewToFetchDelay=1
  67 iewToRenameDelay=1
  68 instShiftAmt=2
  69 issueToExecuteDelay=1
  70 issueWidth=8
  71 itb=system.cpu.itb
  72 localCtrBits=2
  73 localHistoryBits=11
  74 localHistoryTableSize=2048
  75 localPredictorSize=2048
  76 max_insts_all_threads=0
  77 max_insts_any_thread=0
  78 max_loads_all_threads=0
  79 max_loads_any_thread=0
  80 numIQEntries=64
  81 numPhysFloatRegs=256
  82 numPhysIntRegs=256
  83 numROBEntries=192
  84 numRobs=1
  85 numThreads=1
  86 phase=0
  87 predType=tournament
  88 progress_interval=0
  89 renameToDecodeDelay=1
  90 renameToFetchDelay=1
  91 renameToIEWDelay=2
  92 renameToROBDelay=1
  93 renameWidth=8
  94 smtCommitPolicy=RoundRobin
  95 smtFetchPolicy=SingleThread
  96 smtIQPolicy=Partitioned
  97 smtIQThreshold=100
  98 smtLSQPolicy=Partitioned
  99 smtLSQThreshold=100
 100 smtNumFetchingThreads=1
 101 smtROBPolicy=Partitioned
 102 smtROBThreshold=100
 103 squashWidth=8
 104 system=system
 105 tracer=system.cpu.tracer
 106 trapLatency=13
 107 wbDepth=1
 108 wbWidth=8
 109 workload=system.cpu.workload
 110 dcache_port=system.cpu.dcache.cpu_side
 111 icache_port=system.cpu.icache.cpu_side
 112
 113 [system.cpu.dcache]
 114 type=BaseCache
 115 addr_range=0:18446744073709551615
 116 assoc=2
 117 block_size=64
 118 forward_snoops=true
 119 hash_delay=1
 120 is_top_level=true
 121 latency=1000
 122 max_miss_count=0
 123 mshrs=10
 124 num_cpus=1
 125 prefetch_data_accesses_only=false
 126 prefetch_degree=1
 127 prefetch_latency=10000
 128 prefetch_on_access=false
 129 prefetch_past_page=false
 130 prefetch_policy=none
 131 prefetch_serial_squash=false
 132 prefetch_use_cpu_id=true
 133 prefetcher_size=100
 134 prioritizeRequests=false
 135 repl=Null
 136 size=262144
 137 subblock_size=0
 138 tgts_per_mshr=20
 139 trace_addr=0
 140 two_queue=false
 141 write_buffers=8
 142 cpu_side=system.cpu.dcache_port
 143 mem_side=system.cpu.toL2Bus.port[1]
 144
 145 [system.cpu.dtb]
 146 type=ArmTLB
 147 size=64
 148
 149 [system.cpu.fuPool]
 150 type=FUPool
 151 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 152 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 153
 154 [system.cpu.fuPool.FUList0]
 155 type=FUDesc
 156 children=opList
 157 count=6
 158 opList=system.cpu.fuPool.FUList0.opList
 159
 160 [system.cpu.fuPool.FUList0.opList]
 161 type=OpDesc
 162 issueLat=1
 163 opClass=IntAlu
 164 opLat=1
 165
 166 [system.cpu.fuPool.FUList1]
 167 type=FUDesc
 168 children=opList0 opList1
 169 count=2
 170 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 171
 172 [system.cpu.fuPool.FUList1.opList0]
 173 type=OpDesc
 174 issueLat=1
 175 opClass=IntMult
 176 opLat=3
 177
 178 [system.cpu.fuPool.FUList1.opList1]
 179 type=OpDesc
 180 issueLat=19
 181 opClass=IntDiv
 182 opLat=20
 183
 184 [system.cpu.fuPool.FUList2]
 185 type=FUDesc
 186 children=opList0 opList1 opList2
 187 count=4
 188 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 189
 190 [system.cpu.fuPool.FUList2.opList0]
 191 type=OpDesc
 192 issueLat=1
 193 opClass=FloatAdd
 194 opLat=2
 195
 196 [system.cpu.fuPool.FUList2.opList1]
 197 type=OpDesc
 198 issueLat=1
 199 opClass=FloatCmp
 200 opLat=2
 201
 202 [system.cpu.fuPool.FUList2.opList2]
 203 type=OpDesc
 204 issueLat=1
 205 opClass=FloatCvt
 206 opLat=2
 207
 208 [system.cpu.fuPool.FUList3]
 209 type=FUDesc
 210 children=opList0 opList1 opList2
 211 count=2
 212 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 213
 214 [system.cpu.fuPool.FUList3.opList0]
 215 type=OpDesc
 216 issueLat=1
 217 opClass=FloatMult
 218 opLat=4
 219
 220 [system.cpu.fuPool.FUList3.opList1]
 221 type=OpDesc
 222 issueLat=12
 223 opClass=FloatDiv
 224 opLat=12
 225
 226 [system.cpu.fuPool.FUList3.opList2]
 227 type=OpDesc
 228 issueLat=24
 229 opClass=FloatSqrt
 230 opLat=24
 231
 232 [system.cpu.fuPool.FUList4]
 233 type=FUDesc
 234 children=opList
 235 count=0
 236 opList=system.cpu.fuPool.FUList4.opList
 237
 238 [system.cpu.fuPool.FUList4.opList]
 239 type=OpDesc
 240 issueLat=1
 241 opClass=MemRead
 242 opLat=1
 243
 244 [system.cpu.fuPool.FUList5]
 245 type=FUDesc
 246 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 247 count=4
 248 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 249
 250 [system.cpu.fuPool.FUList5.opList00]
 251 type=OpDesc
 252 issueLat=1
 253 opClass=SimdAdd
 254 opLat=1
 255
 256 [system.cpu.fuPool.FUList5.opList01]
 257 type=OpDesc
 258 issueLat=1
 259 opClass=SimdAddAcc
 260 opLat=1
 261
 262 [system.cpu.fuPool.FUList5.opList02]
 263 type=OpDesc
 264 issueLat=1
 265 opClass=SimdAlu
 266 opLat=1
 267
 268 [system.cpu.fuPool.FUList5.opList03]
 269 type=OpDesc
 270 issueLat=1
 271 opClass=SimdCmp
 272 opLat=1
 273
 274 [system.cpu.fuPool.FUList5.opList04]
 275 type=OpDesc
 276 issueLat=1
 277 opClass=SimdCvt
 278 opLat=1
 279
 280 [system.cpu.fuPool.FUList5.opList05]
 281 type=OpDesc
 282 issueLat=1
 283 opClass=SimdMisc
 284 opLat=1
 285
 286 [system.cpu.fuPool.FUList5.opList06]
 287 type=OpDesc
 288 issueLat=1
 289 opClass=SimdMult
 290 opLat=1
 291
 292 [system.cpu.fuPool.FUList5.opList07]
 293 type=OpDesc
 294 issueLat=1
 295 opClass=SimdMultAcc
 296 opLat=1
 297
 298 [system.cpu.fuPool.FUList5.opList08]
 299 type=OpDesc
 300 issueLat=1
 301 opClass=SimdShift
 302 opLat=1
 303
 304 [system.cpu.fuPool.FUList5.opList09]
 305 type=OpDesc
 306 issueLat=1
 307 opClass=SimdShiftAcc
 308 opLat=1
 309
 310 [system.cpu.fuPool.FUList5.opList10]
 311 type=OpDesc
 312 issueLat=1
 313 opClass=SimdSqrt
 314 opLat=1
 315
 316 [system.cpu.fuPool.FUList5.opList11]
 317 type=OpDesc
 318 issueLat=1
 319 opClass=SimdFloatAdd
 320 opLat=1
 321
 322 [system.cpu.fuPool.FUList5.opList12]
 323 type=OpDesc
 324 issueLat=1
 325 opClass=SimdFloatAlu
 326 opLat=1
 327
 328 [system.cpu.fuPool.FUList5.opList13]
 329 type=OpDesc
 330 issueLat=1
 331 opClass=SimdFloatCmp
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList14]
 335 type=OpDesc
 336 issueLat=1
 337 opClass=SimdFloatCvt
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList15]
 341 type=OpDesc
 342 issueLat=1
 343 opClass=SimdFloatDiv
 344 opLat=1
 345
 346 [system.cpu.fuPool.FUList5.opList16]
 347 type=OpDesc
 348 issueLat=1
 349 opClass=SimdFloatMisc
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList17]
 353 type=OpDesc
 354 issueLat=1
 355 opClass=SimdFloatMult
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList18]
 359 type=OpDesc
 360 issueLat=1
 361 opClass=SimdFloatMultAcc
 362 opLat=1
 363
 364 [system.cpu.fuPool.FUList5.opList19]
 365 type=OpDesc
 366 issueLat=1
 367 opClass=SimdFloatSqrt
 368 opLat=1
 369
 370 [system.cpu.fuPool.FUList6]
 371 type=FUDesc
 372 children=opList
 373 count=0
 374 opList=system.cpu.fuPool.FUList6.opList
 375
 376 [system.cpu.fuPool.FUList6.opList]
 377 type=OpDesc
 378 issueLat=1
 379 opClass=MemWrite
 380 opLat=1
 381
 382 [system.cpu.fuPool.FUList7]
 383 type=FUDesc
 384 children=opList0 opList1
 385 count=4
 386 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 387
 388 [system.cpu.fuPool.FUList7.opList0]
 389 type=OpDesc
 390 issueLat=1
 391 opClass=MemRead
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList7.opList1]
 395 type=OpDesc
 396 issueLat=1
 397 opClass=MemWrite
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList8]
 401 type=FUDesc
 402 children=opList
 403 count=1
 404 opList=system.cpu.fuPool.FUList8.opList
 405
 406 [system.cpu.fuPool.FUList8.opList]
 407 type=OpDesc
 408 issueLat=3
 409 opClass=IprAccess
 410 opLat=3
 411
 412 [system.cpu.icache]
 413 type=BaseCache
 414 addr_range=0:18446744073709551615
 415 assoc=2
 416 block_size=64
 417 forward_snoops=true
 418 hash_delay=1
 419 is_top_level=true
 420 latency=1000
 421 max_miss_count=0
 422 mshrs=10
 423 num_cpus=1
 424 prefetch_data_accesses_only=false
 425 prefetch_degree=1
 426 prefetch_latency=10000
 427 prefetch_on_access=false
 428 prefetch_past_page=false
 429 prefetch_policy=none
 430 prefetch_serial_squash=false
 431 prefetch_use_cpu_id=true
 432 prefetcher_size=100
 433 prioritizeRequests=false
 434 repl=Null
 435 size=131072
 436 subblock_size=0
 437 tgts_per_mshr=20
 438 trace_addr=0
 439 two_queue=false
 440 write_buffers=8
 441 cpu_side=system.cpu.icache_port
 442 mem_side=system.cpu.toL2Bus.port[0]
 443
 444 [system.cpu.itb]
 445 type=ArmTLB
 446 size=64
 447
 448 [system.cpu.l2cache]
 449 type=BaseCache
 450 addr_range=0:18446744073709551615
 451 assoc=2
 452 block_size=64
 453 forward_snoops=true
 454 hash_delay=1
 455 is_top_level=false
 456 latency=1000
 457 max_miss_count=0
 458 mshrs=10
 459 num_cpus=1
 460 prefetch_data_accesses_only=false
 461 prefetch_degree=1
 462 prefetch_latency=10000
 463 prefetch_on_access=false
 464 prefetch_past_page=false
 465 prefetch_policy=none
 466 prefetch_serial_squash=false
 467 prefetch_use_cpu_id=true
 468 prefetcher_size=100
 469 prioritizeRequests=false
 470 repl=Null
 471 size=2097152
 472 subblock_size=0
 473 tgts_per_mshr=5
 474 trace_addr=0
 475 two_queue=false
 476 write_buffers=8
 477 cpu_side=system.cpu.toL2Bus.port[2]
 478 mem_side=system.membus.port[1]
 479
 480 [system.cpu.toL2Bus]
 481 type=Bus
 482 block_size=64
 483 bus_id=0
 484 clock=1000
 485 header_cycles=1
 486 use_default_range=false
 487 width=64
 488 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 489
 490 [system.cpu.tracer]
 491 type=ExeTracer
 492
 493 [system.cpu.workload]
 494 type=LiveProcess
 495 cmd=twolf smred
 496 cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
 497 egid=100
 498 env=
 499 errout=cerr
 500 euid=100
 501 executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
 502 gid=100
 503 input=cin
 504 max_stack_size=67108864
 505 output=cout
 506 pid=100
 507 ppid=99
 508 simpoint=0
 509 system=system
 510 uid=100
 511
 512 [system.membus]
 513 type=Bus
 514 block_size=64
 515 bus_id=0
 516 clock=1000
 517 header_cycles=1
 518 use_default_range=false
 519 width=64
 520 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 521
 522 [system.physmem]
 523 type=PhysicalMemory
 524 file=
 525 latency=30000
 526 latency_var=0
 527 null=false
 528 range=0:134217727
 529 zero=false
 530 port=system.membus.port[0]
 531