2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 569972 # Simulator instruction rate (inst/s)
4 host_mem_usage 258100 # Number of bytes of host memory used
5 host_seconds 330.17 # Real time elapsed on the host
6 host_tick_rate 702907358 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 188185929 # Number of instructions simulated
9 sim_seconds 0.232077 # Number of seconds simulated
10 sim_ticks 232077154000 # Number of ticks simulated
11 system.cpu.dcache.LoadLockedReq_accesses 22407 # number of LoadLockedReq accesses(hits+misses)
12 system.cpu.dcache.LoadLockedReq_hits 22407 # number of LoadLockedReq hits
13 system.cpu.dcache.ReadReq_accesses 29600047 # number of ReadReq accesses(hits+misses)
14 system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129 # average ReadReq miss latency
15 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129 # average ReadReq mshr miss latency
16 system.cpu.dcache.ReadReq_hits 29599358 # number of ReadReq hits
17 system.cpu.dcache.ReadReq_miss_latency 36190000 # number of ReadReq miss cycles
18 system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses
19 system.cpu.dcache.ReadReq_misses 689 # number of ReadReq misses
20 system.cpu.dcache.ReadReq_mshr_miss_latency 34123000 # number of ReadReq MSHR miss cycles
21 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses
22 system.cpu.dcache.ReadReq_mshr_misses 689 # number of ReadReq MSHR misses
23 system.cpu.dcache.StoreCondReq_accesses 22407 # number of StoreCondReq accesses(hits+misses)
24 system.cpu.dcache.StoreCondReq_hits 22407 # number of StoreCondReq hits
25 system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
26 system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency
27 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency
28 system.cpu.dcache.WriteReq_hits 12363187 # number of WriteReq hits
29 system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles
30 system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses
31 system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses
32 system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles
33 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
34 system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses
35 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
36 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
37 system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks.
38 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
39 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
40 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
41 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
42 system.cpu.dcache.cache_copies 0 # number of cache copies performed
43 system.cpu.dcache.demand_accesses 41964334 # number of demand (read+write) accesses
44 system.cpu.dcache.demand_avg_miss_latency 54474.007826 # average overall miss latency
45 system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency
46 system.cpu.dcache.demand_hits 41962545 # number of demand (read+write) hits
47 system.cpu.dcache.demand_miss_latency 97454000 # number of demand (read+write) miss cycles
48 system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses
49 system.cpu.dcache.demand_misses 1789 # number of demand (read+write) misses
50 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
51 system.cpu.dcache.demand_mshr_miss_latency 92087000 # number of demand (read+write) MSHR miss cycles
52 system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
53 system.cpu.dcache.demand_mshr_misses 1789 # number of demand (read+write) MSHR misses
54 system.cpu.dcache.fast_writes 0 # number of fast writes performed
55 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
56 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
57 system.cpu.dcache.occ_%::0 0.332911 # Average percentage of cache occupancy
58 system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context
59 system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses
60 system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency
61 system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency
62 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
63 system.cpu.dcache.overall_hits 41962545 # number of overall hits
64 system.cpu.dcache.overall_miss_latency 97454000 # number of overall miss cycles
65 system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses
66 system.cpu.dcache.overall_misses 1789 # number of overall misses
67 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
68 system.cpu.dcache.overall_mshr_miss_latency 92087000 # number of overall MSHR miss cycles
69 system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
70 system.cpu.dcache.overall_mshr_misses 1789 # number of overall MSHR misses
71 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
72 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
73 system.cpu.dcache.replacements 40 # number of replacements
74 system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
75 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
76 system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use
77 system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks.
78 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
79 system.cpu.dcache.writebacks 16 # number of writebacks
80 system.cpu.dtb.accesses 0 # DTB accesses
81 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
83 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
84 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
85 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
86 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
87 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
88 system.cpu.dtb.hits 0 # DTB hits
89 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
90 system.cpu.dtb.inst_hits 0 # ITB inst hits
91 system.cpu.dtb.inst_misses 0 # ITB inst misses
92 system.cpu.dtb.misses 0 # DTB misses
93 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
94 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
95 system.cpu.dtb.read_accesses 0 # DTB read accesses
96 system.cpu.dtb.read_hits 0 # DTB read hits
97 system.cpu.dtb.read_misses 0 # DTB read misses
98 system.cpu.dtb.write_accesses 0 # DTB write accesses
99 system.cpu.dtb.write_hits 0 # DTB write hits
100 system.cpu.dtb.write_misses 0 # DTB write misses
101 system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses)
102 system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency
103 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency
104 system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits
105 system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles
106 system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
107 system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses
108 system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles
109 system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses
110 system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses
111 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
112 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
113 system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks.
114 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
115 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
116 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
117 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
118 system.cpu.icache.cache_copies 0 # number of cache copies performed
119 system.cpu.icache.demand_accesses 189860061 # number of demand (read+write) accesses
120 system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency
121 system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
122 system.cpu.icache.demand_hits 189857010 # number of demand (read+write) hits
123 system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles
124 system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
125 system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses
126 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
127 system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles
128 system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses
129 system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses
130 system.cpu.icache.fast_writes 0 # number of fast writes performed
131 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
132 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
133 system.cpu.icache.occ_%::0 0.560538 # Average percentage of cache occupancy
134 system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context
135 system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses
136 system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
137 system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
138 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
139 system.cpu.icache.overall_hits 189857010 # number of overall hits
140 system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles
141 system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
142 system.cpu.icache.overall_misses 3051 # number of overall misses
143 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
144 system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles
145 system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses
146 system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses
147 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
148 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
149 system.cpu.icache.replacements 1506 # number of replacements
150 system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
151 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
152 system.cpu.icache.tagsinuse 1147.981155 # Cycle average of tags in use
153 system.cpu.icache.total_refs 189857010 # Total number of references to valid blocks.
154 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
155 system.cpu.icache.writebacks 0 # number of writebacks
156 system.cpu.idle_fraction 0 # Percentage of idle cycles
157 system.cpu.itb.accesses 0 # DTB accesses
158 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
159 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
160 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
161 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
162 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
163 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
164 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
165 system.cpu.itb.hits 0 # DTB hits
166 system.cpu.itb.inst_accesses 0 # ITB inst accesses
167 system.cpu.itb.inst_hits 0 # ITB inst hits
168 system.cpu.itb.inst_misses 0 # ITB inst misses
169 system.cpu.itb.misses 0 # DTB misses
170 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
171 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
172 system.cpu.itb.read_accesses 0 # DTB read accesses
173 system.cpu.itb.read_hits 0 # DTB read hits
174 system.cpu.itb.read_misses 0 # DTB read misses
175 system.cpu.itb.write_accesses 0 # DTB write accesses
176 system.cpu.itb.write_hits 0 # DTB write hits
177 system.cpu.itb.write_misses 0 # DTB write misses
178 system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses)
179 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
180 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
181 system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
182 system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles
183 system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses
184 system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses
185 system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles
186 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses
187 system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses
188 system.cpu.l2cache.ReadReq_accesses 3740 # number of ReadReq accesses(hits+misses)
189 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
190 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
191 system.cpu.l2cache.ReadReq_hits 1379 # number of ReadReq hits
192 system.cpu.l2cache.ReadReq_miss_latency 122772000 # number of ReadReq miss cycles
193 system.cpu.l2cache.ReadReq_miss_rate 0.631283 # miss rate for ReadReq accesses
194 system.cpu.l2cache.ReadReq_misses 2361 # number of ReadReq misses
195 system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles
196 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631283 # mshr miss rate for ReadReq accesses
197 system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses
198 system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
199 system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
200 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
201 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
202 system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks.
203 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
204 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
205 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
206 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
207 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
208 system.cpu.l2cache.demand_accesses 4840 # number of demand (read+write) accesses
209 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
210 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
211 system.cpu.l2cache.demand_hits 1387 # number of demand (read+write) hits
212 system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles
213 system.cpu.l2cache.demand_miss_rate 0.713430 # miss rate for demand accesses
214 system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses
215 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
216 system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles
217 system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses
218 system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses
219 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
220 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
221 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
222 system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy
223 system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy
224 system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context
225 system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context
226 system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses
227 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
228 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
229 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
230 system.cpu.l2cache.overall_hits 1387 # number of overall hits
231 system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles
232 system.cpu.l2cache.overall_miss_rate 0.713430 # miss rate for overall accesses
233 system.cpu.l2cache.overall_misses 3453 # number of overall misses
234 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
235 system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles
236 system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses
237 system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses
238 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
239 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
240 system.cpu.l2cache.replacements 0 # number of replacements
241 system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
242 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
243 system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use
244 system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
245 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
246 system.cpu.l2cache.writebacks 0 # number of writebacks
247 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
248 system.cpu.numCycles 464154308 # number of cpu cycles simulated
249 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
250 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
251 system.cpu.num_busy_cycles 464154308 # Number of busy cycles
252 system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls
253 system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
254 system.cpu.num_fp_insts 1752310 # number of float instructions
255 system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
256 system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
257 system.cpu.num_func_calls 3504894 # number of times a function call or return occured
258 system.cpu.num_idle_cycles 0 # Number of idle cycles
259 system.cpu.num_insts 188185929 # Number of instructions executed
260 system.cpu.num_int_alu_accesses 150261055 # Number of integer alu accesses
261 system.cpu.num_int_insts 150261055 # number of integer instructions
262 system.cpu.num_int_register_reads 474507625 # number of times the integer registers were read
263 system.cpu.num_int_register_writes 177007633 # number of times the integer registers were written
264 system.cpu.num_load_insts 29849485 # Number of load instructions
265 system.cpu.num_mem_refs 42494120 # number of memory refs
266 system.cpu.num_store_insts 12644635 # Number of store instructions
267 system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
269 ---------- End Simulation Statistics ----------
projects / gem5.git / blob