tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=TimingSimpleCPU
  14 children=dcache icache l2cache toL2Bus workload
  15 clock=500
  16 cpu_id=0
  17 defer_registration=false
  18 function_trace=false
  19 function_trace_start=0
  20 max_insts_all_threads=0
  21 max_insts_any_thread=0
  22 max_loads_all_threads=0
  23 max_loads_any_thread=0
  24 phase=0
  25 progress_interval=0
  26 system=system
  27 workload=system.cpu.workload
  28 dcache_port=system.cpu.dcache.cpu_side
  29 icache_port=system.cpu.icache.cpu_side
  30
  31 [system.cpu.dcache]
  32 type=BaseCache
  33 adaptive_compression=false
  34 assoc=2
  35 block_size=64
  36 compressed_bus=false
  37 compression_latency=0
  38 hash_delay=1
  39 latency=1000
  40 lifo=false
  41 max_miss_count=0
  42 mshrs=10
  43 prefetch_access=false
  44 prefetch_cache_check_push=true
  45 prefetch_data_accesses_only=false
  46 prefetch_degree=1
  47 prefetch_latency=10
  48 prefetch_miss=false
  49 prefetch_past_page=false
  50 prefetch_policy=none
  51 prefetch_serial_squash=false
  52 prefetch_use_cpu_id=true
  53 prefetcher_size=100
  54 prioritizeRequests=false
  55 protocol=Null
  56 repl=Null
  57 size=262144
  58 split=false
  59 split_size=0
  60 store_compressed=false
  61 subblock_size=0
  62 tgts_per_mshr=5
  63 trace_addr=0
  64 two_queue=false
  65 write_buffers=8
  66 cpu_side=system.cpu.dcache_port
  67 mem_side=system.cpu.toL2Bus.port[1]
  68
  69 [system.cpu.icache]
  70 type=BaseCache
  71 adaptive_compression=false
  72 assoc=2
  73 block_size=64
  74 compressed_bus=false
  75 compression_latency=0
  76 hash_delay=1
  77 latency=1000
  78 lifo=false
  79 max_miss_count=0
  80 mshrs=10
  81 prefetch_access=false
  82 prefetch_cache_check_push=true
  83 prefetch_data_accesses_only=false
  84 prefetch_degree=1
  85 prefetch_latency=10
  86 prefetch_miss=false
  87 prefetch_past_page=false
  88 prefetch_policy=none
  89 prefetch_serial_squash=false
  90 prefetch_use_cpu_id=true
  91 prefetcher_size=100
  92 prioritizeRequests=false
  93 protocol=Null
  94 repl=Null
  95 size=131072
  96 split=false
  97 split_size=0
  98 store_compressed=false
  99 subblock_size=0
 100 tgts_per_mshr=5
 101 trace_addr=0
 102 two_queue=false
 103 write_buffers=8
 104 cpu_side=system.cpu.icache_port
 105 mem_side=system.cpu.toL2Bus.port[0]
 106
 107 [system.cpu.l2cache]
 108 type=BaseCache
 109 adaptive_compression=false
 110 assoc=2
 111 block_size=64
 112 compressed_bus=false
 113 compression_latency=0
 114 hash_delay=1
 115 latency=10000
 116 lifo=false
 117 max_miss_count=0
 118 mshrs=10
 119 prefetch_access=false
 120 prefetch_cache_check_push=true
 121 prefetch_data_accesses_only=false
 122 prefetch_degree=1
 123 prefetch_latency=10
 124 prefetch_miss=false
 125 prefetch_past_page=false
 126 prefetch_policy=none
 127 prefetch_serial_squash=false
 128 prefetch_use_cpu_id=true
 129 prefetcher_size=100
 130 prioritizeRequests=false
 131 protocol=Null
 132 repl=Null
 133 size=2097152
 134 split=false
 135 split_size=0
 136 store_compressed=false
 137 subblock_size=0
 138 tgts_per_mshr=5
 139 trace_addr=0
 140 two_queue=false
 141 write_buffers=8
 142 cpu_side=system.cpu.toL2Bus.port[2]
 143 mem_side=system.membus.port[1]
 144
 145 [system.cpu.toL2Bus]
 146 type=Bus
 147 block_size=64
 148 bus_id=0
 149 clock=1000
 150 responder_set=false
 151 width=64
 152 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 153
 154 [system.cpu.workload]
 155 type=LiveProcess
 156 cmd=twolf smred
 157 cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 158 egid=100
 159 env=
 160 euid=100
 161 executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
 162 gid=100
 163 input=cin
 164 output=cout
 165 pid=100
 166 ppid=99
 167 system=system
 168 uid=100
 169
 170 [system.membus]
 171 type=Bus
 172 block_size=64
 173 bus_id=0
 174 clock=1000
 175 responder_set=false
 176 width=64
 177 port=system.physmem.port system.cpu.l2cache.mem_side
 178
 179 [system.physmem]
 180 type=PhysicalMemory
 181 file=
 182 latency=1
 183 range=0:134217727
 184 zero=false
 185 port=system.membus.port[0]
 186