2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 500598 # Simulator instruction rate (inst/s)
4 host_mem_usage 156000 # Number of bytes of host memory used
5 host_seconds 386.41 # Real time elapsed on the host
6 host_tick_rate 699597163 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 193435973 # Number of instructions simulated
9 sim_seconds 0.270332 # Number of seconds simulated
10 sim_ticks 270331639000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
21 system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
22 system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency
23 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency
24 system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
25 system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles
26 system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
27 system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
28 system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles
29 system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
30 system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
31 system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
32 system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency
33 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency
34 system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits
35 system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles
36 system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
37 system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses
38 system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles
39 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
40 system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses
41 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
42 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
43 system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks.
44 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
45 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
46 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
47 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
48 system.cpu.dcache.cache_copies 0 # number of cache copies performed
49 system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
50 system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency
51 system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
52 system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits
53 system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles
54 system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
55 system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses
56 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
57 system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles
58 system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
59 system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses
60 system.cpu.dcache.fast_writes 0 # number of fast writes performed
61 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
62 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
63 system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
64 system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency
65 system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
66 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
67 system.cpu.dcache.overall_hits 76708968 # number of overall hits
68 system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles
69 system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
70 system.cpu.dcache.overall_misses 1584 # number of overall misses
71 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
72 system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles
73 system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
74 system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses
75 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
76 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
77 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
78 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
79 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
80 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
81 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
82 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
83 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
84 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
85 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
86 system.cpu.dcache.replacements 26 # number of replacements
87 system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
88 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
89 system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use
90 system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
91 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
92 system.cpu.dcache.writebacks 23 # number of writebacks
93 system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses)
94 system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency
95 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency
96 system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits
97 system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles
98 system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
99 system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
100 system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles
101 system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
102 system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
103 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
104 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
105 system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks.
106 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
107 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
108 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
109 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
110 system.cpu.icache.cache_copies 0 # number of cache copies performed
111 system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses
112 system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency
113 system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
114 system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits
115 system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles
116 system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
117 system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
118 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
119 system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles
120 system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
121 system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
122 system.cpu.icache.fast_writes 0 # number of fast writes performed
123 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
124 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
125 system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses
126 system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency
127 system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
128 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
129 system.cpu.icache.overall_hits 193423706 # number of overall hits
130 system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles
131 system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
132 system.cpu.icache.overall_misses 12268 # number of overall misses
133 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
134 system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles
135 system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
136 system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
137 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
138 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
139 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
140 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
141 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
142 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
143 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
144 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
145 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
146 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
147 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
148 system.cpu.icache.replacements 10342 # number of replacements
149 system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
150 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
151 system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use
152 system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks.
153 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
154 system.cpu.icache.writebacks 0 # number of writebacks
155 system.cpu.idle_fraction 0 # Percentage of idle cycles
156 system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses)
157 system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
158 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
159 system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits
160 system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles
161 system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses
162 system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses
163 system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles
164 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses
165 system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses
166 system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
167 system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits
168 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
169 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
170 system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks.
171 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
172 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
173 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
174 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
175 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
176 system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses
177 system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
178 system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
179 system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits
180 system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles
181 system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses
182 system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses
183 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
184 system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles
185 system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses
186 system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses
187 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
188 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
189 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
190 system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses
191 system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
192 system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
193 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
194 system.cpu.l2cache.overall_hits 8708 # number of overall hits
195 system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles
196 system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses
197 system.cpu.l2cache.overall_misses 5167 # number of overall misses
198 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
199 system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles
200 system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses
201 system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses
202 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
203 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
204 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
205 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
206 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
207 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
208 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
209 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
210 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
211 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
212 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
213 system.cpu.l2cache.replacements 0 # number of replacements
214 system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks.
215 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
216 system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use
217 system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks.
218 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
219 system.cpu.l2cache.writebacks 0 # number of writebacks
220 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
221 system.cpu.numCycles 270331639000 # number of cpu cycles simulated
222 system.cpu.num_insts 193435973 # Number of instructions executed
223 system.cpu.num_refs 76732959 # Number of memory references
224 system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
226 ---------- End Simulation Statistics ----------
projects / gem5.git / blob