2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 732316 # Simulator instruction rate (inst/s)
4 host_mem_usage 209324 # Number of bytes of host memory used
5 host_seconds 264.15 # Real time elapsed on the host
6 host_tick_rate 1024317022 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 193444769 # Number of instructions simulated
9 sim_seconds 0.270578 # Number of seconds simulated
10 sim_ticks 270578335000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
21 system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
22 system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
23 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
24 system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
25 system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles
26 system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
27 system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
28 system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles
29 system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
30 system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
31 system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
32 system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
33 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
34 system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits
35 system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
36 system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
37 system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
38 system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
39 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
40 system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
41 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
42 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
43 system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
44 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
45 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
46 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
47 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
48 system.cpu.dcache.cache_copies 0 # number of cache copies performed
49 system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
50 system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
51 system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
52 system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits
53 system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles
54 system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
55 system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses
56 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
57 system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles
58 system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
59 system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses
60 system.cpu.dcache.fast_writes 0 # number of fast writes performed
61 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
62 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
63 system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
64 system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
65 system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
66 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
67 system.cpu.dcache.overall_hits 76709909 # number of overall hits
68 system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles
69 system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
70 system.cpu.dcache.overall_misses 1599 # number of overall misses
71 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
72 system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles
73 system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
74 system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses
75 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
76 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
77 system.cpu.dcache.replacements 2 # number of replacements
78 system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
79 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
80 system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use
81 system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
82 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
83 system.cpu.dcache.writebacks 2 # number of writebacks
84 system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses)
85 system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
86 system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
87 system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits
88 system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
89 system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
90 system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
91 system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
92 system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
93 system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
94 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
95 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
96 system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks.
97 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
98 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
99 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
100 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
101 system.cpu.icache.cache_copies 0 # number of cache copies performed
102 system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses
103 system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
104 system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
105 system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits
106 system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
107 system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
108 system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
109 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
110 system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
111 system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
112 system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
113 system.cpu.icache.fast_writes 0 # number of fast writes performed
114 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
115 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
116 system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses
117 system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
118 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
119 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
120 system.cpu.icache.overall_hits 193433261 # number of overall hits
121 system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
122 system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
123 system.cpu.icache.overall_misses 12288 # number of overall misses
124 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
125 system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
126 system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
127 system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
128 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
129 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
130 system.cpu.icache.replacements 10362 # number of replacements
131 system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
132 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
133 system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use
134 system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks.
135 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136 system.cpu.icache.writebacks 0 # number of writebacks
137 system.cpu.idle_fraction 0 # Percentage of idle cycles
138 system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses)
139 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
140 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
141 system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles
142 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
143 system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses
144 system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
145 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
146 system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
147 system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
148 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
149 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
150 system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits
151 system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles
152 system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses
153 system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses
154 system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
155 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
156 system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
157 system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
158 system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
159 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
160 system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles
161 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
162 system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
163 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
164 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
165 system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
166 system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
167 system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
168 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
169 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
170 system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks.
171 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
172 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
173 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
174 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
175 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
176 system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses
177 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
178 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
179 system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
180 system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles
181 system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses
182 system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses
183 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
184 system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
185 system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
186 system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
187 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
188 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
189 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
190 system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
191 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
192 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
193 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
194 system.cpu.l2cache.overall_hits 8691 # number of overall hits
195 system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles
196 system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses
197 system.cpu.l2cache.overall_misses 5173 # number of overall misses
198 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
199 system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
200 system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
201 system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
202 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
203 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
204 system.cpu.l2cache.replacements 0 # number of replacements
205 system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks.
206 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
207 system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use
208 system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
209 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
210 system.cpu.l2cache.writebacks 0 # number of writebacks
211 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
212 system.cpu.numCycles 541156670 # number of cpu cycles simulated
213 system.cpu.num_insts 193444769 # Number of instructions executed
214 system.cpu.num_refs 76733959 # Number of memory references
215 system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
217 ---------- End Simulation Statistics ----------
projects / gem5.git / blob