8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
14 boot_cpu_frequency=500
15 boot_osflags=root=/dev/hda1 console=ttyS0
17 clk_domain=system.clk_domain
18 console=/dist/binaries/console
21 kernel=/dist/binaries/vmlinux
22 kernel_addr_check=true
23 load_addr_mask=1099511627775
26 mem_ranges=0:134217727
27 memories=system.physmem
29 pal=/dist/binaries/ts_osfpal
30 readfile=/work/gem5.latest/tests/halt.sh
34 work_begin_ckpt_count=0
35 work_begin_cpu_id_exit=-1
36 work_begin_exit_count=0
37 work_cpus_ckpt_count=0
41 system_port=system.membus.slave[0]
45 clk_domain=system.clk_domain
48 ranges=8796093022208:18446744073709551615
51 master=system.iobus.slave[0]
52 slave=system.membus.master[0]
60 voltage_domain=system.voltage_domain
64 children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer
65 branchPred=system.cpu.branchPred
67 clk_domain=system.cpu_clk_domain
70 decodeInputBufferSize=3
72 decodeToExecuteForwardDelay=1
73 do_checkpoint_insts=true
75 do_statistics_insts=true
79 executeAllowEarlyMemoryIssue=true
82 executeCycleInput=true
83 executeFuncUnits=system.cpu.executeFuncUnits
84 executeInputBufferSize=7
87 executeLSQMaxStoreBufferStoresPerCycle=2
88 executeLSQRequestsQueueSize=1
89 executeLSQStoreBufferSize=5
90 executeLSQTransfersQueueSize=2
91 executeMaxAccessesInMemory=2
92 executeMemoryCommitLimit=1
93 executeMemoryIssueLimit=1
95 executeSetTraceTimeOnCommit=true
96 executeSetTraceTimeOnIssue=false
100 fetch1ToFetch2BackwardDelay=1
101 fetch1ToFetch2ForwardDelay=1
102 fetch2CycleInput=true
103 fetch2InputBufferSize=2
104 fetch2ToDecodeForwardDelay=1
106 function_trace_start=0
107 interrupts=system.cpu.interrupts
110 max_insts_all_threads=0
111 max_insts_any_thread=0
112 max_loads_all_threads=0
113 max_loads_any_thread=0
117 simpoint_start_insts=
121 tracer=system.cpu.tracer
123 dcache_port=system.cpu.dcache.cpu_side
124 icache_port=system.cpu.icache.cpu_side
126 [system.cpu.branchPred]
132 choicePredictorSize=8192
135 globalPredictorSize=8192
138 localHistoryTableSize=2048
139 localPredictorSize=2048
146 addr_ranges=0:18446744073709551615
148 clk_domain=system.cpu_clk_domain
149 demand_mshr_reserve=1
156 prefetch_on_access=false
159 sequential_access=false
162 tags=system.cpu.dcache.tags
166 cpu_side=system.cpu.dcache_port
167 mem_side=system.cpu.toL2Bus.slave[1]
169 [system.cpu.dcache.tags]
173 clk_domain=system.cpu_clk_domain
176 sequential_access=false
184 [system.cpu.executeFuncUnits]
186 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
188 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
190 [system.cpu.executeFuncUnits.funcUnits0]
192 children=opClasses timings
193 cantForwardFromFUIndices=
196 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
198 timings=system.cpu.executeFuncUnits.funcUnits0.timings
200 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
204 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
206 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
211 [system.cpu.executeFuncUnits.funcUnits0.timings]
218 extraCommitLatExpr=Null
221 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
222 srcRegsRelativeLats=2
225 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
230 [system.cpu.executeFuncUnits.funcUnits1]
232 children=opClasses timings
233 cantForwardFromFUIndices=
236 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
238 timings=system.cpu.executeFuncUnits.funcUnits1.timings
240 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
244 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
246 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
251 [system.cpu.executeFuncUnits.funcUnits1.timings]
258 extraCommitLatExpr=Null
261 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
262 srcRegsRelativeLats=2
265 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
270 [system.cpu.executeFuncUnits.funcUnits2]
272 children=opClasses timings
273 cantForwardFromFUIndices=
276 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
278 timings=system.cpu.executeFuncUnits.funcUnits2.timings
280 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
284 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
286 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
291 [system.cpu.executeFuncUnits.funcUnits2.timings]
298 extraCommitLatExpr=Null
301 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
302 srcRegsRelativeLats=0
305 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
310 [system.cpu.executeFuncUnits.funcUnits3]
313 cantForwardFromFUIndices=
316 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
320 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
324 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
326 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
331 [system.cpu.executeFuncUnits.funcUnits4]
333 children=opClasses timings
334 cantForwardFromFUIndices=
337 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
339 timings=system.cpu.executeFuncUnits.funcUnits4.timings
341 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
343 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
345 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
347 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
352 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
357 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
362 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
367 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
372 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
377 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
382 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
387 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
392 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
397 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
402 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
407 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
412 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
417 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
422 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
427 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
432 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
437 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
442 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
447 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
452 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
457 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
460 opClass=SimdFloatMisc
462 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
465 opClass=SimdFloatMult
467 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
470 opClass=SimdFloatMultAcc
472 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
475 opClass=SimdFloatSqrt
477 [system.cpu.executeFuncUnits.funcUnits4.timings]
480 description=FloatSimd
484 extraCommitLatExpr=Null
487 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
488 srcRegsRelativeLats=2
491 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
496 [system.cpu.executeFuncUnits.funcUnits5]
498 children=opClasses timings
499 cantForwardFromFUIndices=
502 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
504 timings=system.cpu.executeFuncUnits.funcUnits5.timings
506 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
508 children=opClasses0 opClasses1
510 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
512 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
517 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
522 [system.cpu.executeFuncUnits.funcUnits5.timings]
529 extraCommitLatExpr=Null
532 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
533 srcRegsRelativeLats=1
536 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
541 [system.cpu.executeFuncUnits.funcUnits6]
544 cantForwardFromFUIndices=
547 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
551 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
553 children=opClasses0 opClasses1
555 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
557 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
562 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
570 addr_ranges=0:18446744073709551615
572 clk_domain=system.cpu_clk_domain
573 demand_mshr_reserve=1
580 prefetch_on_access=false
583 sequential_access=false
586 tags=system.cpu.icache.tags
590 cpu_side=system.cpu.icache_port
591 mem_side=system.cpu.toL2Bus.slave[0]
593 [system.cpu.icache.tags]
597 clk_domain=system.cpu_clk_domain
600 sequential_access=false
603 [system.cpu.interrupts]
620 addr_ranges=0:18446744073709551615
622 clk_domain=system.cpu_clk_domain
623 demand_mshr_reserve=1
630 prefetch_on_access=false
633 sequential_access=false
636 tags=system.cpu.l2cache.tags
640 cpu_side=system.cpu.toL2Bus.master[0]
641 mem_side=system.membus.slave[1]
643 [system.cpu.l2cache.tags]
647 clk_domain=system.cpu_clk_domain
650 sequential_access=false
655 clk_domain=system.cpu_clk_domain
660 use_default_range=false
662 master=system.cpu.l2cache.cpu_side
663 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
669 [system.cpu_clk_domain]
675 voltage_domain=system.voltage_domain
683 image=system.disk0.image
688 child=system.disk0.image.child
694 [system.disk0.image.child]
697 image_file=/dist/disks/linux-latest.img
706 image=system.disk2.image
711 child=system.disk2.image.child
717 [system.disk2.image.child]
720 image_file=/dist/disks/linux-bigswap2.img
723 [system.dvfs_handler]
728 sys_clk_domain=system.clk_domain
729 transition_latency=100000000
738 clk_domain=system.clk_domain
741 use_default_range=true
743 default=system.tsunami.pciconfig.pio
744 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
745 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
750 addr_ranges=0:134217727
752 clk_domain=system.clk_domain
753 demand_mshr_reserve=1
760 prefetch_on_access=false
763 sequential_access=false
766 tags=system.iocache.tags
770 cpu_side=system.iobus.master[29]
771 mem_side=system.membus.slave[2]
773 [system.iocache.tags]
777 clk_domain=system.clk_domain
780 sequential_access=false
785 children=badaddr_responder
786 clk_domain=system.clk_domain
791 use_default_range=false
793 default=system.membus.badaddr_responder.pio
794 master=system.bridge.slave system.physmem.port
795 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
797 [system.membus.badaddr_responder]
799 clk_domain=system.clk_domain
807 ret_data32=4294967295
808 ret_data64=18446744073709551615
813 pio=system.membus.default
842 addr_mapping=RoRaBaChCo
843 bank_groups_per_rank=0
847 clk_domain=system.clk_domain
848 conf_table_reported=true
850 device_rowbuffer_size=1024
851 device_size=536870912
856 max_accesses_per_row=16
857 mem_sched_policy=frfcfs
858 min_writes_per_switch=16
860 page_policy=open_adaptive
864 static_backend_latency=10000
865 static_frontend_latency=10000
888 write_high_thresh_perc=85
889 write_low_thresh_perc=50
890 port=system.membus.master[1]
895 disk=system.simple_disk.disk
899 [system.simple_disk.disk]
902 image_file=/dist/disks/linux-latest.img
908 intr_control=system.intrctrl
915 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
917 intrctrl=system.intrctrl
920 [system.tsunami.backdoor]
922 clk_domain=system.clk_domain
924 disk=system.simple_disk
926 pio_addr=8804682956800
928 platform=system.tsunami
930 terminal=system.terminal
931 pio=system.iobus.master[24]
933 [system.tsunami.cchip]
935 clk_domain=system.clk_domain
937 pio_addr=8803072344064
940 tsunami=system.tsunami
941 pio=system.iobus.master[0]
943 [system.tsunami.ethernet]
983 MSICAPNextCapability=0
987 MSIXCAPNextCapability=0
997 PMCAPNextCapability=0
1002 PXCAPDevCapabilities=0
1009 PXCAPNextCapability=0
1017 clk_domain=system.clk_domain
1018 config_latency=20000
1021 dma_no_allocate=true
1027 hardware_address=00:90:00:00:00:01
1033 platform=system.tsunami
1043 config=system.iobus.master[28]
1044 dma=system.iobus.slave[2]
1045 pio=system.iobus.master[27]
1047 [system.tsunami.fake_OROM]
1049 clk_domain=system.clk_domain
1052 pio_addr=8796093677568
1057 ret_data32=4294967295
1058 ret_data64=18446744073709551615
1063 pio=system.iobus.master[8]
1065 [system.tsunami.fake_ata0]
1067 clk_domain=system.clk_domain
1070 pio_addr=8804615848432
1075 ret_data32=4294967295
1076 ret_data64=18446744073709551615
1081 pio=system.iobus.master[19]
1083 [system.tsunami.fake_ata1]
1085 clk_domain=system.clk_domain
1088 pio_addr=8804615848304
1093 ret_data32=4294967295
1094 ret_data64=18446744073709551615
1099 pio=system.iobus.master[20]
1101 [system.tsunami.fake_pnp_addr]
1103 clk_domain=system.clk_domain
1106 pio_addr=8804615848569
1111 ret_data32=4294967295
1112 ret_data64=18446744073709551615
1117 pio=system.iobus.master[9]
1119 [system.tsunami.fake_pnp_read0]
1121 clk_domain=system.clk_domain
1124 pio_addr=8804615848451
1129 ret_data32=4294967295
1130 ret_data64=18446744073709551615
1135 pio=system.iobus.master[11]
1137 [system.tsunami.fake_pnp_read1]
1139 clk_domain=system.clk_domain
1142 pio_addr=8804615848515
1147 ret_data32=4294967295
1148 ret_data64=18446744073709551615
1153 pio=system.iobus.master[12]
1155 [system.tsunami.fake_pnp_read2]
1157 clk_domain=system.clk_domain
1160 pio_addr=8804615848579
1165 ret_data32=4294967295
1166 ret_data64=18446744073709551615
1171 pio=system.iobus.master[13]
1173 [system.tsunami.fake_pnp_read3]
1175 clk_domain=system.clk_domain
1178 pio_addr=8804615848643
1183 ret_data32=4294967295
1184 ret_data64=18446744073709551615
1189 pio=system.iobus.master[14]
1191 [system.tsunami.fake_pnp_read4]
1193 clk_domain=system.clk_domain
1196 pio_addr=8804615848707
1201 ret_data32=4294967295
1202 ret_data64=18446744073709551615
1207 pio=system.iobus.master[15]
1209 [system.tsunami.fake_pnp_read5]
1211 clk_domain=system.clk_domain
1214 pio_addr=8804615848771
1219 ret_data32=4294967295
1220 ret_data64=18446744073709551615
1225 pio=system.iobus.master[16]
1227 [system.tsunami.fake_pnp_read6]
1229 clk_domain=system.clk_domain
1232 pio_addr=8804615848835
1237 ret_data32=4294967295
1238 ret_data64=18446744073709551615
1243 pio=system.iobus.master[17]
1245 [system.tsunami.fake_pnp_read7]
1247 clk_domain=system.clk_domain
1250 pio_addr=8804615848899
1255 ret_data32=4294967295
1256 ret_data64=18446744073709551615
1261 pio=system.iobus.master[18]
1263 [system.tsunami.fake_pnp_write]
1265 clk_domain=system.clk_domain
1268 pio_addr=8804615850617
1273 ret_data32=4294967295
1274 ret_data64=18446744073709551615
1279 pio=system.iobus.master[10]
1281 [system.tsunami.fake_ppc]
1283 clk_domain=system.clk_domain
1286 pio_addr=8804615848891
1291 ret_data32=4294967295
1292 ret_data64=18446744073709551615
1297 pio=system.iobus.master[7]
1299 [system.tsunami.fake_sm_chip]
1301 clk_domain=system.clk_domain
1304 pio_addr=8804615848816
1309 ret_data32=4294967295
1310 ret_data64=18446744073709551615
1315 pio=system.iobus.master[2]
1317 [system.tsunami.fake_uart1]
1319 clk_domain=system.clk_domain
1322 pio_addr=8804615848696
1327 ret_data32=4294967295
1328 ret_data64=18446744073709551615
1333 pio=system.iobus.master[3]
1335 [system.tsunami.fake_uart2]
1337 clk_domain=system.clk_domain
1340 pio_addr=8804615848936
1345 ret_data32=4294967295
1346 ret_data64=18446744073709551615
1351 pio=system.iobus.master[4]
1353 [system.tsunami.fake_uart3]
1355 clk_domain=system.clk_domain
1358 pio_addr=8804615848680
1363 ret_data32=4294967295
1364 ret_data64=18446744073709551615
1369 pio=system.iobus.master[5]
1371 [system.tsunami.fake_uart4]
1373 clk_domain=system.clk_domain
1376 pio_addr=8804615848944
1381 ret_data32=4294967295
1382 ret_data64=18446744073709551615
1387 pio=system.iobus.master[6]
1391 clk_domain=system.clk_domain
1392 devicename=FrameBuffer
1394 pio_addr=8804615848912
1397 pio=system.iobus.master[21]
1399 [system.tsunami.ide]
1438 MSICAPMsgUpperAddr=0
1439 MSICAPNextCapability=0
1443 MSIXCAPNextCapability=0
1453 PMCAPNextCapability=0
1458 PXCAPDevCapabilities=0
1465 PXCAPNextCapability=0
1473 clk_domain=system.clk_domain
1474 config_latency=20000
1476 disks=system.disk0 system.disk2
1483 platform=system.tsunami
1485 config=system.iobus.master[26]
1486 dma=system.iobus.slave[1]
1487 pio=system.iobus.master[25]
1491 clk_domain=system.clk_domain
1494 pio_addr=8804615847936
1497 time=Thu Jan 1 00:00:00 2009
1498 tsunami=system.tsunami
1500 pio=system.iobus.master[22]
1502 [system.tsunami.pchip]
1504 clk_domain=system.clk_domain
1506 pio_addr=8802535473152
1509 tsunami=system.tsunami
1510 pio=system.iobus.master[1]
1512 [system.tsunami.pciconfig]
1515 clk_domain=system.clk_domain
1519 platform=system.tsunami
1522 pio=system.iobus.default
1524 [system.tsunami.uart]
1526 clk_domain=system.clk_domain
1528 pio_addr=8804615848952
1530 platform=system.tsunami
1532 terminal=system.terminal
1533 pio=system.iobus.master[23]
1535 [system.voltage_domain]