2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.893221 # Number of seconds simulated
4 sim_ticks 1893220881500 # Number of ticks simulated
5 final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 25399 # Simulator instruction rate (inst/s)
8 host_op_rate 25399 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 856404595 # Simulator tick rate (ticks/s)
10 host_mem_usage 393548 # Number of bytes of host memory used
11 host_seconds 2210.66 # Real time elapsed on the host
12 sim_insts 56147815 # Number of instructions simulated
13 sim_ops 56147815 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory
19 system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.readReqs 404812 # Number of read requests accepted
45 system.physmem.writeReqs 118228 # Number of write requests accepted
46 system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue
47 system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue
48 system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM
49 system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
50 system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM
51 system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side
52 system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side
53 system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
54 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
55 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56 system.physmem.perBankRdBursts::0 25483 # Per bank write bursts
57 system.physmem.perBankRdBursts::1 25705 # Per bank write bursts
58 system.physmem.perBankRdBursts::2 25813 # Per bank write bursts
59 system.physmem.perBankRdBursts::3 25775 # Per bank write bursts
60 system.physmem.perBankRdBursts::4 25223 # Per bank write bursts
61 system.physmem.perBankRdBursts::5 24955 # Per bank write bursts
62 system.physmem.perBankRdBursts::6 24789 # Per bank write bursts
63 system.physmem.perBankRdBursts::7 24583 # Per bank write bursts
64 system.physmem.perBankRdBursts::8 25108 # Per bank write bursts
65 system.physmem.perBankRdBursts::9 25258 # Per bank write bursts
66 system.physmem.perBankRdBursts::10 25518 # Per bank write bursts
67 system.physmem.perBankRdBursts::11 24875 # Per bank write bursts
68 system.physmem.perBankRdBursts::12 24528 # Per bank write bursts
69 system.physmem.perBankRdBursts::13 25564 # Per bank write bursts
70 system.physmem.perBankRdBursts::14 25798 # Per bank write bursts
71 system.physmem.perBankRdBursts::15 25721 # Per bank write bursts
72 system.physmem.perBankWrBursts::0 7829 # Per bank write bursts
73 system.physmem.perBankWrBursts::1 7671 # Per bank write bursts
74 system.physmem.perBankWrBursts::2 8071 # Per bank write bursts
75 system.physmem.perBankWrBursts::3 7745 # Per bank write bursts
76 system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
77 system.physmem.perBankWrBursts::5 6944 # Per bank write bursts
78 system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
79 system.physmem.perBankWrBursts::7 6427 # Per bank write bursts
80 system.physmem.perBankWrBursts::8 7237 # Per bank write bursts
81 system.physmem.perBankWrBursts::9 6873 # Per bank write bursts
82 system.physmem.perBankWrBursts::10 7386 # Per bank write bursts
83 system.physmem.perBankWrBursts::11 6888 # Per bank write bursts
84 system.physmem.perBankWrBursts::12 7081 # Per bank write bursts
85 system.physmem.perBankWrBursts::13 8010 # Per bank write bursts
86 system.physmem.perBankWrBursts::14 7995 # Per bank write bursts
87 system.physmem.perBankWrBursts::15 7945 # Per bank write bursts
88 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89 system.physmem.numWrRetry 68 # Number of times write queue was full causing retry
90 system.physmem.totGap 1893211891000 # Total gap between requests
91 system.physmem.readPktSize::0 0 # Read request sizes (log2)
92 system.physmem.readPktSize::1 0 # Read request sizes (log2)
93 system.physmem.readPktSize::2 0 # Read request sizes (log2)
94 system.physmem.readPktSize::3 0 # Read request sizes (log2)
95 system.physmem.readPktSize::4 0 # Read request sizes (log2)
96 system.physmem.readPktSize::5 0 # Read request sizes (log2)
97 system.physmem.readPktSize::6 404812 # Read request sizes (log2)
98 system.physmem.writePktSize::0 0 # Write request sizes (log2)
99 system.physmem.writePktSize::1 0 # Write request sizes (log2)
100 system.physmem.writePktSize::2 0 # Write request sizes (log2)
101 system.physmem.writePktSize::3 0 # Write request sizes (log2)
102 system.physmem.writePktSize::4 0 # Write request sizes (log2)
103 system.physmem.writePktSize::5 0 # Write request sizes (log2)
104 system.physmem.writePktSize::6 118228 # Write request sizes (log2)
105 system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see
201 system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation
215 system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes
223 system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads
256 system.physmem.totQLat 5895300250 # Total ticks spent queuing
257 system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM
258 system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers
259 system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst
260 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
261 system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst
262 system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s
263 system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s
264 system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s
265 system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s
266 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
267 system.physmem.busUtil 0.14 # Data bus utilization in percentage
268 system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
269 system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
270 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
271 system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing
272 system.physmem.readRowHits 363810 # Number of row buffer hits during reads
273 system.physmem.writeRowHits 95775 # Number of row buffer hits during writes
274 system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads
275 system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes
276 system.physmem.avgGap 3619631.18 # Average gap between requests
277 system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined
278 system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ)
279 system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ)
280 system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ)
281 system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ)
282 system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ)
283 system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ)
284 system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ)
285 system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ)
286 system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ)
287 system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ)
288 system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ)
289 system.physmem_0.averagePower 249.054730 # Core power per rank (mW)
290 system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank
291 system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states
292 system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states
293 system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states
294 system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states
295 system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states
296 system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states
297 system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ)
298 system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ)
299 system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ)
300 system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ)
301 system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ)
302 system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ)
303 system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ)
304 system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ)
305 system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ)
306 system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ)
307 system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ)
308 system.physmem_1.averagePower 249.269176 # Core power per rank (mW)
309 system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank
310 system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states
311 system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states
312 system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states
313 system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states
314 system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states
315 system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states
316 system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
317 system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
318 system.cpu.branchPred.lookups 15264339 # Number of BP lookups
319 system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted
320 system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect
321 system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups
322 system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits
323 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
324 system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage
325 system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target.
326 system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions.
327 system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups.
328 system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits.
329 system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses.
330 system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches.
331 system.cpu_clk_domain.clock 500 # Clock period in ticks
332 system.cpu.dtb.fetch_hits 0 # ITB hits
333 system.cpu.dtb.fetch_misses 0 # ITB misses
334 system.cpu.dtb.fetch_acv 0 # ITB acv
335 system.cpu.dtb.fetch_accesses 0 # ITB accesses
336 system.cpu.dtb.read_hits 9321681 # DTB read hits
337 system.cpu.dtb.read_misses 17691 # DTB read misses
338 system.cpu.dtb.read_acv 211 # DTB read access violations
339 system.cpu.dtb.read_accesses 764795 # DTB read accesses
340 system.cpu.dtb.write_hits 6394158 # DTB write hits
341 system.cpu.dtb.write_misses 2442 # DTB write misses
342 system.cpu.dtb.write_acv 159 # DTB write access violations
343 system.cpu.dtb.write_accesses 298776 # DTB write accesses
344 system.cpu.dtb.data_hits 15715839 # DTB hits
345 system.cpu.dtb.data_misses 20133 # DTB misses
346 system.cpu.dtb.data_acv 370 # DTB access violations
347 system.cpu.dtb.data_accesses 1063571 # DTB accesses
348 system.cpu.itb.fetch_hits 4020046 # ITB hits
349 system.cpu.itb.fetch_misses 6280 # ITB misses
350 system.cpu.itb.fetch_acv 699 # ITB acv
351 system.cpu.itb.fetch_accesses 4026326 # ITB accesses
352 system.cpu.itb.read_hits 0 # DTB read hits
353 system.cpu.itb.read_misses 0 # DTB read misses
354 system.cpu.itb.read_acv 0 # DTB read access violations
355 system.cpu.itb.read_accesses 0 # DTB read accesses
356 system.cpu.itb.write_hits 0 # DTB write hits
357 system.cpu.itb.write_misses 0 # DTB write misses
358 system.cpu.itb.write_acv 0 # DTB write access violations
359 system.cpu.itb.write_accesses 0 # DTB write accesses
360 system.cpu.itb.data_hits 0 # DTB hits
361 system.cpu.itb.data_misses 0 # DTB misses
362 system.cpu.itb.data_acv 0 # DTB access violations
363 system.cpu.itb.data_accesses 0 # DTB accesses
364 system.cpu.numPwrStateTransitions 12752 # Number of power state transitions
365 system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state
366 system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state
367 system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state
368 system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state
369 system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state
370 system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
371 system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state
372 system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states
373 system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states
374 system.cpu.numCycles 193121889 # number of cpu cycles simulated
375 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
376 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
377 system.cpu.committedInsts 56147815 # Number of instructions committed
378 system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed
379 system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit
380 system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching
381 system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
382 system.cpu.cpi 3.439526 # CPI: cycles per instruction
383 system.cpu.ipc 0.290738 # IPC: instructions per cycle
384 system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction
385 system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction
386 system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction
387 system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
388 system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction
389 system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
390 system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
391 system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
392 system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
393 system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
394 system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction
395 system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
396 system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
397 system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
398 system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
399 system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
400 system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
401 system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
402 system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
403 system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
404 system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
405 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
406 system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
407 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
408 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
409 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
410 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
411 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
412 system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
413 system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
414 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
415 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
416 system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction
417 system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction
418 system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction
419 system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction
420 system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction
421 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
422 system.cpu.op_class_0::total 56147815 # Class of committed instruction
423 system.cpu.kern.inst.arm 0 # number of arm instructions executed
424 system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
425 system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed
426 system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl
427 system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl
428 system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl
429 system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl
430 system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl
431 system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl
432 system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
433 system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl
434 system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl
435 system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl
436 system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl
437 system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl
438 system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl
439 system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl
440 system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl
441 system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl
442 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
443 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
444 system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl
445 system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl
446 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
447 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
448 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
449 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
450 system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed
451 system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
452 system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
453 system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed
454 system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed
455 system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
456 system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
457 system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
458 system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
459 system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed
460 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
461 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
462 system.cpu.kern.callpal::total 192465 # number of callpals executed
463 system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches
464 system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
465 system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
466 system.cpu.kern.mode_good::kernel 1905
467 system.cpu.kern.mode_good::user 1737
468 system.cpu.kern.mode_good::idle 168
469 system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches
470 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
471 system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches
472 system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches
473 system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode
474 system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode
475 system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode
476 system.cpu.kern.swap_context 4174 # number of times the context was actually changed
477 system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked
478 system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped
479 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
480 system.cpu.dcache.tags.replacements 1394246 # number of replacements
481 system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use
482 system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks.
483 system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks.
484 system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks.
485 system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit.
486 system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor
487 system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy
488 system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy
489 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
490 system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id
491 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
492 system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
493 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
494 system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses
495 system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses
496 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
497 system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits
498 system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits
499 system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits
500 system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits
501 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits
502 system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits
503 system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits
504 system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits
505 system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits
506 system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits
507 system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits
508 system.cpu.dcache.overall_hits::total 13563977 # number of overall hits
509 system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses
510 system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses
511 system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses
512 system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses
513 system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses
514 system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses
515 system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses
516 system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses
517 system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses
518 system.cpu.dcache.overall_misses::total 1670044 # number of overall misses
519 system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles
520 system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles
521 system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles
522 system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles
523 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles
524 system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles
525 system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles
526 system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles
527 system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles
528 system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles
529 system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses)
530 system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses)
531 system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses)
532 system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses)
533 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses)
534 system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses)
535 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses)
536 system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses)
537 system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses
538 system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses
539 system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses
540 system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses
541 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses
542 system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses
543 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses
544 system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses
545 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses
546 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses
547 system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses
548 system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses
549 system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses
550 system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses
551 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency
552 system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency
553 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency
554 system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency
555 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency
556 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency
557 system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency
558 system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency
559 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency
560 system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency
561 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
562 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
563 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
564 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
565 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
566 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
567 system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks
568 system.cpu.dcache.writebacks::total 837664 # number of writebacks
569 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits
570 system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits
571 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits
572 system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits
573 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
574 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
575 system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits
576 system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits
577 system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits
578 system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits
579 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses
580 system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses
581 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses
582 system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses
583 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses
584 system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses
585 system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses
586 system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses
587 system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses
588 system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses
589 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
590 system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
591 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
592 system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
593 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
594 system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
595 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles
596 system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles
597 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles
598 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles
599 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles
600 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles
601 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles
602 system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles
603 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles
604 system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles
605 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles
606 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles
607 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles
608 system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles
609 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses
610 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses
611 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses
612 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses
613 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses
614 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses
615 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses
616 system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses
617 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses
618 system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses
619 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency
620 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency
621 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency
622 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency
623 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency
624 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency
625 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency
626 system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency
627 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency
628 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency
629 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency
630 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency
631 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency
632 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency
633 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
634 system.cpu.icache.tags.replacements 1477105 # number of replacements
635 system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use
636 system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks.
637 system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks.
638 system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks.
639 system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit.
640 system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor
641 system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy
642 system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy
643 system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
644 system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
645 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
646 system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id
647 system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
648 system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses
649 system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses
650 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
651 system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits
652 system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits
653 system.cpu.icache.demand_hits::cpu.inst 19233043 # number of demand (read+write) hits
654 system.cpu.icache.demand_hits::total 19233043 # number of demand (read+write) hits
655 system.cpu.icache.overall_hits::cpu.inst 19233043 # number of overall hits
656 system.cpu.icache.overall_hits::total 19233043 # number of overall hits
657 system.cpu.icache.ReadReq_misses::cpu.inst 1477790 # number of ReadReq misses
658 system.cpu.icache.ReadReq_misses::total 1477790 # number of ReadReq misses
659 system.cpu.icache.demand_misses::cpu.inst 1477790 # number of demand (read+write) misses
660 system.cpu.icache.demand_misses::total 1477790 # number of demand (read+write) misses
661 system.cpu.icache.overall_misses::cpu.inst 1477790 # number of overall misses
662 system.cpu.icache.overall_misses::total 1477790 # number of overall misses
663 system.cpu.icache.ReadReq_miss_latency::cpu.inst 20696583500 # number of ReadReq miss cycles
664 system.cpu.icache.ReadReq_miss_latency::total 20696583500 # number of ReadReq miss cycles
665 system.cpu.icache.demand_miss_latency::cpu.inst 20696583500 # number of demand (read+write) miss cycles
666 system.cpu.icache.demand_miss_latency::total 20696583500 # number of demand (read+write) miss cycles
667 system.cpu.icache.overall_miss_latency::cpu.inst 20696583500 # number of overall miss cycles
668 system.cpu.icache.overall_miss_latency::total 20696583500 # number of overall miss cycles
669 system.cpu.icache.ReadReq_accesses::cpu.inst 20710833 # number of ReadReq accesses(hits+misses)
670 system.cpu.icache.ReadReq_accesses::total 20710833 # number of ReadReq accesses(hits+misses)
671 system.cpu.icache.demand_accesses::cpu.inst 20710833 # number of demand (read+write) accesses
672 system.cpu.icache.demand_accesses::total 20710833 # number of demand (read+write) accesses
673 system.cpu.icache.overall_accesses::cpu.inst 20710833 # number of overall (read+write) accesses
674 system.cpu.icache.overall_accesses::total 20710833 # number of overall (read+write) accesses
675 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071353 # miss rate for ReadReq accesses
676 system.cpu.icache.ReadReq_miss_rate::total 0.071353 # miss rate for ReadReq accesses
677 system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses
678 system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses
679 system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses
680 system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses
681 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency
682 system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency
683 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency
684 system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency
685 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency
686 system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency
687 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
688 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
689 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
690 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
691 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
692 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
693 system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks
694 system.cpu.icache.writebacks::total 1477105 # number of writebacks
695 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses
696 system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses
697 system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses
698 system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses
699 system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses
700 system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses
701 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles
702 system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles
703 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles
704 system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles
705 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles
706 system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles
707 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses
708 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses
709 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses
710 system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses
711 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses
712 system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses
713 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency
714 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency
715 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency
716 system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency
717 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency
718 system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency
719 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
720 system.cpu.l2cache.tags.replacements 339628 # number of replacements
721 system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use
722 system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks.
723 system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks.
724 system.cpu.l2cache.tags.avg_refs 13.171233 # Average number of references to valid blocks.
725 system.cpu.l2cache.tags.warmup_cycle 6812996000 # Cycle when the warmup percentage was hit.
726 system.cpu.l2cache.tags.occ_blocks::writebacks 268.308875 # Average occupied blocks per requestor
727 system.cpu.l2cache.tags.occ_blocks::cpu.inst 5785.000603 # Average occupied blocks per requestor
728 system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886 # Average occupied blocks per requestor
729 system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy
730 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088272 # Average percentage of cache occupancy
731 system.cpu.l2cache.tags.occ_percent::cpu.data 0.905690 # Average percentage of cache occupancy
732 system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy
733 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
734 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
735 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id
736 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id
737 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id
738 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id
739 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
740 system.cpu.l2cache.tags.tag_accesses 46341016 # Number of tag accesses
741 system.cpu.l2cache.tags.data_accesses 46341016 # Number of data accesses
742 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
743 system.cpu.l2cache.WritebackDirty_hits::writebacks 837664 # number of WritebackDirty hits
744 system.cpu.l2cache.WritebackDirty_hits::total 837664 # number of WritebackDirty hits
745 system.cpu.l2cache.WritebackClean_hits::writebacks 1476525 # number of WritebackClean hits
746 system.cpu.l2cache.WritebackClean_hits::total 1476525 # number of WritebackClean hits
747 system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits
748 system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits
749 system.cpu.l2cache.ReadExReq_hits::cpu.data 187358 # number of ReadExReq hits
750 system.cpu.l2cache.ReadExReq_hits::total 187358 # number of ReadExReq hits
751 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461386 # number of ReadCleanReq hits
752 system.cpu.l2cache.ReadCleanReq_hits::total 1461386 # number of ReadCleanReq hits
753 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818548 # number of ReadSharedReq hits
754 system.cpu.l2cache.ReadSharedReq_hits::total 818548 # number of ReadSharedReq hits
755 system.cpu.l2cache.demand_hits::cpu.inst 1461386 # number of demand (read+write) hits
756 system.cpu.l2cache.demand_hits::cpu.data 1005906 # number of demand (read+write) hits
757 system.cpu.l2cache.demand_hits::total 2467292 # number of demand (read+write) hits
758 system.cpu.l2cache.overall_hits::cpu.inst 1461386 # number of overall hits
759 system.cpu.l2cache.overall_hits::cpu.data 1005906 # number of overall hits
760 system.cpu.l2cache.overall_hits::total 2467292 # number of overall hits
761 system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
762 system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
763 system.cpu.l2cache.ReadExReq_misses::cpu.data 116652 # number of ReadExReq misses
764 system.cpu.l2cache.ReadExReq_misses::total 116652 # number of ReadExReq misses
765 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16348 # number of ReadCleanReq misses
766 system.cpu.l2cache.ReadCleanReq_misses::total 16348 # number of ReadCleanReq misses
767 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272226 # number of ReadSharedReq misses
768 system.cpu.l2cache.ReadSharedReq_misses::total 272226 # number of ReadSharedReq misses
769 system.cpu.l2cache.demand_misses::cpu.inst 16348 # number of demand (read+write) misses
770 system.cpu.l2cache.demand_misses::cpu.data 388878 # number of demand (read+write) misses
771 system.cpu.l2cache.demand_misses::total 405226 # number of demand (read+write) misses
772 system.cpu.l2cache.overall_misses::cpu.inst 16348 # number of overall misses
773 system.cpu.l2cache.overall_misses::cpu.data 388878 # number of overall misses
774 system.cpu.l2cache.overall_misses::total 405226 # number of overall misses
775 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331000 # number of UpgradeReq miss cycles
776 system.cpu.l2cache.UpgradeReq_miss_latency::total 331000 # number of UpgradeReq miss cycles
777 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10499091500 # number of ReadExReq miss cycles
778 system.cpu.l2cache.ReadExReq_miss_latency::total 10499091500 # number of ReadExReq miss cycles
779 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1618484000 # number of ReadCleanReq miss cycles
780 system.cpu.l2cache.ReadCleanReq_miss_latency::total 1618484000 # number of ReadCleanReq miss cycles
781 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21963269500 # number of ReadSharedReq miss cycles
782 system.cpu.l2cache.ReadSharedReq_miss_latency::total 21963269500 # number of ReadSharedReq miss cycles
783 system.cpu.l2cache.demand_miss_latency::cpu.inst 1618484000 # number of demand (read+write) miss cycles
784 system.cpu.l2cache.demand_miss_latency::cpu.data 32462361000 # number of demand (read+write) miss cycles
785 system.cpu.l2cache.demand_miss_latency::total 34080845000 # number of demand (read+write) miss cycles
786 system.cpu.l2cache.overall_miss_latency::cpu.inst 1618484000 # number of overall miss cycles
787 system.cpu.l2cache.overall_miss_latency::cpu.data 32462361000 # number of overall miss cycles
788 system.cpu.l2cache.overall_miss_latency::total 34080845000 # number of overall miss cycles
789 system.cpu.l2cache.WritebackDirty_accesses::writebacks 837664 # number of WritebackDirty accesses(hits+misses)
790 system.cpu.l2cache.WritebackDirty_accesses::total 837664 # number of WritebackDirty accesses(hits+misses)
791 system.cpu.l2cache.WritebackClean_accesses::writebacks 1476525 # number of WritebackClean accesses(hits+misses)
792 system.cpu.l2cache.WritebackClean_accesses::total 1476525 # number of WritebackClean accesses(hits+misses)
793 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses)
794 system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
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796 system.cpu.l2cache.ReadExReq_accesses::total 304010 # number of ReadExReq accesses(hits+misses)
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798 system.cpu.l2cache.ReadCleanReq_accesses::total 1477734 # number of ReadCleanReq accesses(hits+misses)
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800 system.cpu.l2cache.ReadSharedReq_accesses::total 1090774 # number of ReadSharedReq accesses(hits+misses)
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802 system.cpu.l2cache.demand_accesses::cpu.data 1394784 # number of demand (read+write) accesses
803 system.cpu.l2cache.demand_accesses::total 2872518 # number of demand (read+write) accesses
804 system.cpu.l2cache.overall_accesses::cpu.inst 1477734 # number of overall (read+write) accesses
805 system.cpu.l2cache.overall_accesses::cpu.data 1394784 # number of overall (read+write) accesses
806 system.cpu.l2cache.overall_accesses::total 2872518 # number of overall (read+write) accesses
807 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses
808 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses
809 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383711 # miss rate for ReadExReq accesses
810 system.cpu.l2cache.ReadExReq_miss_rate::total 0.383711 # miss rate for ReadExReq accesses
811 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011063 # miss rate for ReadCleanReq accesses
812 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011063 # miss rate for ReadCleanReq accesses
813 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249571 # miss rate for ReadSharedReq accesses
814 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249571 # miss rate for ReadSharedReq accesses
815 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011063 # miss rate for demand accesses
816 system.cpu.l2cache.demand_miss_rate::cpu.data 0.278809 # miss rate for demand accesses
817 system.cpu.l2cache.demand_miss_rate::total 0.141070 # miss rate for demand accesses
818 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011063 # miss rate for overall accesses
819 system.cpu.l2cache.overall_miss_rate::cpu.data 0.278809 # miss rate for overall accesses
820 system.cpu.l2cache.overall_miss_rate::total 0.141070 # miss rate for overall accesses
821 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667 # average UpgradeReq miss latency
822 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667 # average UpgradeReq miss latency
823 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586 # average ReadExReq miss latency
824 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586 # average ReadExReq miss latency
825 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426 # average ReadCleanReq miss latency
826 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426 # average ReadCleanReq miss latency
827 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519 # average ReadSharedReq miss latency
828 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519 # average ReadSharedReq miss latency
829 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency
830 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency
831 system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848 # average overall miss latency
832 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency
833 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency
834 system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848 # average overall miss latency
835 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
838 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
839 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841 system.cpu.l2cache.writebacks::writebacks 76716 # number of writebacks
842 system.cpu.l2cache.writebacks::total 76716 # number of writebacks
843 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
844 system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
845 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116652 # number of ReadExReq MSHR misses
846 system.cpu.l2cache.ReadExReq_mshr_misses::total 116652 # number of ReadExReq MSHR misses
847 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16348 # number of ReadCleanReq MSHR misses
848 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16348 # number of ReadCleanReq MSHR misses
849 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272226 # number of ReadSharedReq MSHR misses
850 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272226 # number of ReadSharedReq MSHR misses
851 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16348 # number of demand (read+write) MSHR misses
852 system.cpu.l2cache.demand_mshr_misses::cpu.data 388878 # number of demand (read+write) MSHR misses
853 system.cpu.l2cache.demand_mshr_misses::total 405226 # number of demand (read+write) MSHR misses
854 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16348 # number of overall MSHR misses
855 system.cpu.l2cache.overall_mshr_misses::cpu.data 388878 # number of overall MSHR misses
856 system.cpu.l2cache.overall_mshr_misses::total 405226 # number of overall MSHR misses
857 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
858 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
859 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
860 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
861 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
862 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
863 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles
864 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles
865 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles
866 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles
867 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles
868 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles
869 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles
870 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles
871 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles
872 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles
873 system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles
874 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles
875 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles
876 system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles
877 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles
878 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles
879 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles
880 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles
881 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses
882 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses
883 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses
884 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses
885 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses
886 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses
887 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses
888 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses
889 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses
890 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses
891 system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses
892 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses
893 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses
894 system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses
895 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency
896 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency
897 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency
898 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency
899 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency
900 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency
901 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency
902 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency
903 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency
904 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency
905 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency
906 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency
907 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency
908 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency
909 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency
910 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency
911 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency
912 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency
913 system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter.
914 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data.
915 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
916 system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter.
917 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
918 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
919 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
920 system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
921 system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution
922 system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution
923 system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution
924 system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution
925 system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution
926 system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution
927 system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
928 system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
929 system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution
930 system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution
931 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution
932 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution
933 system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
934 system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution
935 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes)
936 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes)
937 system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes)
938 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes)
939 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes)
940 system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes)
941 system.cpu.toL2Bus.snoops 340242 # Total snoops (count)
942 system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes)
943 system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram
944 system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram
945 system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram
946 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
947 system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram
948 system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram
949 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
950 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
951 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
952 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
953 system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram
954 system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks)
955 system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
956 system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
957 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
958 system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks)
959 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
960 system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks)
961 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
962 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
963 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
964 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
965 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
966 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
967 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
968 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
969 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
970 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
971 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
972 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
973 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
974 system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
975 system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
976 system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
977 system.iobus.trans_dist::WriteReq 51175 # Transaction distribution
978 system.iobus.trans_dist::WriteResp 51175 # Transaction distribution
979 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes)
980 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
981 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
982 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
983 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
984 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
985 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
986 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
987 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
988 system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes)
989 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
990 system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
991 system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes)
992 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes)
993 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
994 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
995 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
996 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
997 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
998 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
999 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1000 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1001 system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes)
1002 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
1003 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
1004 system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes)
1005 system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks)
1006 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1007 system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks)
1008 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1009 system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks)
1010 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1011 system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
1012 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1013 system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks)
1014 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1015 system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks)
1016 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1017 system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks)
1018 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1019 system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks)
1020 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1021 system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks)
1022 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1023 system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks)
1024 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1025 system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks)
1026 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1027 system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1028 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1029 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1030 system.iocache.tags.replacements 41685 # number of replacements
1031 system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use
1032 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1033 system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1034 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1035 system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit.
1036 system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor
1037 system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy
1038 system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy
1039 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1040 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1041 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1042 system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1043 system.iocache.tags.data_accesses 375525 # Number of data accesses
1044 system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1045 system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1046 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1047 system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1048 system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1049 system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1050 system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1051 system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1052 system.iocache.overall_misses::total 41725 # number of overall misses
1053 system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles
1054 system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles
1055 system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles
1056 system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles
1057 system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles
1058 system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles
1059 system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles
1060 system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles
1061 system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1062 system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1063 system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1064 system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1065 system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
1066 system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
1067 system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
1068 system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1069 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1070 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1071 system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1072 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1073 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1074 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1075 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1076 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1077 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency
1078 system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency
1079 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency
1080 system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency
1081 system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency
1082 system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency
1083 system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency
1084 system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency
1085 system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked
1086 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1087 system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked
1088 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1089 system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked
1090 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1091 system.iocache.writebacks::writebacks 41512 # number of writebacks
1092 system.iocache.writebacks::total 41512 # number of writebacks
1093 system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1094 system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1095 system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1096 system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1097 system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
1098 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
1099 system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
1100 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1101 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles
1102 system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles
1103 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles
1104 system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles
1105 system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles
1106 system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles
1107 system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles
1108 system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles
1109 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1110 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1111 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1112 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1113 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1114 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1115 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1116 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1117 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency
1118 system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency
1119 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency
1120 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency
1121 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency
1122 system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency
1123 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency
1124 system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency
1125 system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter.
1126 system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1127 system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1128 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1129 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1130 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1131 system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1132 system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1133 system.membus.trans_dist::ReadResp 295653 # Transaction distribution
1134 system.membus.trans_dist::WriteReq 9623 # Transaction distribution
1135 system.membus.trans_dist::WriteResp 9623 # Transaction distribution
1136 system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution
1137 system.membus.trans_dist::CleanEvict 262245 # Transaction distribution
1138 system.membus.trans_dist::UpgradeReq 138 # Transaction distribution
1139 system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
1140 system.membus.trans_dist::ReadExReq 116520 # Transaction distribution
1141 system.membus.trans_dist::ReadExResp 116520 # Transaction distribution
1142 system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution
1143 system.membus.trans_dist::BadAddressError 24 # Transaction distribution
1144 system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1145 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes)
1146 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes)
1147 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
1148 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes)
1149 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1150 system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1151 system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes)
1152 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes)
1153 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes)
1154 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes)
1155 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1156 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1157 system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes)
1158 system.membus.snoops 434 # Total snoops (count)
1159 system.membus.snoopTraffic 27584 # Total snoop traffic (bytes)
1160 system.membus.snoop_fanout::samples 463510 # Request fanout histogram
1161 system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram
1162 system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram
1163 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1164 system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram
1165 system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram
1166 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1167 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1168 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1169 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1170 system.membus.snoop_fanout::total 463510 # Request fanout histogram
1171 system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks)
1172 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1173 system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks)
1174 system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1175 system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks)
1176 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1177 system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks)
1178 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1179 system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
1180 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1181 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1182 system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1183 system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1184 system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1185 system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1186 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1187 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1188 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1189 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1190 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1191 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1192 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1193 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1194 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1195 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1196 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1197 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1198 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1199 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1200 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1201 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1202 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1203 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1204 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1205 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1206 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1207 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1208 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1209 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1210 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1211 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1212 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1213 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1214 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1215 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1216 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1217 system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1218 system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1219 system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1220 system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1221 system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1222 system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1223 system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1224 system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1225 system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1226 system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1227 system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1228 system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1229 system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1230 system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1231 system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1232 system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1233 system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1234 system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1235 system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1236 system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1237 system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1238 system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1239 system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states
1241 ---------- End Simulation Statistics ----------
projects / gem5.git / blob