tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxAlphaSystem
  11 children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
  12 boot_cpu_frequency=500
  13 boot_osflags=root=/dev/hda1 console=ttyS0
  14 clock=1000
  15 console=/gem5/dist/binaries/console
  16 init_param=0
  17 kernel=/gem5/dist/binaries/vmlinux
  18 load_addr_mask=1099511627775
  19 mem_mode=timing
  20 mem_ranges=0:134217727
  21 memories=system.physmem
  22 num_work_ids=16
  23 pal=/gem5/dist/binaries/ts_osfpal
  24 readfile=tests/halt.sh
  25 symbolfile=
  26 system_rev=1024
  27 system_type=34
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.bridge]
  38 type=Bridge
  39 clock=1000
  40 delay=50000
  41 ranges=8796093022208:18446744073709551615
  42 req_size=16
  43 resp_size=16
  44 master=system.iobus.slave[0]
  45 slave=system.membus.master[0]
  46
  47 [system.cpu]
  48 type=DerivO3CPU
  49 children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  50 BTBEntries=4096
  51 BTBTagSize=16
  52 LFSTSize=1024
  53 LQEntries=32
  54 LSQCheckLoads=true
  55 LSQDepCheckShift=4
  56 RASSize=16
  57 SQEntries=32
  58 SSITSize=1024
  59 activity=0
  60 backComSize=5
  61 cachePorts=200
  62 checker=Null
  63 choiceCtrBits=2
  64 choicePredictorSize=8192
  65 clock=500
  66 commitToDecodeDelay=1
  67 commitToFetchDelay=1
  68 commitToIEWDelay=1
  69 commitToRenameDelay=1
  70 commitWidth=8
  71 cpu_id=0
  72 decodeToFetchDelay=1
  73 decodeToRenameDelay=1
  74 decodeWidth=8
  75 dispatchWidth=8
  76 do_checkpoint_insts=true
  77 do_quiesce=true
  78 do_statistics_insts=true
  79 dtb=system.cpu.dtb
  80 fetchToDecodeDelay=1
  81 fetchTrapLatency=1
  82 fetchWidth=8
  83 forwardComSize=5
  84 fuPool=system.cpu.fuPool
  85 function_trace=false
  86 function_trace_start=0
  87 globalCtrBits=2
  88 globalHistoryBits=13
  89 globalPredictorSize=8192
  90 iewToCommitDelay=1
  91 iewToDecodeDelay=1
  92 iewToFetchDelay=1
  93 iewToRenameDelay=1
  94 instShiftAmt=2
  95 interrupts=system.cpu.interrupts
  96 isa=system.cpu.isa
  97 issueToExecuteDelay=1
  98 issueWidth=8
  99 itb=system.cpu.itb
 100 localCtrBits=2
 101 localHistoryBits=11
 102 localHistoryTableSize=2048
 103 localPredictorSize=2048
 104 max_insts_all_threads=0
 105 max_insts_any_thread=0
 106 max_loads_all_threads=0
 107 max_loads_any_thread=0
 108 needsTSO=false
 109 numIQEntries=64
 110 numPhysFloatRegs=256
 111 numPhysIntRegs=256
 112 numROBEntries=192
 113 numRobs=1
 114 numThreads=1
 115 predType=tournament
 116 profile=0
 117 progress_interval=0
 118 renameToDecodeDelay=1
 119 renameToFetchDelay=1
 120 renameToIEWDelay=2
 121 renameToROBDelay=1
 122 renameWidth=8
 123 smtCommitPolicy=RoundRobin
 124 smtFetchPolicy=SingleThread
 125 smtIQPolicy=Partitioned
 126 smtIQThreshold=100
 127 smtLSQPolicy=Partitioned
 128 smtLSQThreshold=100
 129 smtNumFetchingThreads=1
 130 smtROBPolicy=Partitioned
 131 smtROBThreshold=100
 132 squashWidth=8
 133 store_set_clear_period=250000
 134 switched_out=false
 135 system=system
 136 tracer=system.cpu.tracer
 137 trapLatency=13
 138 wbDepth=1
 139 wbWidth=8
 140 workload=
 141 dcache_port=system.cpu.dcache.cpu_side
 142 icache_port=system.cpu.icache.cpu_side
 143
 144 [system.cpu.dcache]
 145 type=BaseCache
 146 addr_ranges=0:18446744073709551615
 147 assoc=4
 148 block_size=64
 149 clock=500
 150 forward_snoops=true
 151 hit_latency=2
 152 is_top_level=true
 153 max_miss_count=0
 154 mshrs=4
 155 prefetch_on_access=false
 156 prefetcher=Null
 157 response_latency=2
 158 size=32768
 159 system=system
 160 tgts_per_mshr=20
 161 two_queue=false
 162 write_buffers=8
 163 cpu_side=system.cpu.dcache_port
 164 mem_side=system.cpu.toL2Bus.slave[1]
 165
 166 [system.cpu.dtb]
 167 type=AlphaTLB
 168 size=64
 169
 170 [system.cpu.fuPool]
 171 type=FUPool
 172 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 173 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 174
 175 [system.cpu.fuPool.FUList0]
 176 type=FUDesc
 177 children=opList
 178 count=6
 179 opList=system.cpu.fuPool.FUList0.opList
 180
 181 [system.cpu.fuPool.FUList0.opList]
 182 type=OpDesc
 183 issueLat=1
 184 opClass=IntAlu
 185 opLat=1
 186
 187 [system.cpu.fuPool.FUList1]
 188 type=FUDesc
 189 children=opList0 opList1
 190 count=2
 191 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 192
 193 [system.cpu.fuPool.FUList1.opList0]
 194 type=OpDesc
 195 issueLat=1
 196 opClass=IntMult
 197 opLat=3
 198
 199 [system.cpu.fuPool.FUList1.opList1]
 200 type=OpDesc
 201 issueLat=19
 202 opClass=IntDiv
 203 opLat=20
 204
 205 [system.cpu.fuPool.FUList2]
 206 type=FUDesc
 207 children=opList0 opList1 opList2
 208 count=4
 209 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 210
 211 [system.cpu.fuPool.FUList2.opList0]
 212 type=OpDesc
 213 issueLat=1
 214 opClass=FloatAdd
 215 opLat=2
 216
 217 [system.cpu.fuPool.FUList2.opList1]
 218 type=OpDesc
 219 issueLat=1
 220 opClass=FloatCmp
 221 opLat=2
 222
 223 [system.cpu.fuPool.FUList2.opList2]
 224 type=OpDesc
 225 issueLat=1
 226 opClass=FloatCvt
 227 opLat=2
 228
 229 [system.cpu.fuPool.FUList3]
 230 type=FUDesc
 231 children=opList0 opList1 opList2
 232 count=2
 233 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 234
 235 [system.cpu.fuPool.FUList3.opList0]
 236 type=OpDesc
 237 issueLat=1
 238 opClass=FloatMult
 239 opLat=4
 240
 241 [system.cpu.fuPool.FUList3.opList1]
 242 type=OpDesc
 243 issueLat=12
 244 opClass=FloatDiv
 245 opLat=12
 246
 247 [system.cpu.fuPool.FUList3.opList2]
 248 type=OpDesc
 249 issueLat=24
 250 opClass=FloatSqrt
 251 opLat=24
 252
 253 [system.cpu.fuPool.FUList4]
 254 type=FUDesc
 255 children=opList
 256 count=0
 257 opList=system.cpu.fuPool.FUList4.opList
 258
 259 [system.cpu.fuPool.FUList4.opList]
 260 type=OpDesc
 261 issueLat=1
 262 opClass=MemRead
 263 opLat=1
 264
 265 [system.cpu.fuPool.FUList5]
 266 type=FUDesc
 267 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 268 count=4
 269 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 270
 271 [system.cpu.fuPool.FUList5.opList00]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=SimdAdd
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5.opList01]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=SimdAddAcc
 281 opLat=1
 282
 283 [system.cpu.fuPool.FUList5.opList02]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdAlu
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList03]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdCmp
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList04]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdCvt
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList05]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdMisc
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList06]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdMult
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList07]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdMultAcc
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList08]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdShift
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList09]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdShiftAcc
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList10]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdSqrt
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList11]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdFloatAdd
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList12]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdFloatAlu
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList13]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatCmp
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList14]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatCvt
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList15]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatDiv
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList16]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdFloatMisc
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList17]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=SimdFloatMult
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList18]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=SimdFloatMultAcc
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList5.opList19]
 386 type=OpDesc
 387 issueLat=1
 388 opClass=SimdFloatSqrt
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList6]
 392 type=FUDesc
 393 children=opList
 394 count=0
 395 opList=system.cpu.fuPool.FUList6.opList
 396
 397 [system.cpu.fuPool.FUList6.opList]
 398 type=OpDesc
 399 issueLat=1
 400 opClass=MemWrite
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList7]
 404 type=FUDesc
 405 children=opList0 opList1
 406 count=4
 407 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 408
 409 [system.cpu.fuPool.FUList7.opList0]
 410 type=OpDesc
 411 issueLat=1
 412 opClass=MemRead
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList7.opList1]
 416 type=OpDesc
 417 issueLat=1
 418 opClass=MemWrite
 419 opLat=1
 420
 421 [system.cpu.fuPool.FUList8]
 422 type=FUDesc
 423 children=opList
 424 count=1
 425 opList=system.cpu.fuPool.FUList8.opList
 426
 427 [system.cpu.fuPool.FUList8.opList]
 428 type=OpDesc
 429 issueLat=3
 430 opClass=IprAccess
 431 opLat=3
 432
 433 [system.cpu.icache]
 434 type=BaseCache
 435 addr_ranges=0:18446744073709551615
 436 assoc=1
 437 block_size=64
 438 clock=500
 439 forward_snoops=true
 440 hit_latency=2
 441 is_top_level=true
 442 max_miss_count=0
 443 mshrs=4
 444 prefetch_on_access=false
 445 prefetcher=Null
 446 response_latency=2
 447 size=32768
 448 system=system
 449 tgts_per_mshr=20
 450 two_queue=false
 451 write_buffers=8
 452 cpu_side=system.cpu.icache_port
 453 mem_side=system.cpu.toL2Bus.slave[0]
 454
 455 [system.cpu.interrupts]
 456 type=AlphaInterrupts
 457
 458 [system.cpu.isa]
 459 type=AlphaISA
 460
 461 [system.cpu.itb]
 462 type=AlphaTLB
 463 size=48
 464
 465 [system.cpu.l2cache]
 466 type=BaseCache
 467 addr_ranges=0:18446744073709551615
 468 assoc=8
 469 block_size=64
 470 clock=500
 471 forward_snoops=true
 472 hit_latency=20
 473 is_top_level=false
 474 max_miss_count=0
 475 mshrs=20
 476 prefetch_on_access=false
 477 prefetcher=Null
 478 response_latency=20
 479 size=4194304
 480 system=system
 481 tgts_per_mshr=12
 482 two_queue=false
 483 write_buffers=8
 484 cpu_side=system.cpu.toL2Bus.master[0]
 485 mem_side=system.membus.slave[1]
 486
 487 [system.cpu.toL2Bus]
 488 type=CoherentBus
 489 block_size=64
 490 clock=500
 491 header_cycles=1
 492 use_default_range=false
 493 width=32
 494 master=system.cpu.l2cache.cpu_side
 495 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 496
 497 [system.cpu.tracer]
 498 type=ExeTracer
 499
 500 [system.disk0]
 501 type=IdeDisk
 502 children=image
 503 delay=1000000
 504 driveID=master
 505 image=system.disk0.image
 506
 507 [system.disk0.image]
 508 type=CowDiskImage
 509 children=child
 510 child=system.disk0.image.child
 511 image_file=
 512 read_only=false
 513 table_size=65536
 514
 515 [system.disk0.image.child]
 516 type=RawDiskImage
 517 image_file=/gem5/dist/disks/linux-latest.img
 518 read_only=true
 519
 520 [system.disk2]
 521 type=IdeDisk
 522 children=image
 523 delay=1000000
 524 driveID=master
 525 image=system.disk2.image
 526
 527 [system.disk2.image]
 528 type=CowDiskImage
 529 children=child
 530 child=system.disk2.image.child
 531 image_file=
 532 read_only=false
 533 table_size=65536
 534
 535 [system.disk2.image.child]
 536 type=RawDiskImage
 537 image_file=/gem5/dist/disks/linux-bigswap2.img
 538 read_only=true
 539
 540 [system.intrctrl]
 541 type=IntrControl
 542 sys=system
 543
 544 [system.iobus]
 545 type=NoncoherentBus
 546 block_size=64
 547 clock=1000
 548 header_cycles=1
 549 use_default_range=true
 550 width=8
 551 default=system.tsunami.pciconfig.pio
 552 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 553 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 554
 555 [system.iocache]
 556 type=BaseCache
 557 addr_ranges=0:134217727
 558 assoc=8
 559 block_size=64
 560 clock=1000
 561 forward_snoops=false
 562 hit_latency=50
 563 is_top_level=true
 564 max_miss_count=0
 565 mshrs=20
 566 prefetch_on_access=false
 567 prefetcher=Null
 568 response_latency=50
 569 size=1024
 570 system=system
 571 tgts_per_mshr=12
 572 two_queue=false
 573 write_buffers=8
 574 cpu_side=system.iobus.master[29]
 575 mem_side=system.membus.slave[2]
 576
 577 [system.membus]
 578 type=CoherentBus
 579 children=badaddr_responder
 580 block_size=64
 581 clock=1000
 582 header_cycles=1
 583 use_default_range=false
 584 width=8
 585 default=system.membus.badaddr_responder.pio
 586 master=system.bridge.slave system.physmem.port
 587 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 588
 589 [system.membus.badaddr_responder]
 590 type=IsaFake
 591 clock=1000
 592 fake_mem=false
 593 pio_addr=0
 594 pio_latency=100000
 595 pio_size=8
 596 ret_bad_addr=true
 597 ret_data16=65535
 598 ret_data32=4294967295
 599 ret_data64=18446744073709551615
 600 ret_data8=255
 601 system=system
 602 update_data=false
 603 warn_access=
 604 pio=system.membus.default
 605
 606 [system.physmem]
 607 type=SimpleDRAM
 608 addr_mapping=openmap
 609 banks_per_rank=8
 610 clock=1000
 611 conf_table_reported=false
 612 in_addr_map=true
 613 lines_per_rowbuffer=64
 614 mem_sched_policy=fcfs
 615 null=false
 616 page_policy=open
 617 range=0:134217727
 618 ranks_per_channel=2
 619 read_buffer_size=32
 620 tBURST=4000
 621 tCL=14000
 622 tRCD=14000
 623 tREFI=7800000
 624 tRFC=300000
 625 tRP=14000
 626 tWTR=1000
 627 write_buffer_size=32
 628 write_thresh_perc=70
 629 zero=false
 630 port=system.membus.master[1]
 631
 632 [system.simple_disk]
 633 type=SimpleDisk
 634 children=disk
 635 disk=system.simple_disk.disk
 636 system=system
 637
 638 [system.simple_disk.disk]
 639 type=RawDiskImage
 640 image_file=/gem5/dist/disks/linux-latest.img
 641 read_only=true
 642
 643 [system.terminal]
 644 type=Terminal
 645 intr_control=system.intrctrl
 646 number=0
 647 output=true
 648 port=3456
 649
 650 [system.tsunami]
 651 type=Tsunami
 652 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 653 intrctrl=system.intrctrl
 654 system=system
 655
 656 [system.tsunami.backdoor]
 657 type=AlphaBackdoor
 658 clock=1000
 659 cpu=system.cpu
 660 disk=system.simple_disk
 661 pio_addr=8804682956800
 662 pio_latency=100000
 663 platform=system.tsunami
 664 system=system
 665 terminal=system.terminal
 666 pio=system.iobus.master[24]
 667
 668 [system.tsunami.cchip]
 669 type=TsunamiCChip
 670 clock=1000
 671 pio_addr=8803072344064
 672 pio_latency=100000
 673 system=system
 674 tsunami=system.tsunami
 675 pio=system.iobus.master[0]
 676
 677 [system.tsunami.ethernet]
 678 type=NSGigE
 679 BAR0=1
 680 BAR0LegacyIO=false
 681 BAR0Size=256
 682 BAR1=0
 683 BAR1LegacyIO=false
 684 BAR1Size=4096
 685 BAR2=0
 686 BAR2LegacyIO=false
 687 BAR2Size=0
 688 BAR3=0
 689 BAR3LegacyIO=false
 690 BAR3Size=0
 691 BAR4=0
 692 BAR4LegacyIO=false
 693 BAR4Size=0
 694 BAR5=0
 695 BAR5LegacyIO=false
 696 BAR5Size=0
 697 BIST=0
 698 CacheLineSize=0
 699 CardbusCIS=0
 700 ClassCode=2
 701 Command=0
 702 DeviceID=34
 703 ExpansionROM=0
 704 HeaderType=0
 705 InterruptLine=30
 706 InterruptPin=1
 707 LatencyTimer=0
 708 MaximumLatency=52
 709 MinimumGrant=176
 710 ProgIF=0
 711 Revision=0
 712 Status=656
 713 SubClassCode=0
 714 SubsystemID=0
 715 SubsystemVendorID=0
 716 VendorID=4107
 717 clock=2000
 718 config_latency=20000
 719 dma_data_free=false
 720 dma_desc_free=false
 721 dma_no_allocate=true
 722 dma_read_delay=0
 723 dma_read_factor=0
 724 dma_write_delay=0
 725 dma_write_factor=0
 726 hardware_address=00:90:00:00:00:01
 727 intr_delay=10000000
 728 pci_bus=0
 729 pci_dev=1
 730 pci_func=0
 731 pio_latency=30000
 732 platform=system.tsunami
 733 rss=false
 734 rx_delay=1000000
 735 rx_fifo_size=524288
 736 rx_filter=true
 737 rx_thread=false
 738 system=system
 739 tx_delay=1000000
 740 tx_fifo_size=524288
 741 tx_thread=false
 742 config=system.iobus.master[28]
 743 dma=system.iobus.slave[2]
 744 pio=system.iobus.master[27]
 745
 746 [system.tsunami.fake_OROM]
 747 type=IsaFake
 748 clock=1000
 749 fake_mem=false
 750 pio_addr=8796093677568
 751 pio_latency=100000
 752 pio_size=393216
 753 ret_bad_addr=false
 754 ret_data16=65535
 755 ret_data32=4294967295
 756 ret_data64=18446744073709551615
 757 ret_data8=255
 758 system=system
 759 update_data=false
 760 warn_access=
 761 pio=system.iobus.master[8]
 762
 763 [system.tsunami.fake_ata0]
 764 type=IsaFake
 765 clock=1000
 766 fake_mem=false
 767 pio_addr=8804615848432
 768 pio_latency=100000
 769 pio_size=8
 770 ret_bad_addr=false
 771 ret_data16=65535
 772 ret_data32=4294967295
 773 ret_data64=18446744073709551615
 774 ret_data8=255
 775 system=system
 776 update_data=false
 777 warn_access=
 778 pio=system.iobus.master[19]
 779
 780 [system.tsunami.fake_ata1]
 781 type=IsaFake
 782 clock=1000
 783 fake_mem=false
 784 pio_addr=8804615848304
 785 pio_latency=100000
 786 pio_size=8
 787 ret_bad_addr=false
 788 ret_data16=65535
 789 ret_data32=4294967295
 790 ret_data64=18446744073709551615
 791 ret_data8=255
 792 system=system
 793 update_data=false
 794 warn_access=
 795 pio=system.iobus.master[20]
 796
 797 [system.tsunami.fake_pnp_addr]
 798 type=IsaFake
 799 clock=1000
 800 fake_mem=false
 801 pio_addr=8804615848569
 802 pio_latency=100000
 803 pio_size=8
 804 ret_bad_addr=false
 805 ret_data16=65535
 806 ret_data32=4294967295
 807 ret_data64=18446744073709551615
 808 ret_data8=255
 809 system=system
 810 update_data=false
 811 warn_access=
 812 pio=system.iobus.master[9]
 813
 814 [system.tsunami.fake_pnp_read0]
 815 type=IsaFake
 816 clock=1000
 817 fake_mem=false
 818 pio_addr=8804615848451
 819 pio_latency=100000
 820 pio_size=8
 821 ret_bad_addr=false
 822 ret_data16=65535
 823 ret_data32=4294967295
 824 ret_data64=18446744073709551615
 825 ret_data8=255
 826 system=system
 827 update_data=false
 828 warn_access=
 829 pio=system.iobus.master[11]
 830
 831 [system.tsunami.fake_pnp_read1]
 832 type=IsaFake
 833 clock=1000
 834 fake_mem=false
 835 pio_addr=8804615848515
 836 pio_latency=100000
 837 pio_size=8
 838 ret_bad_addr=false
 839 ret_data16=65535
 840 ret_data32=4294967295
 841 ret_data64=18446744073709551615
 842 ret_data8=255
 843 system=system
 844 update_data=false
 845 warn_access=
 846 pio=system.iobus.master[12]
 847
 848 [system.tsunami.fake_pnp_read2]
 849 type=IsaFake
 850 clock=1000
 851 fake_mem=false
 852 pio_addr=8804615848579
 853 pio_latency=100000
 854 pio_size=8
 855 ret_bad_addr=false
 856 ret_data16=65535
 857 ret_data32=4294967295
 858 ret_data64=18446744073709551615
 859 ret_data8=255
 860 system=system
 861 update_data=false
 862 warn_access=
 863 pio=system.iobus.master[13]
 864
 865 [system.tsunami.fake_pnp_read3]
 866 type=IsaFake
 867 clock=1000
 868 fake_mem=false
 869 pio_addr=8804615848643
 870 pio_latency=100000
 871 pio_size=8
 872 ret_bad_addr=false
 873 ret_data16=65535
 874 ret_data32=4294967295
 875 ret_data64=18446744073709551615
 876 ret_data8=255
 877 system=system
 878 update_data=false
 879 warn_access=
 880 pio=system.iobus.master[14]
 881
 882 [system.tsunami.fake_pnp_read4]
 883 type=IsaFake
 884 clock=1000
 885 fake_mem=false
 886 pio_addr=8804615848707
 887 pio_latency=100000
 888 pio_size=8
 889 ret_bad_addr=false
 890 ret_data16=65535
 891 ret_data32=4294967295
 892 ret_data64=18446744073709551615
 893 ret_data8=255
 894 system=system
 895 update_data=false
 896 warn_access=
 897 pio=system.iobus.master[15]
 898
 899 [system.tsunami.fake_pnp_read5]
 900 type=IsaFake
 901 clock=1000
 902 fake_mem=false
 903 pio_addr=8804615848771
 904 pio_latency=100000
 905 pio_size=8
 906 ret_bad_addr=false
 907 ret_data16=65535
 908 ret_data32=4294967295
 909 ret_data64=18446744073709551615
 910 ret_data8=255
 911 system=system
 912 update_data=false
 913 warn_access=
 914 pio=system.iobus.master[16]
 915
 916 [system.tsunami.fake_pnp_read6]
 917 type=IsaFake
 918 clock=1000
 919 fake_mem=false
 920 pio_addr=8804615848835
 921 pio_latency=100000
 922 pio_size=8
 923 ret_bad_addr=false
 924 ret_data16=65535
 925 ret_data32=4294967295
 926 ret_data64=18446744073709551615
 927 ret_data8=255
 928 system=system
 929 update_data=false
 930 warn_access=
 931 pio=system.iobus.master[17]
 932
 933 [system.tsunami.fake_pnp_read7]
 934 type=IsaFake
 935 clock=1000
 936 fake_mem=false
 937 pio_addr=8804615848899
 938 pio_latency=100000
 939 pio_size=8
 940 ret_bad_addr=false
 941 ret_data16=65535
 942 ret_data32=4294967295
 943 ret_data64=18446744073709551615
 944 ret_data8=255
 945 system=system
 946 update_data=false
 947 warn_access=
 948 pio=system.iobus.master[18]
 949
 950 [system.tsunami.fake_pnp_write]
 951 type=IsaFake
 952 clock=1000
 953 fake_mem=false
 954 pio_addr=8804615850617
 955 pio_latency=100000
 956 pio_size=8
 957 ret_bad_addr=false
 958 ret_data16=65535
 959 ret_data32=4294967295
 960 ret_data64=18446744073709551615
 961 ret_data8=255
 962 system=system
 963 update_data=false
 964 warn_access=
 965 pio=system.iobus.master[10]
 966
 967 [system.tsunami.fake_ppc]
 968 type=IsaFake
 969 clock=1000
 970 fake_mem=false
 971 pio_addr=8804615848891
 972 pio_latency=100000
 973 pio_size=8
 974 ret_bad_addr=false
 975 ret_data16=65535
 976 ret_data32=4294967295
 977 ret_data64=18446744073709551615
 978 ret_data8=255
 979 system=system
 980 update_data=false
 981 warn_access=
 982 pio=system.iobus.master[7]
 983
 984 [system.tsunami.fake_sm_chip]
 985 type=IsaFake
 986 clock=1000
 987 fake_mem=false
 988 pio_addr=8804615848816
 989 pio_latency=100000
 990 pio_size=8
 991 ret_bad_addr=false
 992 ret_data16=65535
 993 ret_data32=4294967295
 994 ret_data64=18446744073709551615
 995 ret_data8=255
 996 system=system
 997 update_data=false
 998 warn_access=
 999 pio=system.iobus.master[2]
1000
1001 [system.tsunami.fake_uart1]
1002 type=IsaFake
1003 clock=1000
1004 fake_mem=false
1005 pio_addr=8804615848696
1006 pio_latency=100000
1007 pio_size=8
1008 ret_bad_addr=false
1009 ret_data16=65535
1010 ret_data32=4294967295
1011 ret_data64=18446744073709551615
1012 ret_data8=255
1013 system=system
1014 update_data=false
1015 warn_access=
1016 pio=system.iobus.master[3]
1017
1018 [system.tsunami.fake_uart2]
1019 type=IsaFake
1020 clock=1000
1021 fake_mem=false
1022 pio_addr=8804615848936
1023 pio_latency=100000
1024 pio_size=8
1025 ret_bad_addr=false
1026 ret_data16=65535
1027 ret_data32=4294967295
1028 ret_data64=18446744073709551615
1029 ret_data8=255
1030 system=system
1031 update_data=false
1032 warn_access=
1033 pio=system.iobus.master[4]
1034
1035 [system.tsunami.fake_uart3]
1036 type=IsaFake
1037 clock=1000
1038 fake_mem=false
1039 pio_addr=8804615848680
1040 pio_latency=100000
1041 pio_size=8
1042 ret_bad_addr=false
1043 ret_data16=65535
1044 ret_data32=4294967295
1045 ret_data64=18446744073709551615
1046 ret_data8=255
1047 system=system
1048 update_data=false
1049 warn_access=
1050 pio=system.iobus.master[5]
1051
1052 [system.tsunami.fake_uart4]
1053 type=IsaFake
1054 clock=1000
1055 fake_mem=false
1056 pio_addr=8804615848944
1057 pio_latency=100000
1058 pio_size=8
1059 ret_bad_addr=false
1060 ret_data16=65535
1061 ret_data32=4294967295
1062 ret_data64=18446744073709551615
1063 ret_data8=255
1064 system=system
1065 update_data=false
1066 warn_access=
1067 pio=system.iobus.master[6]
1068
1069 [system.tsunami.fb]
1070 type=BadDevice
1071 clock=1000
1072 devicename=FrameBuffer
1073 pio_addr=8804615848912
1074 pio_latency=100000
1075 system=system
1076 pio=system.iobus.master[21]
1077
1078 [system.tsunami.ide]
1079 type=IdeController
1080 BAR0=1
1081 BAR0LegacyIO=false
1082 BAR0Size=8
1083 BAR1=1
1084 BAR1LegacyIO=false
1085 BAR1Size=4
1086 BAR2=1
1087 BAR2LegacyIO=false
1088 BAR2Size=8
1089 BAR3=1
1090 BAR3LegacyIO=false
1091 BAR3Size=4
1092 BAR4=1
1093 BAR4LegacyIO=false
1094 BAR4Size=16
1095 BAR5=1
1096 BAR5LegacyIO=false
1097 BAR5Size=0
1098 BIST=0
1099 CacheLineSize=0
1100 CardbusCIS=0
1101 ClassCode=1
1102 Command=0
1103 DeviceID=28945
1104 ExpansionROM=0
1105 HeaderType=0
1106 InterruptLine=31
1107 InterruptPin=1
1108 LatencyTimer=0
1109 MaximumLatency=0
1110 MinimumGrant=0
1111 ProgIF=133
1112 Revision=0
1113 Status=640
1114 SubClassCode=1
1115 SubsystemID=0
1116 SubsystemVendorID=0
1117 VendorID=32902
1118 clock=1000
1119 config_latency=20000
1120 ctrl_offset=0
1121 disks=system.disk0 system.disk2
1122 io_shift=0
1123 pci_bus=0
1124 pci_dev=0
1125 pci_func=0
1126 pio_latency=30000
1127 platform=system.tsunami
1128 system=system
1129 config=system.iobus.master[26]
1130 dma=system.iobus.slave[1]
1131 pio=system.iobus.master[25]
1132
1133 [system.tsunami.io]
1134 type=TsunamiIO
1135 clock=1000
1136 frequency=976562500
1137 pio_addr=8804615847936
1138 pio_latency=100000
1139 system=system
1140 time=Thu Jan  1 00:00:00 2009
1141 tsunami=system.tsunami
1142 year_is_bcd=false
1143 pio=system.iobus.master[22]
1144
1145 [system.tsunami.pchip]
1146 type=TsunamiPChip
1147 clock=1000
1148 pio_addr=8802535473152
1149 pio_latency=100000
1150 system=system
1151 tsunami=system.tsunami
1152 pio=system.iobus.master[1]
1153
1154 [system.tsunami.pciconfig]
1155 type=PciConfigAll
1156 bus=0
1157 clock=1000
1158 pio_latency=30000
1159 platform=system.tsunami
1160 size=16777216
1161 system=system
1162 pio=system.iobus.default
1163
1164 [system.tsunami.uart]
1165 type=Uart8250
1166 clock=1000
1167 pio_addr=8804615848952
1168 pio_latency=100000
1169 platform=system.tsunami
1170 system=system
1171 terminal=system.terminal
1172 pio=system.iobus.master[23]
1173