stats: update stats for insts/ops and master id changes
[gem5.git] / tests / long / fs / 10.linux-boot / ref / alpha / linux / tsunami-o3 / config.ini
1 [root]
2 type=Root
3 children=system
4 full_system=true
5 time_sync_enable=false
6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
8
9 [system]
10 type=LinuxAlphaSystem
11 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
12 boot_cpu_frequency=500
13 boot_osflags=root=/dev/hda1 console=ttyS0
14 console=/dist/m5/system/binaries/console
15 init_param=0
16 kernel=/dist/m5/system/binaries/vmlinux
17 load_addr_mask=1099511627775
18 mem_mode=timing
19 memories=system.physmem
20 num_work_ids=16
21 pal=/dist/m5/system/binaries/ts_osfpal
22 physmem=system.physmem
23 readfile=tests/halt.sh
24 symbolfile=
25 system_rev=1024
26 system_type=34
27 work_begin_ckpt_count=0
28 work_begin_cpu_id_exit=-1
29 work_begin_exit_count=0
30 work_cpus_ckpt_count=0
31 work_end_ckpt_count=0
32 work_end_exit_count=0
33 work_item_id=-1
34 system_port=system.membus.port[2]
35
36 [system.bridge]
37 type=Bridge
38 delay=50000
39 nack_delay=4000
40 ranges=8796093022208:18446744073709551615
41 req_size=16
42 resp_size=16
43 write_ack=false
44 master=system.iobus.port[0]
45 slave=system.membus.port[0]
46
47 [system.cpu]
48 type=DerivO3CPU
49 children=dcache dtb fuPool icache interrupts itb tracer
50 BTBEntries=4096
51 BTBTagSize=16
52 LFSTSize=1024
53 LQEntries=32
54 LSQCheckLoads=true
55 LSQDepCheckShift=4
56 RASSize=16
57 SQEntries=32
58 SSITSize=1024
59 activity=0
60 backComSize=5
61 cachePorts=200
62 checker=Null
63 choiceCtrBits=2
64 choicePredictorSize=8192
65 clock=500
66 commitToDecodeDelay=1
67 commitToFetchDelay=1
68 commitToIEWDelay=1
69 commitToRenameDelay=1
70 commitWidth=8
71 cpu_id=0
72 decodeToFetchDelay=1
73 decodeToRenameDelay=1
74 decodeWidth=8
75 defer_registration=false
76 dispatchWidth=8
77 do_checkpoint_insts=true
78 do_quiesce=true
79 do_statistics_insts=true
80 dtb=system.cpu.dtb
81 fetchToDecodeDelay=1
82 fetchTrapLatency=1
83 fetchWidth=8
84 forwardComSize=5
85 fuPool=system.cpu.fuPool
86 function_trace=false
87 function_trace_start=0
88 globalCtrBits=2
89 globalHistoryBits=13
90 globalPredictorSize=8192
91 iewToCommitDelay=1
92 iewToDecodeDelay=1
93 iewToFetchDelay=1
94 iewToRenameDelay=1
95 instShiftAmt=2
96 interrupts=system.cpu.interrupts
97 issueToExecuteDelay=1
98 issueWidth=8
99 itb=system.cpu.itb
100 localCtrBits=2
101 localHistoryBits=11
102 localHistoryTableSize=2048
103 localPredictorSize=2048
104 max_insts_all_threads=0
105 max_insts_any_thread=0
106 max_loads_all_threads=0
107 max_loads_any_thread=0
108 needsTSO=false
109 numIQEntries=64
110 numPhysFloatRegs=256
111 numPhysIntRegs=256
112 numROBEntries=192
113 numRobs=1
114 numThreads=1
115 phase=0
116 predType=tournament
117 profile=0
118 progress_interval=0
119 renameToDecodeDelay=1
120 renameToFetchDelay=1
121 renameToIEWDelay=2
122 renameToROBDelay=1
123 renameWidth=8
124 smtCommitPolicy=RoundRobin
125 smtFetchPolicy=SingleThread
126 smtIQPolicy=Partitioned
127 smtIQThreshold=100
128 smtLSQPolicy=Partitioned
129 smtLSQThreshold=100
130 smtNumFetchingThreads=1
131 smtROBPolicy=Partitioned
132 smtROBThreshold=100
133 squashWidth=8
134 store_set_clear_period=250000
135 system=system
136 tracer=system.cpu.tracer
137 trapLatency=13
138 wbDepth=1
139 wbWidth=8
140 workload=
141 dcache_port=system.cpu.dcache.cpu_side
142 icache_port=system.cpu.icache.cpu_side
143
144 [system.cpu.dcache]
145 type=BaseCache
146 addr_range=0:18446744073709551615
147 assoc=4
148 block_size=64
149 forward_snoops=true
150 hash_delay=1
151 is_top_level=true
152 latency=1000
153 max_miss_count=0
154 mshrs=4
155 prefetch_on_access=false
156 prefetcher=Null
157 prioritizeRequests=false
158 repl=Null
159 size=32768
160 subblock_size=0
161 system=system
162 tgts_per_mshr=20
163 trace_addr=0
164 two_queue=false
165 write_buffers=8
166 cpu_side=system.cpu.dcache_port
167 mem_side=system.toL2Bus.port[2]
168
169 [system.cpu.dtb]
170 type=AlphaTLB
171 size=64
172
173 [system.cpu.fuPool]
174 type=FUPool
175 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
176 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
177
178 [system.cpu.fuPool.FUList0]
179 type=FUDesc
180 children=opList
181 count=6
182 opList=system.cpu.fuPool.FUList0.opList
183
184 [system.cpu.fuPool.FUList0.opList]
185 type=OpDesc
186 issueLat=1
187 opClass=IntAlu
188 opLat=1
189
190 [system.cpu.fuPool.FUList1]
191 type=FUDesc
192 children=opList0 opList1
193 count=2
194 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
195
196 [system.cpu.fuPool.FUList1.opList0]
197 type=OpDesc
198 issueLat=1
199 opClass=IntMult
200 opLat=3
201
202 [system.cpu.fuPool.FUList1.opList1]
203 type=OpDesc
204 issueLat=19
205 opClass=IntDiv
206 opLat=20
207
208 [system.cpu.fuPool.FUList2]
209 type=FUDesc
210 children=opList0 opList1 opList2
211 count=4
212 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
213
214 [system.cpu.fuPool.FUList2.opList0]
215 type=OpDesc
216 issueLat=1
217 opClass=FloatAdd
218 opLat=2
219
220 [system.cpu.fuPool.FUList2.opList1]
221 type=OpDesc
222 issueLat=1
223 opClass=FloatCmp
224 opLat=2
225
226 [system.cpu.fuPool.FUList2.opList2]
227 type=OpDesc
228 issueLat=1
229 opClass=FloatCvt
230 opLat=2
231
232 [system.cpu.fuPool.FUList3]
233 type=FUDesc
234 children=opList0 opList1 opList2
235 count=2
236 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
237
238 [system.cpu.fuPool.FUList3.opList0]
239 type=OpDesc
240 issueLat=1
241 opClass=FloatMult
242 opLat=4
243
244 [system.cpu.fuPool.FUList3.opList1]
245 type=OpDesc
246 issueLat=12
247 opClass=FloatDiv
248 opLat=12
249
250 [system.cpu.fuPool.FUList3.opList2]
251 type=OpDesc
252 issueLat=24
253 opClass=FloatSqrt
254 opLat=24
255
256 [system.cpu.fuPool.FUList4]
257 type=FUDesc
258 children=opList
259 count=0
260 opList=system.cpu.fuPool.FUList4.opList
261
262 [system.cpu.fuPool.FUList4.opList]
263 type=OpDesc
264 issueLat=1
265 opClass=MemRead
266 opLat=1
267
268 [system.cpu.fuPool.FUList5]
269 type=FUDesc
270 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
271 count=4
272 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
273
274 [system.cpu.fuPool.FUList5.opList00]
275 type=OpDesc
276 issueLat=1
277 opClass=SimdAdd
278 opLat=1
279
280 [system.cpu.fuPool.FUList5.opList01]
281 type=OpDesc
282 issueLat=1
283 opClass=SimdAddAcc
284 opLat=1
285
286 [system.cpu.fuPool.FUList5.opList02]
287 type=OpDesc
288 issueLat=1
289 opClass=SimdAlu
290 opLat=1
291
292 [system.cpu.fuPool.FUList5.opList03]
293 type=OpDesc
294 issueLat=1
295 opClass=SimdCmp
296 opLat=1
297
298 [system.cpu.fuPool.FUList5.opList04]
299 type=OpDesc
300 issueLat=1
301 opClass=SimdCvt
302 opLat=1
303
304 [system.cpu.fuPool.FUList5.opList05]
305 type=OpDesc
306 issueLat=1
307 opClass=SimdMisc
308 opLat=1
309
310 [system.cpu.fuPool.FUList5.opList06]
311 type=OpDesc
312 issueLat=1
313 opClass=SimdMult
314 opLat=1
315
316 [system.cpu.fuPool.FUList5.opList07]
317 type=OpDesc
318 issueLat=1
319 opClass=SimdMultAcc
320 opLat=1
321
322 [system.cpu.fuPool.FUList5.opList08]
323 type=OpDesc
324 issueLat=1
325 opClass=SimdShift
326 opLat=1
327
328 [system.cpu.fuPool.FUList5.opList09]
329 type=OpDesc
330 issueLat=1
331 opClass=SimdShiftAcc
332 opLat=1
333
334 [system.cpu.fuPool.FUList5.opList10]
335 type=OpDesc
336 issueLat=1
337 opClass=SimdSqrt
338 opLat=1
339
340 [system.cpu.fuPool.FUList5.opList11]
341 type=OpDesc
342 issueLat=1
343 opClass=SimdFloatAdd
344 opLat=1
345
346 [system.cpu.fuPool.FUList5.opList12]
347 type=OpDesc
348 issueLat=1
349 opClass=SimdFloatAlu
350 opLat=1
351
352 [system.cpu.fuPool.FUList5.opList13]
353 type=OpDesc
354 issueLat=1
355 opClass=SimdFloatCmp
356 opLat=1
357
358 [system.cpu.fuPool.FUList5.opList14]
359 type=OpDesc
360 issueLat=1
361 opClass=SimdFloatCvt
362 opLat=1
363
364 [system.cpu.fuPool.FUList5.opList15]
365 type=OpDesc
366 issueLat=1
367 opClass=SimdFloatDiv
368 opLat=1
369
370 [system.cpu.fuPool.FUList5.opList16]
371 type=OpDesc
372 issueLat=1
373 opClass=SimdFloatMisc
374 opLat=1
375
376 [system.cpu.fuPool.FUList5.opList17]
377 type=OpDesc
378 issueLat=1
379 opClass=SimdFloatMult
380 opLat=1
381
382 [system.cpu.fuPool.FUList5.opList18]
383 type=OpDesc
384 issueLat=1
385 opClass=SimdFloatMultAcc
386 opLat=1
387
388 [system.cpu.fuPool.FUList5.opList19]
389 type=OpDesc
390 issueLat=1
391 opClass=SimdFloatSqrt
392 opLat=1
393
394 [system.cpu.fuPool.FUList6]
395 type=FUDesc
396 children=opList
397 count=0
398 opList=system.cpu.fuPool.FUList6.opList
399
400 [system.cpu.fuPool.FUList6.opList]
401 type=OpDesc
402 issueLat=1
403 opClass=MemWrite
404 opLat=1
405
406 [system.cpu.fuPool.FUList7]
407 type=FUDesc
408 children=opList0 opList1
409 count=4
410 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
411
412 [system.cpu.fuPool.FUList7.opList0]
413 type=OpDesc
414 issueLat=1
415 opClass=MemRead
416 opLat=1
417
418 [system.cpu.fuPool.FUList7.opList1]
419 type=OpDesc
420 issueLat=1
421 opClass=MemWrite
422 opLat=1
423
424 [system.cpu.fuPool.FUList8]
425 type=FUDesc
426 children=opList
427 count=1
428 opList=system.cpu.fuPool.FUList8.opList
429
430 [system.cpu.fuPool.FUList8.opList]
431 type=OpDesc
432 issueLat=3
433 opClass=IprAccess
434 opLat=3
435
436 [system.cpu.icache]
437 type=BaseCache
438 addr_range=0:18446744073709551615
439 assoc=1
440 block_size=64
441 forward_snoops=true
442 hash_delay=1
443 is_top_level=true
444 latency=1000
445 max_miss_count=0
446 mshrs=4
447 prefetch_on_access=false
448 prefetcher=Null
449 prioritizeRequests=false
450 repl=Null
451 size=32768
452 subblock_size=0
453 system=system
454 tgts_per_mshr=20
455 trace_addr=0
456 two_queue=false
457 write_buffers=8
458 cpu_side=system.cpu.icache_port
459 mem_side=system.toL2Bus.port[1]
460
461 [system.cpu.interrupts]
462 type=AlphaInterrupts
463
464 [system.cpu.itb]
465 type=AlphaTLB
466 size=48
467
468 [system.cpu.tracer]
469 type=ExeTracer
470
471 [system.disk0]
472 type=IdeDisk
473 children=image
474 delay=1000000
475 driveID=master
476 image=system.disk0.image
477
478 [system.disk0.image]
479 type=CowDiskImage
480 children=child
481 child=system.disk0.image.child
482 image_file=
483 read_only=false
484 table_size=65536
485
486 [system.disk0.image.child]
487 type=RawDiskImage
488 image_file=/dist/m5/system/disks/linux-latest.img
489 read_only=true
490
491 [system.disk2]
492 type=IdeDisk
493 children=image
494 delay=1000000
495 driveID=master
496 image=system.disk2.image
497
498 [system.disk2.image]
499 type=CowDiskImage
500 children=child
501 child=system.disk2.image.child
502 image_file=
503 read_only=false
504 table_size=65536
505
506 [system.disk2.image.child]
507 type=RawDiskImage
508 image_file=/dist/m5/system/disks/linux-bigswap2.img
509 read_only=true
510
511 [system.intrctrl]
512 type=IntrControl
513 sys=system
514
515 [system.iobus]
516 type=Bus
517 block_size=64
518 bus_id=0
519 clock=1000
520 header_cycles=1
521 use_default_range=true
522 width=64
523 default=system.tsunami.pciconfig.pio
524 port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
525
526 [system.iocache]
527 type=BaseCache
528 addr_range=0:8589934591
529 assoc=8
530 block_size=64
531 forward_snoops=false
532 hash_delay=1
533 is_top_level=true
534 latency=50000
535 max_miss_count=0
536 mshrs=20
537 prefetch_on_access=false
538 prefetcher=Null
539 prioritizeRequests=false
540 repl=Null
541 size=1024
542 subblock_size=0
543 system=system
544 tgts_per_mshr=12
545 trace_addr=0
546 two_queue=false
547 write_buffers=8
548 cpu_side=system.iobus.port[32]
549 mem_side=system.membus.port[3]
550
551 [system.l2c]
552 type=BaseCache
553 addr_range=0:18446744073709551615
554 assoc=8
555 block_size=64
556 forward_snoops=true
557 hash_delay=1
558 is_top_level=false
559 latency=10000
560 max_miss_count=0
561 mshrs=92
562 prefetch_on_access=false
563 prefetcher=Null
564 prioritizeRequests=false
565 repl=Null
566 size=4194304
567 subblock_size=0
568 system=system
569 tgts_per_mshr=16
570 trace_addr=0
571 two_queue=false
572 write_buffers=8
573 cpu_side=system.toL2Bus.port[0]
574 mem_side=system.membus.port[4]
575
576 [system.membus]
577 type=Bus
578 children=badaddr_responder
579 block_size=64
580 bus_id=1
581 clock=1000
582 header_cycles=1
583 use_default_range=false
584 width=64
585 default=system.membus.badaddr_responder.pio
586 port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
587
588 [system.membus.badaddr_responder]
589 type=IsaFake
590 fake_mem=false
591 pio_addr=0
592 pio_latency=1000
593 pio_size=8
594 ret_bad_addr=true
595 ret_data16=65535
596 ret_data32=4294967295
597 ret_data64=18446744073709551615
598 ret_data8=255
599 system=system
600 update_data=false
601 warn_access=
602 pio=system.membus.default
603
604 [system.physmem]
605 type=PhysicalMemory
606 file=
607 latency=30000
608 latency_var=0
609 null=false
610 range=0:134217727
611 zero=false
612 port=system.membus.port[1]
613
614 [system.simple_disk]
615 type=SimpleDisk
616 children=disk
617 disk=system.simple_disk.disk
618 system=system
619
620 [system.simple_disk.disk]
621 type=RawDiskImage
622 image_file=/dist/m5/system/disks/linux-latest.img
623 read_only=true
624
625 [system.terminal]
626 type=Terminal
627 intr_control=system.intrctrl
628 number=0
629 output=true
630 port=3456
631
632 [system.toL2Bus]
633 type=Bus
634 block_size=64
635 bus_id=0
636 clock=1000
637 header_cycles=1
638 use_default_range=false
639 width=64
640 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
641
642 [system.tsunami]
643 type=Tsunami
644 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
645 intrctrl=system.intrctrl
646 system=system
647
648 [system.tsunami.backdoor]
649 type=AlphaBackdoor
650 cpu=system.cpu
651 disk=system.simple_disk
652 pio_addr=8804682956800
653 pio_latency=1000
654 platform=system.tsunami
655 system=system
656 terminal=system.terminal
657 pio=system.iobus.port[25]
658
659 [system.tsunami.cchip]
660 type=TsunamiCChip
661 pio_addr=8803072344064
662 pio_latency=1000
663 system=system
664 tsunami=system.tsunami
665 pio=system.iobus.port[1]
666
667 [system.tsunami.ethernet]
668 type=NSGigE
669 BAR0=1
670 BAR0LegacyIO=false
671 BAR0Size=256
672 BAR1=0
673 BAR1LegacyIO=false
674 BAR1Size=4096
675 BAR2=0
676 BAR2LegacyIO=false
677 BAR2Size=0
678 BAR3=0
679 BAR3LegacyIO=false
680 BAR3Size=0
681 BAR4=0
682 BAR4LegacyIO=false
683 BAR4Size=0
684 BAR5=0
685 BAR5LegacyIO=false
686 BAR5Size=0
687 BIST=0
688 CacheLineSize=0
689 CardbusCIS=0
690 ClassCode=2
691 Command=0
692 DeviceID=34
693 ExpansionROM=0
694 HeaderType=0
695 InterruptLine=30
696 InterruptPin=1
697 LatencyTimer=0
698 MaximumLatency=52
699 MinimumGrant=176
700 ProgIF=0
701 Revision=0
702 Status=656
703 SubClassCode=0
704 SubsystemID=0
705 SubsystemVendorID=0
706 VendorID=4107
707 clock=0
708 config_latency=20000
709 dma_data_free=false
710 dma_desc_free=false
711 dma_no_allocate=true
712 dma_read_delay=0
713 dma_read_factor=0
714 dma_write_delay=0
715 dma_write_factor=0
716 hardware_address=00:90:00:00:00:01
717 intr_delay=10000000
718 max_backoff_delay=10000000
719 min_backoff_delay=4000
720 pci_bus=0
721 pci_dev=1
722 pci_func=0
723 pio_latency=1000
724 platform=system.tsunami
725 rss=false
726 rx_delay=1000000
727 rx_fifo_size=524288
728 rx_filter=true
729 rx_thread=false
730 system=system
731 tx_delay=1000000
732 tx_fifo_size=524288
733 tx_thread=false
734 config=system.iobus.port[30]
735 dma=system.iobus.port[31]
736 pio=system.iobus.port[29]
737
738 [system.tsunami.fake_OROM]
739 type=IsaFake
740 fake_mem=false
741 pio_addr=8796093677568
742 pio_latency=1000
743 pio_size=393216
744 ret_bad_addr=false
745 ret_data16=65535
746 ret_data32=4294967295
747 ret_data64=18446744073709551615
748 ret_data8=255
749 system=system
750 update_data=false
751 warn_access=
752 pio=system.iobus.port[9]
753
754 [system.tsunami.fake_ata0]
755 type=IsaFake
756 fake_mem=false
757 pio_addr=8804615848432
758 pio_latency=1000
759 pio_size=8
760 ret_bad_addr=false
761 ret_data16=65535
762 ret_data32=4294967295
763 ret_data64=18446744073709551615
764 ret_data8=255
765 system=system
766 update_data=false
767 warn_access=
768 pio=system.iobus.port[20]
769
770 [system.tsunami.fake_ata1]
771 type=IsaFake
772 fake_mem=false
773 pio_addr=8804615848304
774 pio_latency=1000
775 pio_size=8
776 ret_bad_addr=false
777 ret_data16=65535
778 ret_data32=4294967295
779 ret_data64=18446744073709551615
780 ret_data8=255
781 system=system
782 update_data=false
783 warn_access=
784 pio=system.iobus.port[21]
785
786 [system.tsunami.fake_pnp_addr]
787 type=IsaFake
788 fake_mem=false
789 pio_addr=8804615848569
790 pio_latency=1000
791 pio_size=8
792 ret_bad_addr=false
793 ret_data16=65535
794 ret_data32=4294967295
795 ret_data64=18446744073709551615
796 ret_data8=255
797 system=system
798 update_data=false
799 warn_access=
800 pio=system.iobus.port[10]
801
802 [system.tsunami.fake_pnp_read0]
803 type=IsaFake
804 fake_mem=false
805 pio_addr=8804615848451
806 pio_latency=1000
807 pio_size=8
808 ret_bad_addr=false
809 ret_data16=65535
810 ret_data32=4294967295
811 ret_data64=18446744073709551615
812 ret_data8=255
813 system=system
814 update_data=false
815 warn_access=
816 pio=system.iobus.port[12]
817
818 [system.tsunami.fake_pnp_read1]
819 type=IsaFake
820 fake_mem=false
821 pio_addr=8804615848515
822 pio_latency=1000
823 pio_size=8
824 ret_bad_addr=false
825 ret_data16=65535
826 ret_data32=4294967295
827 ret_data64=18446744073709551615
828 ret_data8=255
829 system=system
830 update_data=false
831 warn_access=
832 pio=system.iobus.port[13]
833
834 [system.tsunami.fake_pnp_read2]
835 type=IsaFake
836 fake_mem=false
837 pio_addr=8804615848579
838 pio_latency=1000
839 pio_size=8
840 ret_bad_addr=false
841 ret_data16=65535
842 ret_data32=4294967295
843 ret_data64=18446744073709551615
844 ret_data8=255
845 system=system
846 update_data=false
847 warn_access=
848 pio=system.iobus.port[14]
849
850 [system.tsunami.fake_pnp_read3]
851 type=IsaFake
852 fake_mem=false
853 pio_addr=8804615848643
854 pio_latency=1000
855 pio_size=8
856 ret_bad_addr=false
857 ret_data16=65535
858 ret_data32=4294967295
859 ret_data64=18446744073709551615
860 ret_data8=255
861 system=system
862 update_data=false
863 warn_access=
864 pio=system.iobus.port[15]
865
866 [system.tsunami.fake_pnp_read4]
867 type=IsaFake
868 fake_mem=false
869 pio_addr=8804615848707
870 pio_latency=1000
871 pio_size=8
872 ret_bad_addr=false
873 ret_data16=65535
874 ret_data32=4294967295
875 ret_data64=18446744073709551615
876 ret_data8=255
877 system=system
878 update_data=false
879 warn_access=
880 pio=system.iobus.port[16]
881
882 [system.tsunami.fake_pnp_read5]
883 type=IsaFake
884 fake_mem=false
885 pio_addr=8804615848771
886 pio_latency=1000
887 pio_size=8
888 ret_bad_addr=false
889 ret_data16=65535
890 ret_data32=4294967295
891 ret_data64=18446744073709551615
892 ret_data8=255
893 system=system
894 update_data=false
895 warn_access=
896 pio=system.iobus.port[17]
897
898 [system.tsunami.fake_pnp_read6]
899 type=IsaFake
900 fake_mem=false
901 pio_addr=8804615848835
902 pio_latency=1000
903 pio_size=8
904 ret_bad_addr=false
905 ret_data16=65535
906 ret_data32=4294967295
907 ret_data64=18446744073709551615
908 ret_data8=255
909 system=system
910 update_data=false
911 warn_access=
912 pio=system.iobus.port[18]
913
914 [system.tsunami.fake_pnp_read7]
915 type=IsaFake
916 fake_mem=false
917 pio_addr=8804615848899
918 pio_latency=1000
919 pio_size=8
920 ret_bad_addr=false
921 ret_data16=65535
922 ret_data32=4294967295
923 ret_data64=18446744073709551615
924 ret_data8=255
925 system=system
926 update_data=false
927 warn_access=
928 pio=system.iobus.port[19]
929
930 [system.tsunami.fake_pnp_write]
931 type=IsaFake
932 fake_mem=false
933 pio_addr=8804615850617
934 pio_latency=1000
935 pio_size=8
936 ret_bad_addr=false
937 ret_data16=65535
938 ret_data32=4294967295
939 ret_data64=18446744073709551615
940 ret_data8=255
941 system=system
942 update_data=false
943 warn_access=
944 pio=system.iobus.port[11]
945
946 [system.tsunami.fake_ppc]
947 type=IsaFake
948 fake_mem=false
949 pio_addr=8804615848891
950 pio_latency=1000
951 pio_size=8
952 ret_bad_addr=false
953 ret_data16=65535
954 ret_data32=4294967295
955 ret_data64=18446744073709551615
956 ret_data8=255
957 system=system
958 update_data=false
959 warn_access=
960 pio=system.iobus.port[8]
961
962 [system.tsunami.fake_sm_chip]
963 type=IsaFake
964 fake_mem=false
965 pio_addr=8804615848816
966 pio_latency=1000
967 pio_size=8
968 ret_bad_addr=false
969 ret_data16=65535
970 ret_data32=4294967295
971 ret_data64=18446744073709551615
972 ret_data8=255
973 system=system
974 update_data=false
975 warn_access=
976 pio=system.iobus.port[3]
977
978 [system.tsunami.fake_uart1]
979 type=IsaFake
980 fake_mem=false
981 pio_addr=8804615848696
982 pio_latency=1000
983 pio_size=8
984 ret_bad_addr=false
985 ret_data16=65535
986 ret_data32=4294967295
987 ret_data64=18446744073709551615
988 ret_data8=255
989 system=system
990 update_data=false
991 warn_access=
992 pio=system.iobus.port[4]
993
994 [system.tsunami.fake_uart2]
995 type=IsaFake
996 fake_mem=false
997 pio_addr=8804615848936
998 pio_latency=1000
999 pio_size=8
1000 ret_bad_addr=false
1001 ret_data16=65535
1002 ret_data32=4294967295
1003 ret_data64=18446744073709551615
1004 ret_data8=255
1005 system=system
1006 update_data=false
1007 warn_access=
1008 pio=system.iobus.port[5]
1009
1010 [system.tsunami.fake_uart3]
1011 type=IsaFake
1012 fake_mem=false
1013 pio_addr=8804615848680
1014 pio_latency=1000
1015 pio_size=8
1016 ret_bad_addr=false
1017 ret_data16=65535
1018 ret_data32=4294967295
1019 ret_data64=18446744073709551615
1020 ret_data8=255
1021 system=system
1022 update_data=false
1023 warn_access=
1024 pio=system.iobus.port[6]
1025
1026 [system.tsunami.fake_uart4]
1027 type=IsaFake
1028 fake_mem=false
1029 pio_addr=8804615848944
1030 pio_latency=1000
1031 pio_size=8
1032 ret_bad_addr=false
1033 ret_data16=65535
1034 ret_data32=4294967295
1035 ret_data64=18446744073709551615
1036 ret_data8=255
1037 system=system
1038 update_data=false
1039 warn_access=
1040 pio=system.iobus.port[7]
1041
1042 [system.tsunami.fb]
1043 type=BadDevice
1044 devicename=FrameBuffer
1045 pio_addr=8804615848912
1046 pio_latency=1000
1047 system=system
1048 pio=system.iobus.port[22]
1049
1050 [system.tsunami.ide]
1051 type=IdeController
1052 BAR0=1
1053 BAR0LegacyIO=false
1054 BAR0Size=8
1055 BAR1=1
1056 BAR1LegacyIO=false
1057 BAR1Size=4
1058 BAR2=1
1059 BAR2LegacyIO=false
1060 BAR2Size=8
1061 BAR3=1
1062 BAR3LegacyIO=false
1063 BAR3Size=4
1064 BAR4=1
1065 BAR4LegacyIO=false
1066 BAR4Size=16
1067 BAR5=1
1068 BAR5LegacyIO=false
1069 BAR5Size=0
1070 BIST=0
1071 CacheLineSize=0
1072 CardbusCIS=0
1073 ClassCode=1
1074 Command=0
1075 DeviceID=28945
1076 ExpansionROM=0
1077 HeaderType=0
1078 InterruptLine=31
1079 InterruptPin=1
1080 LatencyTimer=0
1081 MaximumLatency=0
1082 MinimumGrant=0
1083 ProgIF=133
1084 Revision=0
1085 Status=640
1086 SubClassCode=1
1087 SubsystemID=0
1088 SubsystemVendorID=0
1089 VendorID=32902
1090 config_latency=20000
1091 ctrl_offset=0
1092 disks=system.disk0 system.disk2
1093 io_shift=0
1094 max_backoff_delay=10000000
1095 min_backoff_delay=4000
1096 pci_bus=0
1097 pci_dev=0
1098 pci_func=0
1099 pio_latency=1000
1100 platform=system.tsunami
1101 system=system
1102 config=system.iobus.port[27]
1103 dma=system.iobus.port[28]
1104 pio=system.iobus.port[26]
1105
1106 [system.tsunami.io]
1107 type=TsunamiIO
1108 frequency=976562500
1109 pio_addr=8804615847936
1110 pio_latency=1000
1111 system=system
1112 time=Thu Jan 1 00:00:00 2009
1113 tsunami=system.tsunami
1114 year_is_bcd=false
1115 pio=system.iobus.port[23]
1116
1117 [system.tsunami.pchip]
1118 type=TsunamiPChip
1119 pio_addr=8802535473152
1120 pio_latency=1000
1121 system=system
1122 tsunami=system.tsunami
1123 pio=system.iobus.port[2]
1124
1125 [system.tsunami.pciconfig]
1126 type=PciConfigAll
1127 bus=0
1128 pio_latency=1
1129 platform=system.tsunami
1130 size=16777216
1131 system=system
1132 pio=system.iobus.default
1133
1134 [system.tsunami.uart]
1135 type=Uart8250
1136 pio_addr=8804615848952
1137 pio_latency=1000
1138 platform=system.tsunami
1139 system=system
1140 terminal=system.terminal
1141 pio=system.iobus.port[24]
1142