2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.859851 # Number of seconds simulated
4 sim_ticks 1859850554500 # Number of ticks simulated
5 final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 100457 # Simulator instruction rate (inst/s)
8 host_tick_rate 3519496587 # Simulator tick rate (ticks/s)
9 host_mem_usage 323652 # Number of bytes of host memory used
10 host_seconds 528.44 # Real time elapsed on the host
11 sim_insts 53085804 # Number of instructions simulated
12 system.physmem.bytes_read 29820864 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 10193536 # Number of bytes written to this memory
15 system.physmem.num_reads 465951 # Number of read requests responded to by this memory
16 system.physmem.num_writes 159274 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s)
22 system.l2c.replacements 391353 # number of replacements
23 system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use
24 system.l2c.total_refs 2406767 # Total number of references to valid blocks.
25 system.l2c.sampled_refs 424249 # Sample count of references to valid blocks.
26 system.l2c.avg_refs 5.673006 # Average number of references to valid blocks.
27 system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit.
28 system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context
29 system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context
30 system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy
31 system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy
32 system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits
33 system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits
34 system.l2c.Writeback_hits::0 835189 # number of Writeback hits
35 system.l2c.Writeback_hits::total 835189 # number of Writeback hits
36 system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits
37 system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits
38 system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits
39 system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
40 system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits
41 system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits
42 system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits
43 system.l2c.demand_hits::1 0 # number of demand (read+write) hits
44 system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits
45 system.l2c.overall_hits::0 1984005 # number of overall hits
46 system.l2c.overall_hits::1 0 # number of overall hits
47 system.l2c.overall_hits::total 1984005 # number of overall hits
48 system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses
49 system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses
50 system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses
51 system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses
52 system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses
53 system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses
54 system.l2c.demand_misses::0 425026 # number of demand (read+write) misses
55 system.l2c.demand_misses::1 0 # number of demand (read+write) misses
56 system.l2c.demand_misses::total 425026 # number of demand (read+write) misses
57 system.l2c.overall_misses::0 425026 # number of overall misses
58 system.l2c.overall_misses::1 0 # number of overall misses
59 system.l2c.overall_misses::total 425026 # number of overall misses
60 system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles
61 system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles
62 system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles
63 system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles
64 system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles
65 system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses)
66 system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses)
67 system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses)
68 system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses)
69 system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses)
70 system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses)
71 system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses)
72 system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
73 system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses)
74 system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses)
75 system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses
76 system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
77 system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses
78 system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses
79 system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
80 system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses
81 system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses
82 system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses
83 system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses
84 system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses
85 system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
86 system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
87 system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses
88 system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
89 system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
90 system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency
91 system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
92 system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
93 system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency
94 system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
95 system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
96 system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency
97 system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
98 system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
99 system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency
100 system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
101 system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
102 system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency
103 system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
104 system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
105 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
107 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
108 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
109 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
110 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
111 system.l2c.fast_writes 0 # number of fast writes performed
112 system.l2c.cache_copies 0 # number of cache copies performed
113 system.l2c.writebacks 117762 # number of writebacks
114 system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
115 system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
116 system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses
117 system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
118 system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses
119 system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses
120 system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses
121 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
122 system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles
123 system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles
124 system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles
125 system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles
126 system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles
127 system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles
128 system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles
129 system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles
130 system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses
131 system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
132 system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
133 system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses
134 system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
135 system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
136 system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses
137 system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
138 system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
139 system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses
140 system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
141 system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
142 system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses
143 system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
144 system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
145 system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency
146 system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency
147 system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency
148 system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency
149 system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency
150 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
151 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
152 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
153 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
154 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
155 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
156 system.iocache.replacements 41685 # number of replacements
157 system.iocache.tagsinuse 1.276011 # Cycle average of tags in use
158 system.iocache.total_refs 0 # Total number of references to valid blocks.
159 system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
160 system.iocache.avg_refs 0 # Average number of references to valid blocks.
161 system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit.
162 system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context
163 system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy
164 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
165 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
166 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
167 system.iocache.overall_hits::0 0 # number of overall hits
168 system.iocache.overall_hits::1 0 # number of overall hits
169 system.iocache.overall_hits::total 0 # number of overall hits
170 system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
171 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
172 system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
173 system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
174 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
175 system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
176 system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
177 system.iocache.overall_misses::0 0 # number of overall misses
178 system.iocache.overall_misses::1 41725 # number of overall misses
179 system.iocache.overall_misses::total 41725 # number of overall misses
180 system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
181 system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles
182 system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles
183 system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles
184 system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
185 system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
186 system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
187 system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
188 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
189 system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
190 system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
191 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
192 system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
193 system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
194 system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
195 system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
196 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
197 system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
198 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
199 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
200 system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
201 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
202 system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
203 system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
204 system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
205 system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
206 system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency
207 system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
208 system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
209 system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency
210 system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
211 system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
212 system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency
213 system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
214 system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked
215 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
216 system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked
217 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
218 system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked
219 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
220 system.iocache.fast_writes 0 # number of fast writes performed
221 system.iocache.cache_copies 0 # number of cache copies performed
222 system.iocache.writebacks 41512 # number of writebacks
223 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
224 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
225 system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
226 system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
227 system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
228 system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
229 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
230 system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
231 system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles
232 system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles
233 system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles
234 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
235 system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
236 system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
237 system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
238 system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
239 system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
240 system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
241 system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
242 system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
243 system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
244 system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
245 system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
246 system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
247 system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
248 system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency
249 system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency
250 system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency
251 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
252 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
253 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
254 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
255 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
256 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
257 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
258 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
259 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
260 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
261 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
262 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
263 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
264 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
265 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
266 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
267 system.cpu.dtb.fetch_hits 0 # ITB hits
268 system.cpu.dtb.fetch_misses 0 # ITB misses
269 system.cpu.dtb.fetch_acv 0 # ITB acv
270 system.cpu.dtb.fetch_accesses 0 # ITB accesses
271 system.cpu.dtb.read_hits 10136178 # DTB read hits
272 system.cpu.dtb.read_misses 46729 # DTB read misses
273 system.cpu.dtb.read_acv 584 # DTB read access violations
274 system.cpu.dtb.read_accesses 970980 # DTB read accesses
275 system.cpu.dtb.write_hits 6626287 # DTB write hits
276 system.cpu.dtb.write_misses 12218 # DTB write misses
277 system.cpu.dtb.write_acv 419 # DTB write access violations
278 system.cpu.dtb.write_accesses 347267 # DTB write accesses
279 system.cpu.dtb.data_hits 16762465 # DTB hits
280 system.cpu.dtb.data_misses 58947 # DTB misses
281 system.cpu.dtb.data_acv 1003 # DTB access violations
282 system.cpu.dtb.data_accesses 1318247 # DTB accesses
283 system.cpu.itb.fetch_hits 1326719 # ITB hits
284 system.cpu.itb.fetch_misses 39613 # ITB misses
285 system.cpu.itb.fetch_acv 1063 # ITB acv
286 system.cpu.itb.fetch_accesses 1366332 # ITB accesses
287 system.cpu.itb.read_hits 0 # DTB read hits
288 system.cpu.itb.read_misses 0 # DTB read misses
289 system.cpu.itb.read_acv 0 # DTB read access violations
290 system.cpu.itb.read_accesses 0 # DTB read accesses
291 system.cpu.itb.write_hits 0 # DTB write hits
292 system.cpu.itb.write_misses 0 # DTB write misses
293 system.cpu.itb.write_acv 0 # DTB write access violations
294 system.cpu.itb.write_accesses 0 # DTB write accesses
295 system.cpu.itb.data_hits 0 # DTB hits
296 system.cpu.itb.data_misses 0 # DTB misses
297 system.cpu.itb.data_acv 0 # DTB access violations
298 system.cpu.itb.data_accesses 0 # DTB accesses
299 system.cpu.numCycles 116271514 # number of cpu cycles simulated
300 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302 system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups
303 system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted
304 system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect
305 system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups
306 system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits
307 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
308 system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target.
309 system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions.
310 system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss
311 system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed
312 system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered
313 system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken
314 system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked
315 system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing
316 system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked
317 system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
318 system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps
319 system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions
320 system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR
321 system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched
322 system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed
323 system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle
341 system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle
342 system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle
343 system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked
344 system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running
345 system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking
346 system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing
347 system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch
348 system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction
349 system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode
350 system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode
351 system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing
352 system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle
353 system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking
354 system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst
355 system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running
356 system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking
357 system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename
358 system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full
359 system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full
360 system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full
361 system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed
362 system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made
363 system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups
364 system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups
365 system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed
366 system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing
367 system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed
368 system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed
369 system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer
370 system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit.
371 system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit.
372 system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads.
373 system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores.
374 system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec)
375 system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ
376 system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued
377 system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued
378 system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling
379 system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph
380 system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed
381 system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle
398 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
399 system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available
400 system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available
401 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available
404 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available
405 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available
406 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available
407 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
428 system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available
429 system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available
430 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
431 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
432 system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
433 system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued
434 system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued
435 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued
438 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued
439 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued
440 system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued
441 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued
462 system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued
463 system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued
464 system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued
465 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
466 system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued
467 system.cpu.iq.rate 0.498544 # Inst issue rate
468 system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested
469 system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst)
470 system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads
471 system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes
472 system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses
473 system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads
474 system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes
475 system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses
476 system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses
477 system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses
478 system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores
479 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
480 system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed
481 system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed
482 system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations
483 system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed
484 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
485 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
486 system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled
487 system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked
488 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
489 system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing
490 system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking
491 system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking
492 system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ
493 system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch
494 system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions
495 system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions
496 system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions
497 system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall
498 system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall
499 system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations
500 system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly
501 system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly
502 system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute
503 system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions
504 system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed
505 system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute
506 system.cpu.iew.exec_swp 0 # number of swp insts executed
507 system.cpu.iew.exec_nop 3625473 # number of nop insts executed
508 system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed
509 system.cpu.iew.exec_branches 9097936 # Number of branches executed
510 system.cpu.iew.exec_stores 6653902 # Number of stores executed
511 system.cpu.iew.exec_rate 0.492563 # Inst execution rate
512 system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit
513 system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back
514 system.cpu.iew.wb_producers 28030988 # num instructions producing a value
515 system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value
516 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
517 system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle
518 system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back
519 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
520 system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions
521 system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit
522 system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards
523 system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted
524 system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle
541 system.cpu.commit.count 56280196 # Number of instructions committed
542 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
543 system.cpu.commit.refs 15504446 # Number of memory references committed
544 system.cpu.commit.loads 9112319 # Number of loads committed
545 system.cpu.commit.membars 227818 # Number of memory barriers committed
546 system.cpu.commit.branches 8461284 # Number of branches committed
547 system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
548 system.cpu.commit.int_insts 52119152 # Number of committed integer instructions.
549 system.cpu.commit.function_calls 744404 # Number of function calls committed.
550 system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached
551 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
552 system.cpu.rob.rob_reads 143937484 # The number of ROB reads
553 system.cpu.rob.rob_writes 132136289 # The number of ROB writes
554 system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself
555 system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling
556 system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
557 system.cpu.committedInsts 53085804 # Number of Instructions Simulated
558 system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated
559 system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction
560 system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads
561 system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle
562 system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads
563 system.cpu.int_regfile_reads 75080091 # number of integer regfile reads
564 system.cpu.int_regfile_writes 40965330 # number of integer regfile writes
565 system.cpu.fp_regfile_reads 166532 # number of floating regfile reads
566 system.cpu.fp_regfile_writes 167403 # number of floating regfile writes
567 system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads
568 system.cpu.misc_regfile_writes 949674 # number of misc regfile writes
569 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
570 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
571 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
572 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
573 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
574 system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
575 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
576 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
577 system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
578 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
579 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
580 system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
581 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
582 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
583 system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
584 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
585 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
586 system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
587 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
588 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
589 system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
590 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
591 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
592 system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
593 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
594 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
595 system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
596 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
597 system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
598 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
599 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
600 system.cpu.icache.replacements 1004588 # number of replacements
601 system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use
602 system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks.
603 system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks.
604 system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks.
605 system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit.
606 system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context
607 system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy
608 system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits
609 system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits
610 system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits
611 system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
612 system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits
613 system.cpu.icache.overall_hits::0 7985770 # number of overall hits
614 system.cpu.icache.overall_hits::1 0 # number of overall hits
615 system.cpu.icache.overall_hits::total 7985770 # number of overall hits
616 system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses
617 system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses
618 system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses
619 system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
620 system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses
621 system.cpu.icache.overall_misses::0 1065446 # number of overall misses
622 system.cpu.icache.overall_misses::1 0 # number of overall misses
623 system.cpu.icache.overall_misses::total 1065446 # number of overall misses
624 system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles
625 system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles
626 system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles
627 system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses)
628 system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses)
629 system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses
630 system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
631 system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses
632 system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses
633 system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
634 system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses
635 system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses
636 system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses
637 system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
638 system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
639 system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses
640 system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
641 system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
642 system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency
643 system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
644 system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
645 system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency
646 system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
647 system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
648 system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency
649 system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
650 system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
651 system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked
652 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
653 system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
654 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
655 system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked
656 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
657 system.cpu.icache.fast_writes 0 # number of fast writes performed
658 system.cpu.icache.cache_copies 0 # number of cache copies performed
659 system.cpu.icache.writebacks 234 # number of writebacks
660 system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits
661 system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits
662 system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits
663 system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses
664 system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses
665 system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses
666 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
667 system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles
668 system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles
669 system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles
670 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
671 system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses
672 system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
673 system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
674 system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses
675 system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
676 system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
677 system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses
678 system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
679 system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
680 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency
681 system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
682 system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
683 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
684 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
685 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
686 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
687 system.cpu.dcache.replacements 1403406 # number of replacements
688 system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use
689 system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks.
690 system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks.
691 system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks.
692 system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit.
693 system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context
694 system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy
695 system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits
696 system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits
697 system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits
698 system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits
699 system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits
700 system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits
701 system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits
702 system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits
703 system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits
704 system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
705 system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits
706 system.cpu.dcache.overall_hits::0 11674234 # number of overall hits
707 system.cpu.dcache.overall_hits::1 0 # number of overall hits
708 system.cpu.dcache.overall_hits::total 11674234 # number of overall hits
709 system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses
710 system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses
711 system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses
712 system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses
713 system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses
714 system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses
715 system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses
716 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
717 system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses
718 system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
719 system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses
720 system.cpu.dcache.overall_misses::0 3745657 # number of overall misses
721 system.cpu.dcache.overall_misses::1 0 # number of overall misses
722 system.cpu.dcache.overall_misses::total 3745657 # number of overall misses
723 system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles
724 system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles
725 system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles
726 system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles
727 system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles
728 system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles
729 system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses)
730 system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses)
731 system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses)
732 system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses)
733 system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses)
734 system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses)
735 system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses)
736 system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses)
737 system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses
738 system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
739 system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses
740 system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses
741 system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
742 system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses
743 system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses
744 system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses
745 system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses
746 system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses
747 system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses
748 system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
749 system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
750 system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses
751 system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
752 system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
753 system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency
754 system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
755 system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
756 system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency
757 system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
758 system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
759 system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency
760 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
761 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
762 system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency
763 system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
764 system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
765 system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency
766 system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
767 system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
768 system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency
769 system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
770 system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
771 system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked
772 system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked
773 system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked
774 system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
775 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked
776 system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked
777 system.cpu.dcache.fast_writes 0 # number of fast writes performed
778 system.cpu.dcache.cache_copies 0 # number of cache copies performed
779 system.cpu.dcache.writebacks 834955 # number of writebacks
780 system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits
781 system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits
782 system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits
783 system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits
784 system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits
785 system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses
786 system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses
787 system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses
788 system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses
789 system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses
790 system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses
791 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
792 system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles
793 system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles
794 system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles
795 system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles
796 system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles
797 system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles
798 system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles
799 system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles
800 system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles
801 system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses
802 system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
803 system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
804 system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses
805 system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
806 system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
807 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses
808 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
809 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
810 system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses
811 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
812 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
813 system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses
814 system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
815 system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
816 system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses
817 system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
818 system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
819 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency
820 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency
821 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency
822 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
823 system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
824 system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
825 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
826 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
827 system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
828 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
829 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
830 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
831 system.cpu.kern.inst.arm 0 # number of arm instructions executed
832 system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed
833 system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed
834 system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl
835 system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl
836 system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl
837 system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl
838 system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl
839 system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl
840 system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl
841 system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl
842 system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl
843 system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl
844 system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl
845 system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl
846 system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl
847 system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl
848 system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl
849 system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl
850 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
851 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
852 system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl
853 system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
854 system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
855 system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
856 system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
857 system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
858 system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
859 system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
860 system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
861 system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
862 system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
863 system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
864 system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
865 system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
866 system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
867 system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
868 system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
869 system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
870 system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
871 system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
872 system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
873 system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
874 system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
875 system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
876 system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
877 system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
878 system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
879 system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
880 system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
881 system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
882 system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
883 system.cpu.kern.syscall::total 326 # number of syscalls executed
884 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
885 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
886 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
887 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
888 system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
889 system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
890 system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
891 system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed
892 system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed
893 system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
894 system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
895 system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
896 system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
897 system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed
898 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
899 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
900 system.cpu.kern.callpal::total 192344 # number of callpals executed
901 system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
902 system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
903 system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches
904 system.cpu.kern.mode_good::kernel 1909
905 system.cpu.kern.mode_good::user 1739
906 system.cpu.kern.mode_good::idle 170
907 system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches
908 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
909 system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches
910 system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches
911 system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode
912 system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode
913 system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode
914 system.cpu.kern.swap_context 4177 # number of times the context was actually changed
916 ---------- End Simulation Statistics ----------
projects / gem5.git / blob