tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxAlphaSystem
  13 children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
  14 boot_cpu_frequency=500
  15 boot_osflags=root=/dev/hda1 console=ttyS0
  16 cache_line_size=64
  17 clk_domain=system.clk_domain
  18 console=/scratch/nilay/GEM5/system/binaries/console
  19 eventq_index=0
  20 init_param=0
  21 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 num_work_ids=16
  30 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
  31 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  32 symbolfile=
  33 system_rev=1024
  34 system_type=34
  35 work_begin_ckpt_count=0
  36 work_begin_cpu_id_exit=-1
  37 work_begin_exit_count=0
  38 work_cpus_ckpt_count=0
  39 work_end_ckpt_count=0
  40 work_end_exit_count=0
  41 work_item_id=-1
  42 system_port=system.membus.slave[0]
  43
  44 [system.bridge]
  45 type=Bridge
  46 clk_domain=system.clk_domain
  47 delay=50000
  48 eventq_index=0
  49 ranges=8796093022208:18446744073709551615
  50 req_size=16
  51 resp_size=16
  52 master=system.iobus.slave[0]
  53 slave=system.membus.master[0]
  54
  55 [system.clk_domain]
  56 type=SrcClockDomain
  57 clock=1000
  58 domain_id=-1
  59 eventq_index=0
  60 init_perf_level=0
  61 voltage_domain=system.voltage_domain
  62
  63 [system.cpu0]
  64 type=DerivO3CPU
  65 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
  66 LFSTSize=1024
  67 LQEntries=32
  68 LSQCheckLoads=true
  69 LSQDepCheckShift=4
  70 SQEntries=32
  71 SSITSize=1024
  72 activity=0
  73 backComSize=5
  74 branchPred=system.cpu0.branchPred
  75 cachePorts=200
  76 checker=Null
  77 clk_domain=system.cpu_clk_domain
  78 commitToDecodeDelay=1
  79 commitToFetchDelay=1
  80 commitToIEWDelay=1
  81 commitToRenameDelay=1
  82 commitWidth=8
  83 cpu_id=0
  84 decodeToFetchDelay=1
  85 decodeToRenameDelay=1
  86 decodeWidth=8
  87 dispatchWidth=8
  88 do_checkpoint_insts=true
  89 do_quiesce=true
  90 do_statistics_insts=true
  91 dtb=system.cpu0.dtb
  92 eventq_index=0
  93 fetchBufferSize=64
  94 fetchQueueSize=32
  95 fetchToDecodeDelay=1
  96 fetchTrapLatency=1
  97 fetchWidth=8
  98 forwardComSize=5
  99 fuPool=system.cpu0.fuPool
 100 function_trace=false
 101 function_trace_start=0
 102 iewToCommitDelay=1
 103 iewToDecodeDelay=1
 104 iewToFetchDelay=1
 105 iewToRenameDelay=1
 106 interrupts=system.cpu0.interrupts
 107 isa=system.cpu0.isa
 108 issueToExecuteDelay=1
 109 issueWidth=8
 110 itb=system.cpu0.itb
 111 max_insts_all_threads=0
 112 max_insts_any_thread=0
 113 max_loads_all_threads=0
 114 max_loads_any_thread=0
 115 needsTSO=false
 116 numIQEntries=64
 117 numPhysCCRegs=0
 118 numPhysFloatRegs=256
 119 numPhysIntRegs=256
 120 numROBEntries=192
 121 numRobs=1
 122 numThreads=1
 123 profile=0
 124 progress_interval=0
 125 renameToDecodeDelay=1
 126 renameToFetchDelay=1
 127 renameToIEWDelay=2
 128 renameToROBDelay=1
 129 renameWidth=8
 130 simpoint_start_insts=
 131 smtCommitPolicy=RoundRobin
 132 smtFetchPolicy=SingleThread
 133 smtIQPolicy=Partitioned
 134 smtIQThreshold=100
 135 smtLSQPolicy=Partitioned
 136 smtLSQThreshold=100
 137 smtNumFetchingThreads=1
 138 smtROBPolicy=Partitioned
 139 smtROBThreshold=100
 140 socket_id=0
 141 squashWidth=8
 142 store_set_clear_period=250000
 143 switched_out=false
 144 system=system
 145 tracer=system.cpu0.tracer
 146 trapLatency=13
 147 wbWidth=8
 148 workload=
 149 dcache_port=system.cpu0.dcache.cpu_side
 150 icache_port=system.cpu0.icache.cpu_side
 151
 152 [system.cpu0.branchPred]
 153 type=TournamentBP
 154 BTBEntries=4096
 155 BTBTagSize=16
 156 RASSize=16
 157 choiceCtrBits=2
 158 choicePredictorSize=8192
 159 eventq_index=0
 160 globalCtrBits=2
 161 globalPredictorSize=8192
 162 instShiftAmt=2
 163 localCtrBits=2
 164 localHistoryTableSize=2048
 165 localPredictorSize=2048
 166 numThreads=1
 167
 168 [system.cpu0.dcache]
 169 type=BaseCache
 170 children=tags
 171 addr_ranges=0:18446744073709551615
 172 assoc=4
 173 clk_domain=system.cpu_clk_domain
 174 demand_mshr_reserve=1
 175 eventq_index=0
 176 forward_snoops=true
 177 hit_latency=2
 178 is_read_only=false
 179 max_miss_count=0
 180 mshrs=4
 181 prefetch_on_access=false
 182 prefetcher=Null
 183 response_latency=2
 184 sequential_access=false
 185 size=32768
 186 system=system
 187 tags=system.cpu0.dcache.tags
 188 tgts_per_mshr=20
 189 write_buffers=8
 190 cpu_side=system.cpu0.dcache_port
 191 mem_side=system.toL2Bus.slave[1]
 192
 193 [system.cpu0.dcache.tags]
 194 type=LRU
 195 assoc=4
 196 block_size=64
 197 clk_domain=system.cpu_clk_domain
 198 eventq_index=0
 199 hit_latency=2
 200 sequential_access=false
 201 size=32768
 202
 203 [system.cpu0.dtb]
 204 type=AlphaTLB
 205 eventq_index=0
 206 size=64
 207
 208 [system.cpu0.fuPool]
 209 type=FUPool
 210 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 211 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 212 eventq_index=0
 213
 214 [system.cpu0.fuPool.FUList0]
 215 type=FUDesc
 216 children=opList
 217 count=6
 218 eventq_index=0
 219 opList=system.cpu0.fuPool.FUList0.opList
 220
 221 [system.cpu0.fuPool.FUList0.opList]
 222 type=OpDesc
 223 eventq_index=0
 224 opClass=IntAlu
 225 opLat=1
 226 pipelined=true
 227
 228 [system.cpu0.fuPool.FUList1]
 229 type=FUDesc
 230 children=opList0 opList1
 231 count=2
 232 eventq_index=0
 233 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 234
 235 [system.cpu0.fuPool.FUList1.opList0]
 236 type=OpDesc
 237 eventq_index=0
 238 opClass=IntMult
 239 opLat=3
 240 pipelined=true
 241
 242 [system.cpu0.fuPool.FUList1.opList1]
 243 type=OpDesc
 244 eventq_index=0
 245 opClass=IntDiv
 246 opLat=20
 247 pipelined=false
 248
 249 [system.cpu0.fuPool.FUList2]
 250 type=FUDesc
 251 children=opList0 opList1 opList2
 252 count=4
 253 eventq_index=0
 254 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 255
 256 [system.cpu0.fuPool.FUList2.opList0]
 257 type=OpDesc
 258 eventq_index=0
 259 opClass=FloatAdd
 260 opLat=2
 261 pipelined=true
 262
 263 [system.cpu0.fuPool.FUList2.opList1]
 264 type=OpDesc
 265 eventq_index=0
 266 opClass=FloatCmp
 267 opLat=2
 268 pipelined=true
 269
 270 [system.cpu0.fuPool.FUList2.opList2]
 271 type=OpDesc
 272 eventq_index=0
 273 opClass=FloatCvt
 274 opLat=2
 275 pipelined=true
 276
 277 [system.cpu0.fuPool.FUList3]
 278 type=FUDesc
 279 children=opList0 opList1 opList2
 280 count=2
 281 eventq_index=0
 282 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 283
 284 [system.cpu0.fuPool.FUList3.opList0]
 285 type=OpDesc
 286 eventq_index=0
 287 opClass=FloatMult
 288 opLat=4
 289 pipelined=true
 290
 291 [system.cpu0.fuPool.FUList3.opList1]
 292 type=OpDesc
 293 eventq_index=0
 294 opClass=FloatDiv
 295 opLat=12
 296 pipelined=false
 297
 298 [system.cpu0.fuPool.FUList3.opList2]
 299 type=OpDesc
 300 eventq_index=0
 301 opClass=FloatSqrt
 302 opLat=24
 303 pipelined=false
 304
 305 [system.cpu0.fuPool.FUList4]
 306 type=FUDesc
 307 children=opList
 308 count=0
 309 eventq_index=0
 310 opList=system.cpu0.fuPool.FUList4.opList
 311
 312 [system.cpu0.fuPool.FUList4.opList]
 313 type=OpDesc
 314 eventq_index=0
 315 opClass=MemRead
 316 opLat=1
 317 pipelined=true
 318
 319 [system.cpu0.fuPool.FUList5]
 320 type=FUDesc
 321 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 322 count=4
 323 eventq_index=0
 324 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 325
 326 [system.cpu0.fuPool.FUList5.opList00]
 327 type=OpDesc
 328 eventq_index=0
 329 opClass=SimdAdd
 330 opLat=1
 331 pipelined=true
 332
 333 [system.cpu0.fuPool.FUList5.opList01]
 334 type=OpDesc
 335 eventq_index=0
 336 opClass=SimdAddAcc
 337 opLat=1
 338 pipelined=true
 339
 340 [system.cpu0.fuPool.FUList5.opList02]
 341 type=OpDesc
 342 eventq_index=0
 343 opClass=SimdAlu
 344 opLat=1
 345 pipelined=true
 346
 347 [system.cpu0.fuPool.FUList5.opList03]
 348 type=OpDesc
 349 eventq_index=0
 350 opClass=SimdCmp
 351 opLat=1
 352 pipelined=true
 353
 354 [system.cpu0.fuPool.FUList5.opList04]
 355 type=OpDesc
 356 eventq_index=0
 357 opClass=SimdCvt
 358 opLat=1
 359 pipelined=true
 360
 361 [system.cpu0.fuPool.FUList5.opList05]
 362 type=OpDesc
 363 eventq_index=0
 364 opClass=SimdMisc
 365 opLat=1
 366 pipelined=true
 367
 368 [system.cpu0.fuPool.FUList5.opList06]
 369 type=OpDesc
 370 eventq_index=0
 371 opClass=SimdMult
 372 opLat=1
 373 pipelined=true
 374
 375 [system.cpu0.fuPool.FUList5.opList07]
 376 type=OpDesc
 377 eventq_index=0
 378 opClass=SimdMultAcc
 379 opLat=1
 380 pipelined=true
 381
 382 [system.cpu0.fuPool.FUList5.opList08]
 383 type=OpDesc
 384 eventq_index=0
 385 opClass=SimdShift
 386 opLat=1
 387 pipelined=true
 388
 389 [system.cpu0.fuPool.FUList5.opList09]
 390 type=OpDesc
 391 eventq_index=0
 392 opClass=SimdShiftAcc
 393 opLat=1
 394 pipelined=true
 395
 396 [system.cpu0.fuPool.FUList5.opList10]
 397 type=OpDesc
 398 eventq_index=0
 399 opClass=SimdSqrt
 400 opLat=1
 401 pipelined=true
 402
 403 [system.cpu0.fuPool.FUList5.opList11]
 404 type=OpDesc
 405 eventq_index=0
 406 opClass=SimdFloatAdd
 407 opLat=1
 408 pipelined=true
 409
 410 [system.cpu0.fuPool.FUList5.opList12]
 411 type=OpDesc
 412 eventq_index=0
 413 opClass=SimdFloatAlu
 414 opLat=1
 415 pipelined=true
 416
 417 [system.cpu0.fuPool.FUList5.opList13]
 418 type=OpDesc
 419 eventq_index=0
 420 opClass=SimdFloatCmp
 421 opLat=1
 422 pipelined=true
 423
 424 [system.cpu0.fuPool.FUList5.opList14]
 425 type=OpDesc
 426 eventq_index=0
 427 opClass=SimdFloatCvt
 428 opLat=1
 429 pipelined=true
 430
 431 [system.cpu0.fuPool.FUList5.opList15]
 432 type=OpDesc
 433 eventq_index=0
 434 opClass=SimdFloatDiv
 435 opLat=1
 436 pipelined=true
 437
 438 [system.cpu0.fuPool.FUList5.opList16]
 439 type=OpDesc
 440 eventq_index=0
 441 opClass=SimdFloatMisc
 442 opLat=1
 443 pipelined=true
 444
 445 [system.cpu0.fuPool.FUList5.opList17]
 446 type=OpDesc
 447 eventq_index=0
 448 opClass=SimdFloatMult
 449 opLat=1
 450 pipelined=true
 451
 452 [system.cpu0.fuPool.FUList5.opList18]
 453 type=OpDesc
 454 eventq_index=0
 455 opClass=SimdFloatMultAcc
 456 opLat=1
 457 pipelined=true
 458
 459 [system.cpu0.fuPool.FUList5.opList19]
 460 type=OpDesc
 461 eventq_index=0
 462 opClass=SimdFloatSqrt
 463 opLat=1
 464 pipelined=true
 465
 466 [system.cpu0.fuPool.FUList6]
 467 type=FUDesc
 468 children=opList
 469 count=0
 470 eventq_index=0
 471 opList=system.cpu0.fuPool.FUList6.opList
 472
 473 [system.cpu0.fuPool.FUList6.opList]
 474 type=OpDesc
 475 eventq_index=0
 476 opClass=MemWrite
 477 opLat=1
 478 pipelined=true
 479
 480 [system.cpu0.fuPool.FUList7]
 481 type=FUDesc
 482 children=opList0 opList1
 483 count=4
 484 eventq_index=0
 485 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 486
 487 [system.cpu0.fuPool.FUList7.opList0]
 488 type=OpDesc
 489 eventq_index=0
 490 opClass=MemRead
 491 opLat=1
 492 pipelined=true
 493
 494 [system.cpu0.fuPool.FUList7.opList1]
 495 type=OpDesc
 496 eventq_index=0
 497 opClass=MemWrite
 498 opLat=1
 499 pipelined=true
 500
 501 [system.cpu0.fuPool.FUList8]
 502 type=FUDesc
 503 children=opList
 504 count=1
 505 eventq_index=0
 506 opList=system.cpu0.fuPool.FUList8.opList
 507
 508 [system.cpu0.fuPool.FUList8.opList]
 509 type=OpDesc
 510 eventq_index=0
 511 opClass=IprAccess
 512 opLat=3
 513 pipelined=false
 514
 515 [system.cpu0.icache]
 516 type=BaseCache
 517 children=tags
 518 addr_ranges=0:18446744073709551615
 519 assoc=1
 520 clk_domain=system.cpu_clk_domain
 521 demand_mshr_reserve=1
 522 eventq_index=0
 523 forward_snoops=true
 524 hit_latency=2
 525 is_read_only=true
 526 max_miss_count=0
 527 mshrs=4
 528 prefetch_on_access=false
 529 prefetcher=Null
 530 response_latency=2
 531 sequential_access=false
 532 size=32768
 533 system=system
 534 tags=system.cpu0.icache.tags
 535 tgts_per_mshr=20
 536 write_buffers=8
 537 cpu_side=system.cpu0.icache_port
 538 mem_side=system.toL2Bus.slave[0]
 539
 540 [system.cpu0.icache.tags]
 541 type=LRU
 542 assoc=1
 543 block_size=64
 544 clk_domain=system.cpu_clk_domain
 545 eventq_index=0
 546 hit_latency=2
 547 sequential_access=false
 548 size=32768
 549
 550 [system.cpu0.interrupts]
 551 type=AlphaInterrupts
 552 eventq_index=0
 553
 554 [system.cpu0.isa]
 555 type=AlphaISA
 556 eventq_index=0
 557 system=system
 558
 559 [system.cpu0.itb]
 560 type=AlphaTLB
 561 eventq_index=0
 562 size=48
 563
 564 [system.cpu0.tracer]
 565 type=ExeTracer
 566 eventq_index=0
 567
 568 [system.cpu1]
 569 type=DerivO3CPU
 570 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
 571 LFSTSize=1024
 572 LQEntries=32
 573 LSQCheckLoads=true
 574 LSQDepCheckShift=4
 575 SQEntries=32
 576 SSITSize=1024
 577 activity=0
 578 backComSize=5
 579 branchPred=system.cpu1.branchPred
 580 cachePorts=200
 581 checker=Null
 582 clk_domain=system.cpu_clk_domain
 583 commitToDecodeDelay=1
 584 commitToFetchDelay=1
 585 commitToIEWDelay=1
 586 commitToRenameDelay=1
 587 commitWidth=8
 588 cpu_id=1
 589 decodeToFetchDelay=1
 590 decodeToRenameDelay=1
 591 decodeWidth=8
 592 dispatchWidth=8
 593 do_checkpoint_insts=true
 594 do_quiesce=true
 595 do_statistics_insts=true
 596 dtb=system.cpu1.dtb
 597 eventq_index=0
 598 fetchBufferSize=64
 599 fetchQueueSize=32
 600 fetchToDecodeDelay=1
 601 fetchTrapLatency=1
 602 fetchWidth=8
 603 forwardComSize=5
 604 fuPool=system.cpu1.fuPool
 605 function_trace=false
 606 function_trace_start=0
 607 iewToCommitDelay=1
 608 iewToDecodeDelay=1
 609 iewToFetchDelay=1
 610 iewToRenameDelay=1
 611 interrupts=system.cpu1.interrupts
 612 isa=system.cpu1.isa
 613 issueToExecuteDelay=1
 614 issueWidth=8
 615 itb=system.cpu1.itb
 616 max_insts_all_threads=0
 617 max_insts_any_thread=0
 618 max_loads_all_threads=0
 619 max_loads_any_thread=0
 620 needsTSO=false
 621 numIQEntries=64
 622 numPhysCCRegs=0
 623 numPhysFloatRegs=256
 624 numPhysIntRegs=256
 625 numROBEntries=192
 626 numRobs=1
 627 numThreads=1
 628 profile=0
 629 progress_interval=0
 630 renameToDecodeDelay=1
 631 renameToFetchDelay=1
 632 renameToIEWDelay=2
 633 renameToROBDelay=1
 634 renameWidth=8
 635 simpoint_start_insts=
 636 smtCommitPolicy=RoundRobin
 637 smtFetchPolicy=SingleThread
 638 smtIQPolicy=Partitioned
 639 smtIQThreshold=100
 640 smtLSQPolicy=Partitioned
 641 smtLSQThreshold=100
 642 smtNumFetchingThreads=1
 643 smtROBPolicy=Partitioned
 644 smtROBThreshold=100
 645 socket_id=0
 646 squashWidth=8
 647 store_set_clear_period=250000
 648 switched_out=false
 649 system=system
 650 tracer=system.cpu1.tracer
 651 trapLatency=13
 652 wbWidth=8
 653 workload=
 654 dcache_port=system.cpu1.dcache.cpu_side
 655 icache_port=system.cpu1.icache.cpu_side
 656
 657 [system.cpu1.branchPred]
 658 type=TournamentBP
 659 BTBEntries=4096
 660 BTBTagSize=16
 661 RASSize=16
 662 choiceCtrBits=2
 663 choicePredictorSize=8192
 664 eventq_index=0
 665 globalCtrBits=2
 666 globalPredictorSize=8192
 667 instShiftAmt=2
 668 localCtrBits=2
 669 localHistoryTableSize=2048
 670 localPredictorSize=2048
 671 numThreads=1
 672
 673 [system.cpu1.dcache]
 674 type=BaseCache
 675 children=tags
 676 addr_ranges=0:18446744073709551615
 677 assoc=4
 678 clk_domain=system.cpu_clk_domain
 679 demand_mshr_reserve=1
 680 eventq_index=0
 681 forward_snoops=true
 682 hit_latency=2
 683 is_read_only=false
 684 max_miss_count=0
 685 mshrs=4
 686 prefetch_on_access=false
 687 prefetcher=Null
 688 response_latency=2
 689 sequential_access=false
 690 size=32768
 691 system=system
 692 tags=system.cpu1.dcache.tags
 693 tgts_per_mshr=20
 694 write_buffers=8
 695 cpu_side=system.cpu1.dcache_port
 696 mem_side=system.toL2Bus.slave[3]
 697
 698 [system.cpu1.dcache.tags]
 699 type=LRU
 700 assoc=4
 701 block_size=64
 702 clk_domain=system.cpu_clk_domain
 703 eventq_index=0
 704 hit_latency=2
 705 sequential_access=false
 706 size=32768
 707
 708 [system.cpu1.dtb]
 709 type=AlphaTLB
 710 eventq_index=0
 711 size=64
 712
 713 [system.cpu1.fuPool]
 714 type=FUPool
 715 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 716 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 717 eventq_index=0
 718
 719 [system.cpu1.fuPool.FUList0]
 720 type=FUDesc
 721 children=opList
 722 count=6
 723 eventq_index=0
 724 opList=system.cpu1.fuPool.FUList0.opList
 725
 726 [system.cpu1.fuPool.FUList0.opList]
 727 type=OpDesc
 728 eventq_index=0
 729 opClass=IntAlu
 730 opLat=1
 731 pipelined=true
 732
 733 [system.cpu1.fuPool.FUList1]
 734 type=FUDesc
 735 children=opList0 opList1
 736 count=2
 737 eventq_index=0
 738 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 739
 740 [system.cpu1.fuPool.FUList1.opList0]
 741 type=OpDesc
 742 eventq_index=0
 743 opClass=IntMult
 744 opLat=3
 745 pipelined=true
 746
 747 [system.cpu1.fuPool.FUList1.opList1]
 748 type=OpDesc
 749 eventq_index=0
 750 opClass=IntDiv
 751 opLat=20
 752 pipelined=false
 753
 754 [system.cpu1.fuPool.FUList2]
 755 type=FUDesc
 756 children=opList0 opList1 opList2
 757 count=4
 758 eventq_index=0
 759 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 760
 761 [system.cpu1.fuPool.FUList2.opList0]
 762 type=OpDesc
 763 eventq_index=0
 764 opClass=FloatAdd
 765 opLat=2
 766 pipelined=true
 767
 768 [system.cpu1.fuPool.FUList2.opList1]
 769 type=OpDesc
 770 eventq_index=0
 771 opClass=FloatCmp
 772 opLat=2
 773 pipelined=true
 774
 775 [system.cpu1.fuPool.FUList2.opList2]
 776 type=OpDesc
 777 eventq_index=0
 778 opClass=FloatCvt
 779 opLat=2
 780 pipelined=true
 781
 782 [system.cpu1.fuPool.FUList3]
 783 type=FUDesc
 784 children=opList0 opList1 opList2
 785 count=2
 786 eventq_index=0
 787 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 788
 789 [system.cpu1.fuPool.FUList3.opList0]
 790 type=OpDesc
 791 eventq_index=0
 792 opClass=FloatMult
 793 opLat=4
 794 pipelined=true
 795
 796 [system.cpu1.fuPool.FUList3.opList1]
 797 type=OpDesc
 798 eventq_index=0
 799 opClass=FloatDiv
 800 opLat=12
 801 pipelined=false
 802
 803 [system.cpu1.fuPool.FUList3.opList2]
 804 type=OpDesc
 805 eventq_index=0
 806 opClass=FloatSqrt
 807 opLat=24
 808 pipelined=false
 809
 810 [system.cpu1.fuPool.FUList4]
 811 type=FUDesc
 812 children=opList
 813 count=0
 814 eventq_index=0
 815 opList=system.cpu1.fuPool.FUList4.opList
 816
 817 [system.cpu1.fuPool.FUList4.opList]
 818 type=OpDesc
 819 eventq_index=0
 820 opClass=MemRead
 821 opLat=1
 822 pipelined=true
 823
 824 [system.cpu1.fuPool.FUList5]
 825 type=FUDesc
 826 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 827 count=4
 828 eventq_index=0
 829 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 830
 831 [system.cpu1.fuPool.FUList5.opList00]
 832 type=OpDesc
 833 eventq_index=0
 834 opClass=SimdAdd
 835 opLat=1
 836 pipelined=true
 837
 838 [system.cpu1.fuPool.FUList5.opList01]
 839 type=OpDesc
 840 eventq_index=0
 841 opClass=SimdAddAcc
 842 opLat=1
 843 pipelined=true
 844
 845 [system.cpu1.fuPool.FUList5.opList02]
 846 type=OpDesc
 847 eventq_index=0
 848 opClass=SimdAlu
 849 opLat=1
 850 pipelined=true
 851
 852 [system.cpu1.fuPool.FUList5.opList03]
 853 type=OpDesc
 854 eventq_index=0
 855 opClass=SimdCmp
 856 opLat=1
 857 pipelined=true
 858
 859 [system.cpu1.fuPool.FUList5.opList04]
 860 type=OpDesc
 861 eventq_index=0
 862 opClass=SimdCvt
 863 opLat=1
 864 pipelined=true
 865
 866 [system.cpu1.fuPool.FUList5.opList05]
 867 type=OpDesc
 868 eventq_index=0
 869 opClass=SimdMisc
 870 opLat=1
 871 pipelined=true
 872
 873 [system.cpu1.fuPool.FUList5.opList06]
 874 type=OpDesc
 875 eventq_index=0
 876 opClass=SimdMult
 877 opLat=1
 878 pipelined=true
 879
 880 [system.cpu1.fuPool.FUList5.opList07]
 881 type=OpDesc
 882 eventq_index=0
 883 opClass=SimdMultAcc
 884 opLat=1
 885 pipelined=true
 886
 887 [system.cpu1.fuPool.FUList5.opList08]
 888 type=OpDesc
 889 eventq_index=0
 890 opClass=SimdShift
 891 opLat=1
 892 pipelined=true
 893
 894 [system.cpu1.fuPool.FUList5.opList09]
 895 type=OpDesc
 896 eventq_index=0
 897 opClass=SimdShiftAcc
 898 opLat=1
 899 pipelined=true
 900
 901 [system.cpu1.fuPool.FUList5.opList10]
 902 type=OpDesc
 903 eventq_index=0
 904 opClass=SimdSqrt
 905 opLat=1
 906 pipelined=true
 907
 908 [system.cpu1.fuPool.FUList5.opList11]
 909 type=OpDesc
 910 eventq_index=0
 911 opClass=SimdFloatAdd
 912 opLat=1
 913 pipelined=true
 914
 915 [system.cpu1.fuPool.FUList5.opList12]
 916 type=OpDesc
 917 eventq_index=0
 918 opClass=SimdFloatAlu
 919 opLat=1
 920 pipelined=true
 921
 922 [system.cpu1.fuPool.FUList5.opList13]
 923 type=OpDesc
 924 eventq_index=0
 925 opClass=SimdFloatCmp
 926 opLat=1
 927 pipelined=true
 928
 929 [system.cpu1.fuPool.FUList5.opList14]
 930 type=OpDesc
 931 eventq_index=0
 932 opClass=SimdFloatCvt
 933 opLat=1
 934 pipelined=true
 935
 936 [system.cpu1.fuPool.FUList5.opList15]
 937 type=OpDesc
 938 eventq_index=0
 939 opClass=SimdFloatDiv
 940 opLat=1
 941 pipelined=true
 942
 943 [system.cpu1.fuPool.FUList5.opList16]
 944 type=OpDesc
 945 eventq_index=0
 946 opClass=SimdFloatMisc
 947 opLat=1
 948 pipelined=true
 949
 950 [system.cpu1.fuPool.FUList5.opList17]
 951 type=OpDesc
 952 eventq_index=0
 953 opClass=SimdFloatMult
 954 opLat=1
 955 pipelined=true
 956
 957 [system.cpu1.fuPool.FUList5.opList18]
 958 type=OpDesc
 959 eventq_index=0
 960 opClass=SimdFloatMultAcc
 961 opLat=1
 962 pipelined=true
 963
 964 [system.cpu1.fuPool.FUList5.opList19]
 965 type=OpDesc
 966 eventq_index=0
 967 opClass=SimdFloatSqrt
 968 opLat=1
 969 pipelined=true
 970
 971 [system.cpu1.fuPool.FUList6]
 972 type=FUDesc
 973 children=opList
 974 count=0
 975 eventq_index=0
 976 opList=system.cpu1.fuPool.FUList6.opList
 977
 978 [system.cpu1.fuPool.FUList6.opList]
 979 type=OpDesc
 980 eventq_index=0
 981 opClass=MemWrite
 982 opLat=1
 983 pipelined=true
 984
 985 [system.cpu1.fuPool.FUList7]
 986 type=FUDesc
 987 children=opList0 opList1
 988 count=4
 989 eventq_index=0
 990 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 991
 992 [system.cpu1.fuPool.FUList7.opList0]
 993 type=OpDesc
 994 eventq_index=0
 995 opClass=MemRead
 996 opLat=1
 997 pipelined=true
 998
 999 [system.cpu1.fuPool.FUList7.opList1]
1000 type=OpDesc
1001 eventq_index=0
1002 opClass=MemWrite
1003 opLat=1
1004 pipelined=true
1005
1006 [system.cpu1.fuPool.FUList8]
1007 type=FUDesc
1008 children=opList
1009 count=1
1010 eventq_index=0
1011 opList=system.cpu1.fuPool.FUList8.opList
1012
1013 [system.cpu1.fuPool.FUList8.opList]
1014 type=OpDesc
1015 eventq_index=0
1016 opClass=IprAccess
1017 opLat=3
1018 pipelined=false
1019
1020 [system.cpu1.icache]
1021 type=BaseCache
1022 children=tags
1023 addr_ranges=0:18446744073709551615
1024 assoc=1
1025 clk_domain=system.cpu_clk_domain
1026 demand_mshr_reserve=1
1027 eventq_index=0
1028 forward_snoops=true
1029 hit_latency=2
1030 is_read_only=true
1031 max_miss_count=0
1032 mshrs=4
1033 prefetch_on_access=false
1034 prefetcher=Null
1035 response_latency=2
1036 sequential_access=false
1037 size=32768
1038 system=system
1039 tags=system.cpu1.icache.tags
1040 tgts_per_mshr=20
1041 write_buffers=8
1042 cpu_side=system.cpu1.icache_port
1043 mem_side=system.toL2Bus.slave[2]
1044
1045 [system.cpu1.icache.tags]
1046 type=LRU
1047 assoc=1
1048 block_size=64
1049 clk_domain=system.cpu_clk_domain
1050 eventq_index=0
1051 hit_latency=2
1052 sequential_access=false
1053 size=32768
1054
1055 [system.cpu1.interrupts]
1056 type=AlphaInterrupts
1057 eventq_index=0
1058
1059 [system.cpu1.isa]
1060 type=AlphaISA
1061 eventq_index=0
1062 system=system
1063
1064 [system.cpu1.itb]
1065 type=AlphaTLB
1066 eventq_index=0
1067 size=48
1068
1069 [system.cpu1.tracer]
1070 type=ExeTracer
1071 eventq_index=0
1072
1073 [system.cpu_clk_domain]
1074 type=SrcClockDomain
1075 clock=500
1076 domain_id=-1
1077 eventq_index=0
1078 init_perf_level=0
1079 voltage_domain=system.voltage_domain
1080
1081 [system.disk0]
1082 type=IdeDisk
1083 children=image
1084 delay=1000000
1085 driveID=master
1086 eventq_index=0
1087 image=system.disk0.image
1088
1089 [system.disk0.image]
1090 type=CowDiskImage
1091 children=child
1092 child=system.disk0.image.child
1093 eventq_index=0
1094 image_file=
1095 read_only=false
1096 table_size=65536
1097
1098 [system.disk0.image.child]
1099 type=RawDiskImage
1100 eventq_index=0
1101 image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
1102 read_only=true
1103
1104 [system.disk2]
1105 type=IdeDisk
1106 children=image
1107 delay=1000000
1108 driveID=master
1109 eventq_index=0
1110 image=system.disk2.image
1111
1112 [system.disk2.image]
1113 type=CowDiskImage
1114 children=child
1115 child=system.disk2.image.child
1116 eventq_index=0
1117 image_file=
1118 read_only=false
1119 table_size=65536
1120
1121 [system.disk2.image.child]
1122 type=RawDiskImage
1123 eventq_index=0
1124 image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
1125 read_only=true
1126
1127 [system.dvfs_handler]
1128 type=DVFSHandler
1129 domains=
1130 enable=false
1131 eventq_index=0
1132 sys_clk_domain=system.clk_domain
1133 transition_latency=100000000
1134
1135 [system.intrctrl]
1136 type=IntrControl
1137 eventq_index=0
1138 sys=system
1139
1140 [system.iobus]
1141 type=NoncoherentXBar
1142 clk_domain=system.clk_domain
1143 eventq_index=0
1144 forward_latency=1
1145 frontend_latency=2
1146 response_latency=2
1147 use_default_range=true
1148 width=16
1149 default=system.tsunami.pciconfig.pio
1150 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
1151 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
1152
1153 [system.iocache]
1154 type=BaseCache
1155 children=tags
1156 addr_ranges=0:134217727
1157 assoc=8
1158 clk_domain=system.clk_domain
1159 demand_mshr_reserve=1
1160 eventq_index=0
1161 forward_snoops=false
1162 hit_latency=50
1163 is_read_only=false
1164 max_miss_count=0
1165 mshrs=20
1166 prefetch_on_access=false
1167 prefetcher=Null
1168 response_latency=50
1169 sequential_access=false
1170 size=1024
1171 system=system
1172 tags=system.iocache.tags
1173 tgts_per_mshr=12
1174 write_buffers=8
1175 cpu_side=system.iobus.master[29]
1176 mem_side=system.membus.slave[2]
1177
1178 [system.iocache.tags]
1179 type=LRU
1180 assoc=8
1181 block_size=64
1182 clk_domain=system.clk_domain
1183 eventq_index=0
1184 hit_latency=50
1185 sequential_access=false
1186 size=1024
1187
1188 [system.l2c]
1189 type=BaseCache
1190 children=tags
1191 addr_ranges=0:18446744073709551615
1192 assoc=8
1193 clk_domain=system.cpu_clk_domain
1194 demand_mshr_reserve=1
1195 eventq_index=0
1196 forward_snoops=true
1197 hit_latency=20
1198 is_read_only=false
1199 max_miss_count=0
1200 mshrs=20
1201 prefetch_on_access=false
1202 prefetcher=Null
1203 response_latency=20
1204 sequential_access=false
1205 size=4194304
1206 system=system
1207 tags=system.l2c.tags
1208 tgts_per_mshr=12
1209 write_buffers=8
1210 cpu_side=system.toL2Bus.master[0]
1211 mem_side=system.membus.slave[1]
1212
1213 [system.l2c.tags]
1214 type=LRU
1215 assoc=8
1216 block_size=64
1217 clk_domain=system.cpu_clk_domain
1218 eventq_index=0
1219 hit_latency=20
1220 sequential_access=false
1221 size=4194304
1222
1223 [system.membus]
1224 type=CoherentXBar
1225 children=badaddr_responder
1226 clk_domain=system.clk_domain
1227 eventq_index=0
1228 forward_latency=4
1229 frontend_latency=3
1230 response_latency=2
1231 snoop_filter=Null
1232 snoop_response_latency=4
1233 system=system
1234 use_default_range=false
1235 width=16
1236 default=system.membus.badaddr_responder.pio
1237 master=system.bridge.slave system.physmem.port
1238 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1239
1240 [system.membus.badaddr_responder]
1241 type=IsaFake
1242 clk_domain=system.clk_domain
1243 eventq_index=0
1244 fake_mem=false
1245 pio_addr=0
1246 pio_latency=100000
1247 pio_size=8
1248 ret_bad_addr=true
1249 ret_data16=65535
1250 ret_data32=4294967295
1251 ret_data64=18446744073709551615
1252 ret_data8=255
1253 system=system
1254 update_data=false
1255 warn_access=
1256 pio=system.membus.default
1257
1258 [system.physmem]
1259 type=DRAMCtrl
1260 IDD0=0.075000
1261 IDD02=0.000000
1262 IDD2N=0.050000
1263 IDD2N2=0.000000
1264 IDD2P0=0.000000
1265 IDD2P02=0.000000
1266 IDD2P1=0.000000
1267 IDD2P12=0.000000
1268 IDD3N=0.057000
1269 IDD3N2=0.000000
1270 IDD3P0=0.000000
1271 IDD3P02=0.000000
1272 IDD3P1=0.000000
1273 IDD3P12=0.000000
1274 IDD4R=0.187000
1275 IDD4R2=0.000000
1276 IDD4W=0.165000
1277 IDD4W2=0.000000
1278 IDD5=0.220000
1279 IDD52=0.000000
1280 IDD6=0.000000
1281 IDD62=0.000000
1282 VDD=1.500000
1283 VDD2=0.000000
1284 activation_limit=4
1285 addr_mapping=RoRaBaCoCh
1286 bank_groups_per_rank=0
1287 banks_per_rank=8
1288 burst_length=8
1289 channels=1
1290 clk_domain=system.clk_domain
1291 conf_table_reported=true
1292 device_bus_width=8
1293 device_rowbuffer_size=1024
1294 device_size=536870912
1295 devices_per_rank=8
1296 dll=true
1297 eventq_index=0
1298 in_addr_map=true
1299 max_accesses_per_row=16
1300 mem_sched_policy=frfcfs
1301 min_writes_per_switch=16
1302 null=false
1303 page_policy=open_adaptive
1304 range=0:134217727
1305 ranks_per_channel=2
1306 read_buffer_size=32
1307 static_backend_latency=10000
1308 static_frontend_latency=10000
1309 tBURST=5000
1310 tCCD_L=0
1311 tCK=1250
1312 tCL=13750
1313 tCS=2500
1314 tRAS=35000
1315 tRCD=13750
1316 tREFI=7800000
1317 tRFC=260000
1318 tRP=13750
1319 tRRD=6000
1320 tRRD_L=0
1321 tRTP=7500
1322 tRTW=2500
1323 tWR=15000
1324 tWTR=7500
1325 tXAW=30000
1326 tXP=0
1327 tXPDLL=0
1328 tXS=0
1329 tXSDLL=0
1330 write_buffer_size=64
1331 write_high_thresh_perc=85
1332 write_low_thresh_perc=50
1333 port=system.membus.master[1]
1334
1335 [system.simple_disk]
1336 type=SimpleDisk
1337 children=disk
1338 disk=system.simple_disk.disk
1339 eventq_index=0
1340 system=system
1341
1342 [system.simple_disk.disk]
1343 type=RawDiskImage
1344 eventq_index=0
1345 image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
1346 read_only=true
1347
1348 [system.terminal]
1349 type=Terminal
1350 eventq_index=0
1351 intr_control=system.intrctrl
1352 number=0
1353 output=true
1354 port=3456
1355
1356 [system.toL2Bus]
1357 type=CoherentXBar
1358 clk_domain=system.cpu_clk_domain
1359 eventq_index=0
1360 forward_latency=0
1361 frontend_latency=1
1362 response_latency=1
1363 snoop_filter=Null
1364 snoop_response_latency=1
1365 system=system
1366 use_default_range=false
1367 width=32
1368 master=system.l2c.cpu_side
1369 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
1370
1371 [system.tsunami]
1372 type=Tsunami
1373 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1374 eventq_index=0
1375 intrctrl=system.intrctrl
1376 system=system
1377
1378 [system.tsunami.backdoor]
1379 type=AlphaBackdoor
1380 clk_domain=system.clk_domain
1381 cpu=system.cpu0
1382 disk=system.simple_disk
1383 eventq_index=0
1384 pio_addr=8804682956800
1385 pio_latency=100000
1386 platform=system.tsunami
1387 system=system
1388 terminal=system.terminal
1389 pio=system.iobus.master[24]
1390
1391 [system.tsunami.cchip]
1392 type=TsunamiCChip
1393 clk_domain=system.clk_domain
1394 eventq_index=0
1395 pio_addr=8803072344064
1396 pio_latency=100000
1397 system=system
1398 tsunami=system.tsunami
1399 pio=system.iobus.master[0]
1400
1401 [system.tsunami.ethernet]
1402 type=NSGigE
1403 BAR0=1
1404 BAR0LegacyIO=false
1405 BAR0Size=256
1406 BAR1=0
1407 BAR1LegacyIO=false
1408 BAR1Size=4096
1409 BAR2=0
1410 BAR2LegacyIO=false
1411 BAR2Size=0
1412 BAR3=0
1413 BAR3LegacyIO=false
1414 BAR3Size=0
1415 BAR4=0
1416 BAR4LegacyIO=false
1417 BAR4Size=0
1418 BAR5=0
1419 BAR5LegacyIO=false
1420 BAR5Size=0
1421 BIST=0
1422 CacheLineSize=0
1423 CapabilityPtr=0
1424 CardbusCIS=0
1425 ClassCode=2
1426 Command=0
1427 DeviceID=34
1428 ExpansionROM=0
1429 HeaderType=0
1430 InterruptLine=30
1431 InterruptPin=1
1432 LatencyTimer=0
1433 LegacyIOBase=0
1434 MSICAPBaseOffset=0
1435 MSICAPCapId=0
1436 MSICAPMaskBits=0
1437 MSICAPMsgAddr=0
1438 MSICAPMsgCtrl=0
1439 MSICAPMsgData=0
1440 MSICAPMsgUpperAddr=0
1441 MSICAPNextCapability=0
1442 MSICAPPendingBits=0
1443 MSIXCAPBaseOffset=0
1444 MSIXCAPCapId=0
1445 MSIXCAPNextCapability=0
1446 MSIXMsgCtrl=0
1447 MSIXPbaOffset=0
1448 MSIXTableOffset=0
1449 MaximumLatency=52
1450 MinimumGrant=176
1451 PMCAPBaseOffset=0
1452 PMCAPCapId=0
1453 PMCAPCapabilities=0
1454 PMCAPCtrlStatus=0
1455 PMCAPNextCapability=0
1456 PXCAPBaseOffset=0
1457 PXCAPCapId=0
1458 PXCAPCapabilities=0
1459 PXCAPDevCap2=0
1460 PXCAPDevCapabilities=0
1461 PXCAPDevCtrl=0
1462 PXCAPDevCtrl2=0
1463 PXCAPDevStatus=0
1464 PXCAPLinkCap=0
1465 PXCAPLinkCtrl=0
1466 PXCAPLinkStatus=0
1467 PXCAPNextCapability=0
1468 ProgIF=0
1469 Revision=0
1470 Status=656
1471 SubClassCode=0
1472 SubsystemID=0
1473 SubsystemVendorID=0
1474 VendorID=4107
1475 clk_domain=system.clk_domain
1476 config_latency=20000
1477 dma_data_free=false
1478 dma_desc_free=false
1479 dma_no_allocate=true
1480 dma_read_delay=0
1481 dma_read_factor=0
1482 dma_write_delay=0
1483 dma_write_factor=0
1484 eventq_index=0
1485 hardware_address=00:90:00:00:00:01
1486 intr_delay=10000000
1487 pci_bus=0
1488 pci_dev=1
1489 pci_func=0
1490 pio_latency=30000
1491 platform=system.tsunami
1492 rss=false
1493 rx_delay=1000000
1494 rx_fifo_size=524288
1495 rx_filter=true
1496 rx_thread=false
1497 system=system
1498 tx_delay=1000000
1499 tx_fifo_size=524288
1500 tx_thread=false
1501 config=system.iobus.master[28]
1502 dma=system.iobus.slave[2]
1503 pio=system.iobus.master[27]
1504
1505 [system.tsunami.fake_OROM]
1506 type=IsaFake
1507 clk_domain=system.clk_domain
1508 eventq_index=0
1509 fake_mem=false
1510 pio_addr=8796093677568
1511 pio_latency=100000
1512 pio_size=393216
1513 ret_bad_addr=false
1514 ret_data16=65535
1515 ret_data32=4294967295
1516 ret_data64=18446744073709551615
1517 ret_data8=255
1518 system=system
1519 update_data=false
1520 warn_access=
1521 pio=system.iobus.master[8]
1522
1523 [system.tsunami.fake_ata0]
1524 type=IsaFake
1525 clk_domain=system.clk_domain
1526 eventq_index=0
1527 fake_mem=false
1528 pio_addr=8804615848432
1529 pio_latency=100000
1530 pio_size=8
1531 ret_bad_addr=false
1532 ret_data16=65535
1533 ret_data32=4294967295
1534 ret_data64=18446744073709551615
1535 ret_data8=255
1536 system=system
1537 update_data=false
1538 warn_access=
1539 pio=system.iobus.master[19]
1540
1541 [system.tsunami.fake_ata1]
1542 type=IsaFake
1543 clk_domain=system.clk_domain
1544 eventq_index=0
1545 fake_mem=false
1546 pio_addr=8804615848304
1547 pio_latency=100000
1548 pio_size=8
1549 ret_bad_addr=false
1550 ret_data16=65535
1551 ret_data32=4294967295
1552 ret_data64=18446744073709551615
1553 ret_data8=255
1554 system=system
1555 update_data=false
1556 warn_access=
1557 pio=system.iobus.master[20]
1558
1559 [system.tsunami.fake_pnp_addr]
1560 type=IsaFake
1561 clk_domain=system.clk_domain
1562 eventq_index=0
1563 fake_mem=false
1564 pio_addr=8804615848569
1565 pio_latency=100000
1566 pio_size=8
1567 ret_bad_addr=false
1568 ret_data16=65535
1569 ret_data32=4294967295
1570 ret_data64=18446744073709551615
1571 ret_data8=255
1572 system=system
1573 update_data=false
1574 warn_access=
1575 pio=system.iobus.master[9]
1576
1577 [system.tsunami.fake_pnp_read0]
1578 type=IsaFake
1579 clk_domain=system.clk_domain
1580 eventq_index=0
1581 fake_mem=false
1582 pio_addr=8804615848451
1583 pio_latency=100000
1584 pio_size=8
1585 ret_bad_addr=false
1586 ret_data16=65535
1587 ret_data32=4294967295
1588 ret_data64=18446744073709551615
1589 ret_data8=255
1590 system=system
1591 update_data=false
1592 warn_access=
1593 pio=system.iobus.master[11]
1594
1595 [system.tsunami.fake_pnp_read1]
1596 type=IsaFake
1597 clk_domain=system.clk_domain
1598 eventq_index=0
1599 fake_mem=false
1600 pio_addr=8804615848515
1601 pio_latency=100000
1602 pio_size=8
1603 ret_bad_addr=false
1604 ret_data16=65535
1605 ret_data32=4294967295
1606 ret_data64=18446744073709551615
1607 ret_data8=255
1608 system=system
1609 update_data=false
1610 warn_access=
1611 pio=system.iobus.master[12]
1612
1613 [system.tsunami.fake_pnp_read2]
1614 type=IsaFake
1615 clk_domain=system.clk_domain
1616 eventq_index=0
1617 fake_mem=false
1618 pio_addr=8804615848579
1619 pio_latency=100000
1620 pio_size=8
1621 ret_bad_addr=false
1622 ret_data16=65535
1623 ret_data32=4294967295
1624 ret_data64=18446744073709551615
1625 ret_data8=255
1626 system=system
1627 update_data=false
1628 warn_access=
1629 pio=system.iobus.master[13]
1630
1631 [system.tsunami.fake_pnp_read3]
1632 type=IsaFake
1633 clk_domain=system.clk_domain
1634 eventq_index=0
1635 fake_mem=false
1636 pio_addr=8804615848643
1637 pio_latency=100000
1638 pio_size=8
1639 ret_bad_addr=false
1640 ret_data16=65535
1641 ret_data32=4294967295
1642 ret_data64=18446744073709551615
1643 ret_data8=255
1644 system=system
1645 update_data=false
1646 warn_access=
1647 pio=system.iobus.master[14]
1648
1649 [system.tsunami.fake_pnp_read4]
1650 type=IsaFake
1651 clk_domain=system.clk_domain
1652 eventq_index=0
1653 fake_mem=false
1654 pio_addr=8804615848707
1655 pio_latency=100000
1656 pio_size=8
1657 ret_bad_addr=false
1658 ret_data16=65535
1659 ret_data32=4294967295
1660 ret_data64=18446744073709551615
1661 ret_data8=255
1662 system=system
1663 update_data=false
1664 warn_access=
1665 pio=system.iobus.master[15]
1666
1667 [system.tsunami.fake_pnp_read5]
1668 type=IsaFake
1669 clk_domain=system.clk_domain
1670 eventq_index=0
1671 fake_mem=false
1672 pio_addr=8804615848771
1673 pio_latency=100000
1674 pio_size=8
1675 ret_bad_addr=false
1676 ret_data16=65535
1677 ret_data32=4294967295
1678 ret_data64=18446744073709551615
1679 ret_data8=255
1680 system=system
1681 update_data=false
1682 warn_access=
1683 pio=system.iobus.master[16]
1684
1685 [system.tsunami.fake_pnp_read6]
1686 type=IsaFake
1687 clk_domain=system.clk_domain
1688 eventq_index=0
1689 fake_mem=false
1690 pio_addr=8804615848835
1691 pio_latency=100000
1692 pio_size=8
1693 ret_bad_addr=false
1694 ret_data16=65535
1695 ret_data32=4294967295
1696 ret_data64=18446744073709551615
1697 ret_data8=255
1698 system=system
1699 update_data=false
1700 warn_access=
1701 pio=system.iobus.master[17]
1702
1703 [system.tsunami.fake_pnp_read7]
1704 type=IsaFake
1705 clk_domain=system.clk_domain
1706 eventq_index=0
1707 fake_mem=false
1708 pio_addr=8804615848899
1709 pio_latency=100000
1710 pio_size=8
1711 ret_bad_addr=false
1712 ret_data16=65535
1713 ret_data32=4294967295
1714 ret_data64=18446744073709551615
1715 ret_data8=255
1716 system=system
1717 update_data=false
1718 warn_access=
1719 pio=system.iobus.master[18]
1720
1721 [system.tsunami.fake_pnp_write]
1722 type=IsaFake
1723 clk_domain=system.clk_domain
1724 eventq_index=0
1725 fake_mem=false
1726 pio_addr=8804615850617
1727 pio_latency=100000
1728 pio_size=8
1729 ret_bad_addr=false
1730 ret_data16=65535
1731 ret_data32=4294967295
1732 ret_data64=18446744073709551615
1733 ret_data8=255
1734 system=system
1735 update_data=false
1736 warn_access=
1737 pio=system.iobus.master[10]
1738
1739 [system.tsunami.fake_ppc]
1740 type=IsaFake
1741 clk_domain=system.clk_domain
1742 eventq_index=0
1743 fake_mem=false
1744 pio_addr=8804615848891
1745 pio_latency=100000
1746 pio_size=8
1747 ret_bad_addr=false
1748 ret_data16=65535
1749 ret_data32=4294967295
1750 ret_data64=18446744073709551615
1751 ret_data8=255
1752 system=system
1753 update_data=false
1754 warn_access=
1755 pio=system.iobus.master[7]
1756
1757 [system.tsunami.fake_sm_chip]
1758 type=IsaFake
1759 clk_domain=system.clk_domain
1760 eventq_index=0
1761 fake_mem=false
1762 pio_addr=8804615848816
1763 pio_latency=100000
1764 pio_size=8
1765 ret_bad_addr=false
1766 ret_data16=65535
1767 ret_data32=4294967295
1768 ret_data64=18446744073709551615
1769 ret_data8=255
1770 system=system
1771 update_data=false
1772 warn_access=
1773 pio=system.iobus.master[2]
1774
1775 [system.tsunami.fake_uart1]
1776 type=IsaFake
1777 clk_domain=system.clk_domain
1778 eventq_index=0
1779 fake_mem=false
1780 pio_addr=8804615848696
1781 pio_latency=100000
1782 pio_size=8
1783 ret_bad_addr=false
1784 ret_data16=65535
1785 ret_data32=4294967295
1786 ret_data64=18446744073709551615
1787 ret_data8=255
1788 system=system
1789 update_data=false
1790 warn_access=
1791 pio=system.iobus.master[3]
1792
1793 [system.tsunami.fake_uart2]
1794 type=IsaFake
1795 clk_domain=system.clk_domain
1796 eventq_index=0
1797 fake_mem=false
1798 pio_addr=8804615848936
1799 pio_latency=100000
1800 pio_size=8
1801 ret_bad_addr=false
1802 ret_data16=65535
1803 ret_data32=4294967295
1804 ret_data64=18446744073709551615
1805 ret_data8=255
1806 system=system
1807 update_data=false
1808 warn_access=
1809 pio=system.iobus.master[4]
1810
1811 [system.tsunami.fake_uart3]
1812 type=IsaFake
1813 clk_domain=system.clk_domain
1814 eventq_index=0
1815 fake_mem=false
1816 pio_addr=8804615848680
1817 pio_latency=100000
1818 pio_size=8
1819 ret_bad_addr=false
1820 ret_data16=65535
1821 ret_data32=4294967295
1822 ret_data64=18446744073709551615
1823 ret_data8=255
1824 system=system
1825 update_data=false
1826 warn_access=
1827 pio=system.iobus.master[5]
1828
1829 [system.tsunami.fake_uart4]
1830 type=IsaFake
1831 clk_domain=system.clk_domain
1832 eventq_index=0
1833 fake_mem=false
1834 pio_addr=8804615848944
1835 pio_latency=100000
1836 pio_size=8
1837 ret_bad_addr=false
1838 ret_data16=65535
1839 ret_data32=4294967295
1840 ret_data64=18446744073709551615
1841 ret_data8=255
1842 system=system
1843 update_data=false
1844 warn_access=
1845 pio=system.iobus.master[6]
1846
1847 [system.tsunami.fb]
1848 type=BadDevice
1849 clk_domain=system.clk_domain
1850 devicename=FrameBuffer
1851 eventq_index=0
1852 pio_addr=8804615848912
1853 pio_latency=100000
1854 system=system
1855 pio=system.iobus.master[21]
1856
1857 [system.tsunami.ide]
1858 type=IdeController
1859 BAR0=1
1860 BAR0LegacyIO=false
1861 BAR0Size=8
1862 BAR1=1
1863 BAR1LegacyIO=false
1864 BAR1Size=4
1865 BAR2=1
1866 BAR2LegacyIO=false
1867 BAR2Size=8
1868 BAR3=1
1869 BAR3LegacyIO=false
1870 BAR3Size=4
1871 BAR4=1
1872 BAR4LegacyIO=false
1873 BAR4Size=16
1874 BAR5=1
1875 BAR5LegacyIO=false
1876 BAR5Size=0
1877 BIST=0
1878 CacheLineSize=0
1879 CapabilityPtr=0
1880 CardbusCIS=0
1881 ClassCode=1
1882 Command=0
1883 DeviceID=28945
1884 ExpansionROM=0
1885 HeaderType=0
1886 InterruptLine=31
1887 InterruptPin=1
1888 LatencyTimer=0
1889 LegacyIOBase=0
1890 MSICAPBaseOffset=0
1891 MSICAPCapId=0
1892 MSICAPMaskBits=0
1893 MSICAPMsgAddr=0
1894 MSICAPMsgCtrl=0
1895 MSICAPMsgData=0
1896 MSICAPMsgUpperAddr=0
1897 MSICAPNextCapability=0
1898 MSICAPPendingBits=0
1899 MSIXCAPBaseOffset=0
1900 MSIXCAPCapId=0
1901 MSIXCAPNextCapability=0
1902 MSIXMsgCtrl=0
1903 MSIXPbaOffset=0
1904 MSIXTableOffset=0
1905 MaximumLatency=0
1906 MinimumGrant=0
1907 PMCAPBaseOffset=0
1908 PMCAPCapId=0
1909 PMCAPCapabilities=0
1910 PMCAPCtrlStatus=0
1911 PMCAPNextCapability=0
1912 PXCAPBaseOffset=0
1913 PXCAPCapId=0
1914 PXCAPCapabilities=0
1915 PXCAPDevCap2=0
1916 PXCAPDevCapabilities=0
1917 PXCAPDevCtrl=0
1918 PXCAPDevCtrl2=0
1919 PXCAPDevStatus=0
1920 PXCAPLinkCap=0
1921 PXCAPLinkCtrl=0
1922 PXCAPLinkStatus=0
1923 PXCAPNextCapability=0
1924 ProgIF=133
1925 Revision=0
1926 Status=640
1927 SubClassCode=1
1928 SubsystemID=0
1929 SubsystemVendorID=0
1930 VendorID=32902
1931 clk_domain=system.clk_domain
1932 config_latency=20000
1933 ctrl_offset=0
1934 disks=system.disk0 system.disk2
1935 eventq_index=0
1936 io_shift=0
1937 pci_bus=0
1938 pci_dev=0
1939 pci_func=0
1940 pio_latency=30000
1941 platform=system.tsunami
1942 system=system
1943 config=system.iobus.master[26]
1944 dma=system.iobus.slave[1]
1945 pio=system.iobus.master[25]
1946
1947 [system.tsunami.io]
1948 type=TsunamiIO
1949 clk_domain=system.clk_domain
1950 eventq_index=0
1951 frequency=976562500
1952 pio_addr=8804615847936
1953 pio_latency=100000
1954 system=system
1955 time=Thu Jan  1 00:00:00 2009
1956 tsunami=system.tsunami
1957 year_is_bcd=false
1958 pio=system.iobus.master[22]
1959
1960 [system.tsunami.pchip]
1961 type=TsunamiPChip
1962 clk_domain=system.clk_domain
1963 eventq_index=0
1964 pio_addr=8802535473152
1965 pio_latency=100000
1966 system=system
1967 tsunami=system.tsunami
1968 pio=system.iobus.master[1]
1969
1970 [system.tsunami.pciconfig]
1971 type=PciConfigAll
1972 bus=0
1973 clk_domain=system.clk_domain
1974 eventq_index=0
1975 pio_addr=0
1976 pio_latency=30000
1977 platform=system.tsunami
1978 size=16777216
1979 system=system
1980 pio=system.iobus.default
1981
1982 [system.tsunami.uart]
1983 type=Uart8250
1984 clk_domain=system.clk_domain
1985 eventq_index=0
1986 pio_addr=8804615848952
1987 pio_latency=100000
1988 platform=system.tsunami
1989 system=system
1990 terminal=system.terminal
1991 pio=system.iobus.master[23]
1992
1993 [system.voltage_domain]
1994 type=VoltageDomain
1995 eventq_index=0
1996 voltage=1.000000
1997