tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxAlphaSystem
  13 children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
  14 boot_cpu_frequency=500
  15 boot_osflags=root=/dev/hda1 console=ttyS0
  16 cache_line_size=64
  17 clk_domain=system.clk_domain
  18 console=/scratch/nilay/GEM5/system/binaries/console
  19 eventq_index=0
  20 init_param=0
  21 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.physmem
  28 num_work_ids=16
  29 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
  30 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  31 symbolfile=
  32 system_rev=1024
  33 system_type=34
  34 work_begin_ckpt_count=0
  35 work_begin_cpu_id_exit=-1
  36 work_begin_exit_count=0
  37 work_cpus_ckpt_count=0
  38 work_end_ckpt_count=0
  39 work_end_exit_count=0
  40 work_item_id=-1
  41 system_port=system.membus.slave[0]
  42
  43 [system.bridge]
  44 type=Bridge
  45 clk_domain=system.clk_domain
  46 delay=50000
  47 eventq_index=0
  48 ranges=8796093022208:18446744073709551615
  49 req_size=16
  50 resp_size=16
  51 master=system.iobus.slave[0]
  52 slave=system.membus.master[0]
  53
  54 [system.clk_domain]
  55 type=SrcClockDomain
  56 clock=1000
  57 domain_id=-1
  58 eventq_index=0
  59 init_perf_level=0
  60 voltage_domain=system.voltage_domain
  61
  62 [system.cpu0]
  63 type=DerivO3CPU
  64 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
  65 LFSTSize=1024
  66 LQEntries=32
  67 LSQCheckLoads=true
  68 LSQDepCheckShift=4
  69 SQEntries=32
  70 SSITSize=1024
  71 activity=0
  72 backComSize=5
  73 branchPred=system.cpu0.branchPred
  74 cachePorts=200
  75 checker=Null
  76 clk_domain=system.cpu_clk_domain
  77 commitToDecodeDelay=1
  78 commitToFetchDelay=1
  79 commitToIEWDelay=1
  80 commitToRenameDelay=1
  81 commitWidth=8
  82 cpu_id=0
  83 decodeToFetchDelay=1
  84 decodeToRenameDelay=1
  85 decodeWidth=8
  86 dispatchWidth=8
  87 do_checkpoint_insts=true
  88 do_quiesce=true
  89 do_statistics_insts=true
  90 dtb=system.cpu0.dtb
  91 eventq_index=0
  92 fetchBufferSize=64
  93 fetchQueueSize=32
  94 fetchToDecodeDelay=1
  95 fetchTrapLatency=1
  96 fetchWidth=8
  97 forwardComSize=5
  98 fuPool=system.cpu0.fuPool
  99 function_trace=false
 100 function_trace_start=0
 101 iewToCommitDelay=1
 102 iewToDecodeDelay=1
 103 iewToFetchDelay=1
 104 iewToRenameDelay=1
 105 interrupts=system.cpu0.interrupts
 106 isa=system.cpu0.isa
 107 issueToExecuteDelay=1
 108 issueWidth=8
 109 itb=system.cpu0.itb
 110 max_insts_all_threads=0
 111 max_insts_any_thread=0
 112 max_loads_all_threads=0
 113 max_loads_any_thread=0
 114 needsTSO=false
 115 numIQEntries=64
 116 numPhysCCRegs=0
 117 numPhysFloatRegs=256
 118 numPhysIntRegs=256
 119 numROBEntries=192
 120 numRobs=1
 121 numThreads=1
 122 profile=0
 123 progress_interval=0
 124 renameToDecodeDelay=1
 125 renameToFetchDelay=1
 126 renameToIEWDelay=2
 127 renameToROBDelay=1
 128 renameWidth=8
 129 simpoint_start_insts=
 130 smtCommitPolicy=RoundRobin
 131 smtFetchPolicy=SingleThread
 132 smtIQPolicy=Partitioned
 133 smtIQThreshold=100
 134 smtLSQPolicy=Partitioned
 135 smtLSQThreshold=100
 136 smtNumFetchingThreads=1
 137 smtROBPolicy=Partitioned
 138 smtROBThreshold=100
 139 socket_id=0
 140 squashWidth=8
 141 store_set_clear_period=250000
 142 switched_out=false
 143 system=system
 144 tracer=system.cpu0.tracer
 145 trapLatency=13
 146 wbWidth=8
 147 workload=
 148 dcache_port=system.cpu0.dcache.cpu_side
 149 icache_port=system.cpu0.icache.cpu_side
 150
 151 [system.cpu0.branchPred]
 152 type=BranchPredictor
 153 BTBEntries=4096
 154 BTBTagSize=16
 155 RASSize=16
 156 choiceCtrBits=2
 157 choicePredictorSize=8192
 158 eventq_index=0
 159 globalCtrBits=2
 160 globalPredictorSize=8192
 161 instShiftAmt=2
 162 localCtrBits=2
 163 localHistoryTableSize=2048
 164 localPredictorSize=2048
 165 numThreads=1
 166 predType=tournament
 167
 168 [system.cpu0.dcache]
 169 type=BaseCache
 170 children=tags
 171 addr_ranges=0:18446744073709551615
 172 assoc=4
 173 clk_domain=system.cpu_clk_domain
 174 eventq_index=0
 175 forward_snoops=true
 176 hit_latency=2
 177 is_top_level=true
 178 max_miss_count=0
 179 mshrs=4
 180 prefetch_on_access=false
 181 prefetcher=Null
 182 response_latency=2
 183 sequential_access=false
 184 size=32768
 185 system=system
 186 tags=system.cpu0.dcache.tags
 187 tgts_per_mshr=20
 188 two_queue=false
 189 write_buffers=8
 190 cpu_side=system.cpu0.dcache_port
 191 mem_side=system.toL2Bus.slave[1]
 192
 193 [system.cpu0.dcache.tags]
 194 type=LRU
 195 assoc=4
 196 block_size=64
 197 clk_domain=system.cpu_clk_domain
 198 eventq_index=0
 199 hit_latency=2
 200 sequential_access=false
 201 size=32768
 202
 203 [system.cpu0.dtb]
 204 type=AlphaTLB
 205 eventq_index=0
 206 size=64
 207
 208 [system.cpu0.fuPool]
 209 type=FUPool
 210 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 211 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 212 eventq_index=0
 213
 214 [system.cpu0.fuPool.FUList0]
 215 type=FUDesc
 216 children=opList
 217 count=6
 218 eventq_index=0
 219 opList=system.cpu0.fuPool.FUList0.opList
 220
 221 [system.cpu0.fuPool.FUList0.opList]
 222 type=OpDesc
 223 eventq_index=0
 224 issueLat=1
 225 opClass=IntAlu
 226 opLat=1
 227
 228 [system.cpu0.fuPool.FUList1]
 229 type=FUDesc
 230 children=opList0 opList1
 231 count=2
 232 eventq_index=0
 233 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 234
 235 [system.cpu0.fuPool.FUList1.opList0]
 236 type=OpDesc
 237 eventq_index=0
 238 issueLat=1
 239 opClass=IntMult
 240 opLat=3
 241
 242 [system.cpu0.fuPool.FUList1.opList1]
 243 type=OpDesc
 244 eventq_index=0
 245 issueLat=19
 246 opClass=IntDiv
 247 opLat=20
 248
 249 [system.cpu0.fuPool.FUList2]
 250 type=FUDesc
 251 children=opList0 opList1 opList2
 252 count=4
 253 eventq_index=0
 254 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 255
 256 [system.cpu0.fuPool.FUList2.opList0]
 257 type=OpDesc
 258 eventq_index=0
 259 issueLat=1
 260 opClass=FloatAdd
 261 opLat=2
 262
 263 [system.cpu0.fuPool.FUList2.opList1]
 264 type=OpDesc
 265 eventq_index=0
 266 issueLat=1
 267 opClass=FloatCmp
 268 opLat=2
 269
 270 [system.cpu0.fuPool.FUList2.opList2]
 271 type=OpDesc
 272 eventq_index=0
 273 issueLat=1
 274 opClass=FloatCvt
 275 opLat=2
 276
 277 [system.cpu0.fuPool.FUList3]
 278 type=FUDesc
 279 children=opList0 opList1 opList2
 280 count=2
 281 eventq_index=0
 282 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 283
 284 [system.cpu0.fuPool.FUList3.opList0]
 285 type=OpDesc
 286 eventq_index=0
 287 issueLat=1
 288 opClass=FloatMult
 289 opLat=4
 290
 291 [system.cpu0.fuPool.FUList3.opList1]
 292 type=OpDesc
 293 eventq_index=0
 294 issueLat=12
 295 opClass=FloatDiv
 296 opLat=12
 297
 298 [system.cpu0.fuPool.FUList3.opList2]
 299 type=OpDesc
 300 eventq_index=0
 301 issueLat=24
 302 opClass=FloatSqrt
 303 opLat=24
 304
 305 [system.cpu0.fuPool.FUList4]
 306 type=FUDesc
 307 children=opList
 308 count=0
 309 eventq_index=0
 310 opList=system.cpu0.fuPool.FUList4.opList
 311
 312 [system.cpu0.fuPool.FUList4.opList]
 313 type=OpDesc
 314 eventq_index=0
 315 issueLat=1
 316 opClass=MemRead
 317 opLat=1
 318
 319 [system.cpu0.fuPool.FUList5]
 320 type=FUDesc
 321 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 322 count=4
 323 eventq_index=0
 324 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 325
 326 [system.cpu0.fuPool.FUList5.opList00]
 327 type=OpDesc
 328 eventq_index=0
 329 issueLat=1
 330 opClass=SimdAdd
 331 opLat=1
 332
 333 [system.cpu0.fuPool.FUList5.opList01]
 334 type=OpDesc
 335 eventq_index=0
 336 issueLat=1
 337 opClass=SimdAddAcc
 338 opLat=1
 339
 340 [system.cpu0.fuPool.FUList5.opList02]
 341 type=OpDesc
 342 eventq_index=0
 343 issueLat=1
 344 opClass=SimdAlu
 345 opLat=1
 346
 347 [system.cpu0.fuPool.FUList5.opList03]
 348 type=OpDesc
 349 eventq_index=0
 350 issueLat=1
 351 opClass=SimdCmp
 352 opLat=1
 353
 354 [system.cpu0.fuPool.FUList5.opList04]
 355 type=OpDesc
 356 eventq_index=0
 357 issueLat=1
 358 opClass=SimdCvt
 359 opLat=1
 360
 361 [system.cpu0.fuPool.FUList5.opList05]
 362 type=OpDesc
 363 eventq_index=0
 364 issueLat=1
 365 opClass=SimdMisc
 366 opLat=1
 367
 368 [system.cpu0.fuPool.FUList5.opList06]
 369 type=OpDesc
 370 eventq_index=0
 371 issueLat=1
 372 opClass=SimdMult
 373 opLat=1
 374
 375 [system.cpu0.fuPool.FUList5.opList07]
 376 type=OpDesc
 377 eventq_index=0
 378 issueLat=1
 379 opClass=SimdMultAcc
 380 opLat=1
 381
 382 [system.cpu0.fuPool.FUList5.opList08]
 383 type=OpDesc
 384 eventq_index=0
 385 issueLat=1
 386 opClass=SimdShift
 387 opLat=1
 388
 389 [system.cpu0.fuPool.FUList5.opList09]
 390 type=OpDesc
 391 eventq_index=0
 392 issueLat=1
 393 opClass=SimdShiftAcc
 394 opLat=1
 395
 396 [system.cpu0.fuPool.FUList5.opList10]
 397 type=OpDesc
 398 eventq_index=0
 399 issueLat=1
 400 opClass=SimdSqrt
 401 opLat=1
 402
 403 [system.cpu0.fuPool.FUList5.opList11]
 404 type=OpDesc
 405 eventq_index=0
 406 issueLat=1
 407 opClass=SimdFloatAdd
 408 opLat=1
 409
 410 [system.cpu0.fuPool.FUList5.opList12]
 411 type=OpDesc
 412 eventq_index=0
 413 issueLat=1
 414 opClass=SimdFloatAlu
 415 opLat=1
 416
 417 [system.cpu0.fuPool.FUList5.opList13]
 418 type=OpDesc
 419 eventq_index=0
 420 issueLat=1
 421 opClass=SimdFloatCmp
 422 opLat=1
 423
 424 [system.cpu0.fuPool.FUList5.opList14]
 425 type=OpDesc
 426 eventq_index=0
 427 issueLat=1
 428 opClass=SimdFloatCvt
 429 opLat=1
 430
 431 [system.cpu0.fuPool.FUList5.opList15]
 432 type=OpDesc
 433 eventq_index=0
 434 issueLat=1
 435 opClass=SimdFloatDiv
 436 opLat=1
 437
 438 [system.cpu0.fuPool.FUList5.opList16]
 439 type=OpDesc
 440 eventq_index=0
 441 issueLat=1
 442 opClass=SimdFloatMisc
 443 opLat=1
 444
 445 [system.cpu0.fuPool.FUList5.opList17]
 446 type=OpDesc
 447 eventq_index=0
 448 issueLat=1
 449 opClass=SimdFloatMult
 450 opLat=1
 451
 452 [system.cpu0.fuPool.FUList5.opList18]
 453 type=OpDesc
 454 eventq_index=0
 455 issueLat=1
 456 opClass=SimdFloatMultAcc
 457 opLat=1
 458
 459 [system.cpu0.fuPool.FUList5.opList19]
 460 type=OpDesc
 461 eventq_index=0
 462 issueLat=1
 463 opClass=SimdFloatSqrt
 464 opLat=1
 465
 466 [system.cpu0.fuPool.FUList6]
 467 type=FUDesc
 468 children=opList
 469 count=0
 470 eventq_index=0
 471 opList=system.cpu0.fuPool.FUList6.opList
 472
 473 [system.cpu0.fuPool.FUList6.opList]
 474 type=OpDesc
 475 eventq_index=0
 476 issueLat=1
 477 opClass=MemWrite
 478 opLat=1
 479
 480 [system.cpu0.fuPool.FUList7]
 481 type=FUDesc
 482 children=opList0 opList1
 483 count=4
 484 eventq_index=0
 485 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 486
 487 [system.cpu0.fuPool.FUList7.opList0]
 488 type=OpDesc
 489 eventq_index=0
 490 issueLat=1
 491 opClass=MemRead
 492 opLat=1
 493
 494 [system.cpu0.fuPool.FUList7.opList1]
 495 type=OpDesc
 496 eventq_index=0
 497 issueLat=1
 498 opClass=MemWrite
 499 opLat=1
 500
 501 [system.cpu0.fuPool.FUList8]
 502 type=FUDesc
 503 children=opList
 504 count=1
 505 eventq_index=0
 506 opList=system.cpu0.fuPool.FUList8.opList
 507
 508 [system.cpu0.fuPool.FUList8.opList]
 509 type=OpDesc
 510 eventq_index=0
 511 issueLat=3
 512 opClass=IprAccess
 513 opLat=3
 514
 515 [system.cpu0.icache]
 516 type=BaseCache
 517 children=tags
 518 addr_ranges=0:18446744073709551615
 519 assoc=1
 520 clk_domain=system.cpu_clk_domain
 521 eventq_index=0
 522 forward_snoops=true
 523 hit_latency=2
 524 is_top_level=true
 525 max_miss_count=0
 526 mshrs=4
 527 prefetch_on_access=false
 528 prefetcher=Null
 529 response_latency=2
 530 sequential_access=false
 531 size=32768
 532 system=system
 533 tags=system.cpu0.icache.tags
 534 tgts_per_mshr=20
 535 two_queue=false
 536 write_buffers=8
 537 cpu_side=system.cpu0.icache_port
 538 mem_side=system.toL2Bus.slave[0]
 539
 540 [system.cpu0.icache.tags]
 541 type=LRU
 542 assoc=1
 543 block_size=64
 544 clk_domain=system.cpu_clk_domain
 545 eventq_index=0
 546 hit_latency=2
 547 sequential_access=false
 548 size=32768
 549
 550 [system.cpu0.interrupts]
 551 type=AlphaInterrupts
 552 eventq_index=0
 553
 554 [system.cpu0.isa]
 555 type=AlphaISA
 556 eventq_index=0
 557 system=system
 558
 559 [system.cpu0.itb]
 560 type=AlphaTLB
 561 eventq_index=0
 562 size=48
 563
 564 [system.cpu0.tracer]
 565 type=ExeTracer
 566 eventq_index=0
 567
 568 [system.cpu1]
 569 type=DerivO3CPU
 570 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
 571 LFSTSize=1024
 572 LQEntries=32
 573 LSQCheckLoads=true
 574 LSQDepCheckShift=4
 575 SQEntries=32
 576 SSITSize=1024
 577 activity=0
 578 backComSize=5
 579 branchPred=system.cpu1.branchPred
 580 cachePorts=200
 581 checker=Null
 582 clk_domain=system.cpu_clk_domain
 583 commitToDecodeDelay=1
 584 commitToFetchDelay=1
 585 commitToIEWDelay=1
 586 commitToRenameDelay=1
 587 commitWidth=8
 588 cpu_id=1
 589 decodeToFetchDelay=1
 590 decodeToRenameDelay=1
 591 decodeWidth=8
 592 dispatchWidth=8
 593 do_checkpoint_insts=true
 594 do_quiesce=true
 595 do_statistics_insts=true
 596 dtb=system.cpu1.dtb
 597 eventq_index=0
 598 fetchBufferSize=64
 599 fetchQueueSize=32
 600 fetchToDecodeDelay=1
 601 fetchTrapLatency=1
 602 fetchWidth=8
 603 forwardComSize=5
 604 fuPool=system.cpu1.fuPool
 605 function_trace=false
 606 function_trace_start=0
 607 iewToCommitDelay=1
 608 iewToDecodeDelay=1
 609 iewToFetchDelay=1
 610 iewToRenameDelay=1
 611 interrupts=system.cpu1.interrupts
 612 isa=system.cpu1.isa
 613 issueToExecuteDelay=1
 614 issueWidth=8
 615 itb=system.cpu1.itb
 616 max_insts_all_threads=0
 617 max_insts_any_thread=0
 618 max_loads_all_threads=0
 619 max_loads_any_thread=0
 620 needsTSO=false
 621 numIQEntries=64
 622 numPhysCCRegs=0
 623 numPhysFloatRegs=256
 624 numPhysIntRegs=256
 625 numROBEntries=192
 626 numRobs=1
 627 numThreads=1
 628 profile=0
 629 progress_interval=0
 630 renameToDecodeDelay=1
 631 renameToFetchDelay=1
 632 renameToIEWDelay=2
 633 renameToROBDelay=1
 634 renameWidth=8
 635 simpoint_start_insts=
 636 smtCommitPolicy=RoundRobin
 637 smtFetchPolicy=SingleThread
 638 smtIQPolicy=Partitioned
 639 smtIQThreshold=100
 640 smtLSQPolicy=Partitioned
 641 smtLSQThreshold=100
 642 smtNumFetchingThreads=1
 643 smtROBPolicy=Partitioned
 644 smtROBThreshold=100
 645 socket_id=0
 646 squashWidth=8
 647 store_set_clear_period=250000
 648 switched_out=false
 649 system=system
 650 tracer=system.cpu1.tracer
 651 trapLatency=13
 652 wbWidth=8
 653 workload=
 654 dcache_port=system.cpu1.dcache.cpu_side
 655 icache_port=system.cpu1.icache.cpu_side
 656
 657 [system.cpu1.branchPred]
 658 type=BranchPredictor
 659 BTBEntries=4096
 660 BTBTagSize=16
 661 RASSize=16
 662 choiceCtrBits=2
 663 choicePredictorSize=8192
 664 eventq_index=0
 665 globalCtrBits=2
 666 globalPredictorSize=8192
 667 instShiftAmt=2
 668 localCtrBits=2
 669 localHistoryTableSize=2048
 670 localPredictorSize=2048
 671 numThreads=1
 672 predType=tournament
 673
 674 [system.cpu1.dcache]
 675 type=BaseCache
 676 children=tags
 677 addr_ranges=0:18446744073709551615
 678 assoc=4
 679 clk_domain=system.cpu_clk_domain
 680 eventq_index=0
 681 forward_snoops=true
 682 hit_latency=2
 683 is_top_level=true
 684 max_miss_count=0
 685 mshrs=4
 686 prefetch_on_access=false
 687 prefetcher=Null
 688 response_latency=2
 689 sequential_access=false
 690 size=32768
 691 system=system
 692 tags=system.cpu1.dcache.tags
 693 tgts_per_mshr=20
 694 two_queue=false
 695 write_buffers=8
 696 cpu_side=system.cpu1.dcache_port
 697 mem_side=system.toL2Bus.slave[3]
 698
 699 [system.cpu1.dcache.tags]
 700 type=LRU
 701 assoc=4
 702 block_size=64
 703 clk_domain=system.cpu_clk_domain
 704 eventq_index=0
 705 hit_latency=2
 706 sequential_access=false
 707 size=32768
 708
 709 [system.cpu1.dtb]
 710 type=AlphaTLB
 711 eventq_index=0
 712 size=64
 713
 714 [system.cpu1.fuPool]
 715 type=FUPool
 716 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 717 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 718 eventq_index=0
 719
 720 [system.cpu1.fuPool.FUList0]
 721 type=FUDesc
 722 children=opList
 723 count=6
 724 eventq_index=0
 725 opList=system.cpu1.fuPool.FUList0.opList
 726
 727 [system.cpu1.fuPool.FUList0.opList]
 728 type=OpDesc
 729 eventq_index=0
 730 issueLat=1
 731 opClass=IntAlu
 732 opLat=1
 733
 734 [system.cpu1.fuPool.FUList1]
 735 type=FUDesc
 736 children=opList0 opList1
 737 count=2
 738 eventq_index=0
 739 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 740
 741 [system.cpu1.fuPool.FUList1.opList0]
 742 type=OpDesc
 743 eventq_index=0
 744 issueLat=1
 745 opClass=IntMult
 746 opLat=3
 747
 748 [system.cpu1.fuPool.FUList1.opList1]
 749 type=OpDesc
 750 eventq_index=0
 751 issueLat=19
 752 opClass=IntDiv
 753 opLat=20
 754
 755 [system.cpu1.fuPool.FUList2]
 756 type=FUDesc
 757 children=opList0 opList1 opList2
 758 count=4
 759 eventq_index=0
 760 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 761
 762 [system.cpu1.fuPool.FUList2.opList0]
 763 type=OpDesc
 764 eventq_index=0
 765 issueLat=1
 766 opClass=FloatAdd
 767 opLat=2
 768
 769 [system.cpu1.fuPool.FUList2.opList1]
 770 type=OpDesc
 771 eventq_index=0
 772 issueLat=1
 773 opClass=FloatCmp
 774 opLat=2
 775
 776 [system.cpu1.fuPool.FUList2.opList2]
 777 type=OpDesc
 778 eventq_index=0
 779 issueLat=1
 780 opClass=FloatCvt
 781 opLat=2
 782
 783 [system.cpu1.fuPool.FUList3]
 784 type=FUDesc
 785 children=opList0 opList1 opList2
 786 count=2
 787 eventq_index=0
 788 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 789
 790 [system.cpu1.fuPool.FUList3.opList0]
 791 type=OpDesc
 792 eventq_index=0
 793 issueLat=1
 794 opClass=FloatMult
 795 opLat=4
 796
 797 [system.cpu1.fuPool.FUList3.opList1]
 798 type=OpDesc
 799 eventq_index=0
 800 issueLat=12
 801 opClass=FloatDiv
 802 opLat=12
 803
 804 [system.cpu1.fuPool.FUList3.opList2]
 805 type=OpDesc
 806 eventq_index=0
 807 issueLat=24
 808 opClass=FloatSqrt
 809 opLat=24
 810
 811 [system.cpu1.fuPool.FUList4]
 812 type=FUDesc
 813 children=opList
 814 count=0
 815 eventq_index=0
 816 opList=system.cpu1.fuPool.FUList4.opList
 817
 818 [system.cpu1.fuPool.FUList4.opList]
 819 type=OpDesc
 820 eventq_index=0
 821 issueLat=1
 822 opClass=MemRead
 823 opLat=1
 824
 825 [system.cpu1.fuPool.FUList5]
 826 type=FUDesc
 827 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 828 count=4
 829 eventq_index=0
 830 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 831
 832 [system.cpu1.fuPool.FUList5.opList00]
 833 type=OpDesc
 834 eventq_index=0
 835 issueLat=1
 836 opClass=SimdAdd
 837 opLat=1
 838
 839 [system.cpu1.fuPool.FUList5.opList01]
 840 type=OpDesc
 841 eventq_index=0
 842 issueLat=1
 843 opClass=SimdAddAcc
 844 opLat=1
 845
 846 [system.cpu1.fuPool.FUList5.opList02]
 847 type=OpDesc
 848 eventq_index=0
 849 issueLat=1
 850 opClass=SimdAlu
 851 opLat=1
 852
 853 [system.cpu1.fuPool.FUList5.opList03]
 854 type=OpDesc
 855 eventq_index=0
 856 issueLat=1
 857 opClass=SimdCmp
 858 opLat=1
 859
 860 [system.cpu1.fuPool.FUList5.opList04]
 861 type=OpDesc
 862 eventq_index=0
 863 issueLat=1
 864 opClass=SimdCvt
 865 opLat=1
 866
 867 [system.cpu1.fuPool.FUList5.opList05]
 868 type=OpDesc
 869 eventq_index=0
 870 issueLat=1
 871 opClass=SimdMisc
 872 opLat=1
 873
 874 [system.cpu1.fuPool.FUList5.opList06]
 875 type=OpDesc
 876 eventq_index=0
 877 issueLat=1
 878 opClass=SimdMult
 879 opLat=1
 880
 881 [system.cpu1.fuPool.FUList5.opList07]
 882 type=OpDesc
 883 eventq_index=0
 884 issueLat=1
 885 opClass=SimdMultAcc
 886 opLat=1
 887
 888 [system.cpu1.fuPool.FUList5.opList08]
 889 type=OpDesc
 890 eventq_index=0
 891 issueLat=1
 892 opClass=SimdShift
 893 opLat=1
 894
 895 [system.cpu1.fuPool.FUList5.opList09]
 896 type=OpDesc
 897 eventq_index=0
 898 issueLat=1
 899 opClass=SimdShiftAcc
 900 opLat=1
 901
 902 [system.cpu1.fuPool.FUList5.opList10]
 903 type=OpDesc
 904 eventq_index=0
 905 issueLat=1
 906 opClass=SimdSqrt
 907 opLat=1
 908
 909 [system.cpu1.fuPool.FUList5.opList11]
 910 type=OpDesc
 911 eventq_index=0
 912 issueLat=1
 913 opClass=SimdFloatAdd
 914 opLat=1
 915
 916 [system.cpu1.fuPool.FUList5.opList12]
 917 type=OpDesc
 918 eventq_index=0
 919 issueLat=1
 920 opClass=SimdFloatAlu
 921 opLat=1
 922
 923 [system.cpu1.fuPool.FUList5.opList13]
 924 type=OpDesc
 925 eventq_index=0
 926 issueLat=1
 927 opClass=SimdFloatCmp
 928 opLat=1
 929
 930 [system.cpu1.fuPool.FUList5.opList14]
 931 type=OpDesc
 932 eventq_index=0
 933 issueLat=1
 934 opClass=SimdFloatCvt
 935 opLat=1
 936
 937 [system.cpu1.fuPool.FUList5.opList15]
 938 type=OpDesc
 939 eventq_index=0
 940 issueLat=1
 941 opClass=SimdFloatDiv
 942 opLat=1
 943
 944 [system.cpu1.fuPool.FUList5.opList16]
 945 type=OpDesc
 946 eventq_index=0
 947 issueLat=1
 948 opClass=SimdFloatMisc
 949 opLat=1
 950
 951 [system.cpu1.fuPool.FUList5.opList17]
 952 type=OpDesc
 953 eventq_index=0
 954 issueLat=1
 955 opClass=SimdFloatMult
 956 opLat=1
 957
 958 [system.cpu1.fuPool.FUList5.opList18]
 959 type=OpDesc
 960 eventq_index=0
 961 issueLat=1
 962 opClass=SimdFloatMultAcc
 963 opLat=1
 964
 965 [system.cpu1.fuPool.FUList5.opList19]
 966 type=OpDesc
 967 eventq_index=0
 968 issueLat=1
 969 opClass=SimdFloatSqrt
 970 opLat=1
 971
 972 [system.cpu1.fuPool.FUList6]
 973 type=FUDesc
 974 children=opList
 975 count=0
 976 eventq_index=0
 977 opList=system.cpu1.fuPool.FUList6.opList
 978
 979 [system.cpu1.fuPool.FUList6.opList]
 980 type=OpDesc
 981 eventq_index=0
 982 issueLat=1
 983 opClass=MemWrite
 984 opLat=1
 985
 986 [system.cpu1.fuPool.FUList7]
 987 type=FUDesc
 988 children=opList0 opList1
 989 count=4
 990 eventq_index=0
 991 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 992
 993 [system.cpu1.fuPool.FUList7.opList0]
 994 type=OpDesc
 995 eventq_index=0
 996 issueLat=1
 997 opClass=MemRead
 998 opLat=1
 999
1000 [system.cpu1.fuPool.FUList7.opList1]
1001 type=OpDesc
1002 eventq_index=0
1003 issueLat=1
1004 opClass=MemWrite
1005 opLat=1
1006
1007 [system.cpu1.fuPool.FUList8]
1008 type=FUDesc
1009 children=opList
1010 count=1
1011 eventq_index=0
1012 opList=system.cpu1.fuPool.FUList8.opList
1013
1014 [system.cpu1.fuPool.FUList8.opList]
1015 type=OpDesc
1016 eventq_index=0
1017 issueLat=3
1018 opClass=IprAccess
1019 opLat=3
1020
1021 [system.cpu1.icache]
1022 type=BaseCache
1023 children=tags
1024 addr_ranges=0:18446744073709551615
1025 assoc=1
1026 clk_domain=system.cpu_clk_domain
1027 eventq_index=0
1028 forward_snoops=true
1029 hit_latency=2
1030 is_top_level=true
1031 max_miss_count=0
1032 mshrs=4
1033 prefetch_on_access=false
1034 prefetcher=Null
1035 response_latency=2
1036 sequential_access=false
1037 size=32768
1038 system=system
1039 tags=system.cpu1.icache.tags
1040 tgts_per_mshr=20
1041 two_queue=false
1042 write_buffers=8
1043 cpu_side=system.cpu1.icache_port
1044 mem_side=system.toL2Bus.slave[2]
1045
1046 [system.cpu1.icache.tags]
1047 type=LRU
1048 assoc=1
1049 block_size=64
1050 clk_domain=system.cpu_clk_domain
1051 eventq_index=0
1052 hit_latency=2
1053 sequential_access=false
1054 size=32768
1055
1056 [system.cpu1.interrupts]
1057 type=AlphaInterrupts
1058 eventq_index=0
1059
1060 [system.cpu1.isa]
1061 type=AlphaISA
1062 eventq_index=0
1063 system=system
1064
1065 [system.cpu1.itb]
1066 type=AlphaTLB
1067 eventq_index=0
1068 size=48
1069
1070 [system.cpu1.tracer]
1071 type=ExeTracer
1072 eventq_index=0
1073
1074 [system.cpu_clk_domain]
1075 type=SrcClockDomain
1076 clock=500
1077 domain_id=-1
1078 eventq_index=0
1079 init_perf_level=0
1080 voltage_domain=system.voltage_domain
1081
1082 [system.disk0]
1083 type=IdeDisk
1084 children=image
1085 delay=1000000
1086 driveID=master
1087 eventq_index=0
1088 image=system.disk0.image
1089
1090 [system.disk0.image]
1091 type=CowDiskImage
1092 children=child
1093 child=system.disk0.image.child
1094 eventq_index=0
1095 image_file=
1096 read_only=false
1097 table_size=65536
1098
1099 [system.disk0.image.child]
1100 type=RawDiskImage
1101 eventq_index=0
1102 image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
1103 read_only=true
1104
1105 [system.disk2]
1106 type=IdeDisk
1107 children=image
1108 delay=1000000
1109 driveID=master
1110 eventq_index=0
1111 image=system.disk2.image
1112
1113 [system.disk2.image]
1114 type=CowDiskImage
1115 children=child
1116 child=system.disk2.image.child
1117 eventq_index=0
1118 image_file=
1119 read_only=false
1120 table_size=65536
1121
1122 [system.disk2.image.child]
1123 type=RawDiskImage
1124 eventq_index=0
1125 image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
1126 read_only=true
1127
1128 [system.dvfs_handler]
1129 type=DVFSHandler
1130 domains=
1131 enable=false
1132 eventq_index=0
1133 sys_clk_domain=system.clk_domain
1134 transition_latency=100000000
1135
1136 [system.intrctrl]
1137 type=IntrControl
1138 eventq_index=0
1139 sys=system
1140
1141 [system.iobus]
1142 type=NoncoherentXBar
1143 clk_domain=system.clk_domain
1144 eventq_index=0
1145 header_cycles=1
1146 use_default_range=true
1147 width=8
1148 default=system.tsunami.pciconfig.pio
1149 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
1150 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
1151
1152 [system.iocache]
1153 type=BaseCache
1154 children=tags
1155 addr_ranges=0:134217727
1156 assoc=8
1157 clk_domain=system.clk_domain
1158 eventq_index=0
1159 forward_snoops=false
1160 hit_latency=50
1161 is_top_level=true
1162 max_miss_count=0
1163 mshrs=20
1164 prefetch_on_access=false
1165 prefetcher=Null
1166 response_latency=50
1167 sequential_access=false
1168 size=1024
1169 system=system
1170 tags=system.iocache.tags
1171 tgts_per_mshr=12
1172 two_queue=false
1173 write_buffers=8
1174 cpu_side=system.iobus.master[29]
1175 mem_side=system.membus.slave[2]
1176
1177 [system.iocache.tags]
1178 type=LRU
1179 assoc=8
1180 block_size=64
1181 clk_domain=system.clk_domain
1182 eventq_index=0
1183 hit_latency=50
1184 sequential_access=false
1185 size=1024
1186
1187 [system.l2c]
1188 type=BaseCache
1189 children=tags
1190 addr_ranges=0:18446744073709551615
1191 assoc=8
1192 clk_domain=system.cpu_clk_domain
1193 eventq_index=0
1194 forward_snoops=true
1195 hit_latency=20
1196 is_top_level=false
1197 max_miss_count=0
1198 mshrs=20
1199 prefetch_on_access=false
1200 prefetcher=Null
1201 response_latency=20
1202 sequential_access=false
1203 size=4194304
1204 system=system
1205 tags=system.l2c.tags
1206 tgts_per_mshr=12
1207 two_queue=false
1208 write_buffers=8
1209 cpu_side=system.toL2Bus.master[0]
1210 mem_side=system.membus.slave[1]
1211
1212 [system.l2c.tags]
1213 type=LRU
1214 assoc=8
1215 block_size=64
1216 clk_domain=system.cpu_clk_domain
1217 eventq_index=0
1218 hit_latency=20
1219 sequential_access=false
1220 size=4194304
1221
1222 [system.membus]
1223 type=CoherentXBar
1224 children=badaddr_responder
1225 clk_domain=system.clk_domain
1226 eventq_index=0
1227 header_cycles=1
1228 snoop_filter=Null
1229 system=system
1230 use_default_range=false
1231 width=8
1232 default=system.membus.badaddr_responder.pio
1233 master=system.bridge.slave system.physmem.port
1234 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1235
1236 [system.membus.badaddr_responder]
1237 type=IsaFake
1238 clk_domain=system.clk_domain
1239 eventq_index=0
1240 fake_mem=false
1241 pio_addr=0
1242 pio_latency=100000
1243 pio_size=8
1244 ret_bad_addr=true
1245 ret_data16=65535
1246 ret_data32=4294967295
1247 ret_data64=18446744073709551615
1248 ret_data8=255
1249 system=system
1250 update_data=false
1251 warn_access=
1252 pio=system.membus.default
1253
1254 [system.physmem]
1255 type=DRAMCtrl
1256 IDD0=0.075000
1257 IDD02=0.000000
1258 IDD2N=0.050000
1259 IDD2N2=0.000000
1260 IDD2P0=0.000000
1261 IDD2P02=0.000000
1262 IDD2P1=0.000000
1263 IDD2P12=0.000000
1264 IDD3N=0.057000
1265 IDD3N2=0.000000
1266 IDD3P0=0.000000
1267 IDD3P02=0.000000
1268 IDD3P1=0.000000
1269 IDD3P12=0.000000
1270 IDD4R=0.187000
1271 IDD4R2=0.000000
1272 IDD4W=0.165000
1273 IDD4W2=0.000000
1274 IDD5=0.220000
1275 IDD52=0.000000
1276 IDD6=0.000000
1277 IDD62=0.000000
1278 VDD=1.500000
1279 VDD2=0.000000
1280 activation_limit=4
1281 addr_mapping=RoRaBaChCo
1282 bank_groups_per_rank=0
1283 banks_per_rank=8
1284 burst_length=8
1285 channels=1
1286 clk_domain=system.clk_domain
1287 conf_table_reported=true
1288 device_bus_width=8
1289 device_rowbuffer_size=1024
1290 devices_per_rank=8
1291 dll=true
1292 eventq_index=0
1293 in_addr_map=true
1294 max_accesses_per_row=16
1295 mem_sched_policy=frfcfs
1296 min_writes_per_switch=16
1297 null=false
1298 page_policy=open_adaptive
1299 range=0:134217727
1300 ranks_per_channel=2
1301 read_buffer_size=32
1302 static_backend_latency=10000
1303 static_frontend_latency=10000
1304 tBURST=5000
1305 tCCD_L=0
1306 tCK=1250
1307 tCL=13750
1308 tCS=2500
1309 tRAS=35000
1310 tRCD=13750
1311 tREFI=7800000
1312 tRFC=260000
1313 tRP=13750
1314 tRRD=6000
1315 tRRD_L=0
1316 tRTP=7500
1317 tRTW=2500
1318 tWR=15000
1319 tWTR=7500
1320 tXAW=30000
1321 tXP=0
1322 tXPDLL=0
1323 tXS=0
1324 tXSDLL=0
1325 write_buffer_size=64
1326 write_high_thresh_perc=85
1327 write_low_thresh_perc=50
1328 port=system.membus.master[1]
1329
1330 [system.simple_disk]
1331 type=SimpleDisk
1332 children=disk
1333 disk=system.simple_disk.disk
1334 eventq_index=0
1335 system=system
1336
1337 [system.simple_disk.disk]
1338 type=RawDiskImage
1339 eventq_index=0
1340 image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
1341 read_only=true
1342
1343 [system.terminal]
1344 type=Terminal
1345 eventq_index=0
1346 intr_control=system.intrctrl
1347 number=0
1348 output=true
1349 port=3456
1350
1351 [system.toL2Bus]
1352 type=CoherentXBar
1353 clk_domain=system.cpu_clk_domain
1354 eventq_index=0
1355 header_cycles=1
1356 snoop_filter=Null
1357 system=system
1358 use_default_range=false
1359 width=8
1360 master=system.l2c.cpu_side
1361 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
1362
1363 [system.tsunami]
1364 type=Tsunami
1365 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1366 eventq_index=0
1367 intrctrl=system.intrctrl
1368 system=system
1369
1370 [system.tsunami.backdoor]
1371 type=AlphaBackdoor
1372 clk_domain=system.clk_domain
1373 cpu=system.cpu0
1374 disk=system.simple_disk
1375 eventq_index=0
1376 pio_addr=8804682956800
1377 pio_latency=100000
1378 platform=system.tsunami
1379 system=system
1380 terminal=system.terminal
1381 pio=system.iobus.master[24]
1382
1383 [system.tsunami.cchip]
1384 type=TsunamiCChip
1385 clk_domain=system.clk_domain
1386 eventq_index=0
1387 pio_addr=8803072344064
1388 pio_latency=100000
1389 system=system
1390 tsunami=system.tsunami
1391 pio=system.iobus.master[0]
1392
1393 [system.tsunami.ethernet]
1394 type=NSGigE
1395 BAR0=1
1396 BAR0LegacyIO=false
1397 BAR0Size=256
1398 BAR1=0
1399 BAR1LegacyIO=false
1400 BAR1Size=4096
1401 BAR2=0
1402 BAR2LegacyIO=false
1403 BAR2Size=0
1404 BAR3=0
1405 BAR3LegacyIO=false
1406 BAR3Size=0
1407 BAR4=0
1408 BAR4LegacyIO=false
1409 BAR4Size=0
1410 BAR5=0
1411 BAR5LegacyIO=false
1412 BAR5Size=0
1413 BIST=0
1414 CacheLineSize=0
1415 CapabilityPtr=0
1416 CardbusCIS=0
1417 ClassCode=2
1418 Command=0
1419 DeviceID=34
1420 ExpansionROM=0
1421 HeaderType=0
1422 InterruptLine=30
1423 InterruptPin=1
1424 LatencyTimer=0
1425 LegacyIOBase=0
1426 MSICAPBaseOffset=0
1427 MSICAPCapId=0
1428 MSICAPMaskBits=0
1429 MSICAPMsgAddr=0
1430 MSICAPMsgCtrl=0
1431 MSICAPMsgData=0
1432 MSICAPMsgUpperAddr=0
1433 MSICAPNextCapability=0
1434 MSICAPPendingBits=0
1435 MSIXCAPBaseOffset=0
1436 MSIXCAPCapId=0
1437 MSIXCAPNextCapability=0
1438 MSIXMsgCtrl=0
1439 MSIXPbaOffset=0
1440 MSIXTableOffset=0
1441 MaximumLatency=52
1442 MinimumGrant=176
1443 PMCAPBaseOffset=0
1444 PMCAPCapId=0
1445 PMCAPCapabilities=0
1446 PMCAPCtrlStatus=0
1447 PMCAPNextCapability=0
1448 PXCAPBaseOffset=0
1449 PXCAPCapId=0
1450 PXCAPCapabilities=0
1451 PXCAPDevCap2=0
1452 PXCAPDevCapabilities=0
1453 PXCAPDevCtrl=0
1454 PXCAPDevCtrl2=0
1455 PXCAPDevStatus=0
1456 PXCAPLinkCap=0
1457 PXCAPLinkCtrl=0
1458 PXCAPLinkStatus=0
1459 PXCAPNextCapability=0
1460 ProgIF=0
1461 Revision=0
1462 Status=656
1463 SubClassCode=0
1464 SubsystemID=0
1465 SubsystemVendorID=0
1466 VendorID=4107
1467 clk_domain=system.clk_domain
1468 config_latency=20000
1469 dma_data_free=false
1470 dma_desc_free=false
1471 dma_no_allocate=true
1472 dma_read_delay=0
1473 dma_read_factor=0
1474 dma_write_delay=0
1475 dma_write_factor=0
1476 eventq_index=0
1477 hardware_address=00:90:00:00:00:01
1478 intr_delay=10000000
1479 pci_bus=0
1480 pci_dev=1
1481 pci_func=0
1482 pio_latency=30000
1483 platform=system.tsunami
1484 rss=false
1485 rx_delay=1000000
1486 rx_fifo_size=524288
1487 rx_filter=true
1488 rx_thread=false
1489 system=system
1490 tx_delay=1000000
1491 tx_fifo_size=524288
1492 tx_thread=false
1493 config=system.iobus.master[28]
1494 dma=system.iobus.slave[2]
1495 pio=system.iobus.master[27]
1496
1497 [system.tsunami.fake_OROM]
1498 type=IsaFake
1499 clk_domain=system.clk_domain
1500 eventq_index=0
1501 fake_mem=false
1502 pio_addr=8796093677568
1503 pio_latency=100000
1504 pio_size=393216
1505 ret_bad_addr=false
1506 ret_data16=65535
1507 ret_data32=4294967295
1508 ret_data64=18446744073709551615
1509 ret_data8=255
1510 system=system
1511 update_data=false
1512 warn_access=
1513 pio=system.iobus.master[8]
1514
1515 [system.tsunami.fake_ata0]
1516 type=IsaFake
1517 clk_domain=system.clk_domain
1518 eventq_index=0
1519 fake_mem=false
1520 pio_addr=8804615848432
1521 pio_latency=100000
1522 pio_size=8
1523 ret_bad_addr=false
1524 ret_data16=65535
1525 ret_data32=4294967295
1526 ret_data64=18446744073709551615
1527 ret_data8=255
1528 system=system
1529 update_data=false
1530 warn_access=
1531 pio=system.iobus.master[19]
1532
1533 [system.tsunami.fake_ata1]
1534 type=IsaFake
1535 clk_domain=system.clk_domain
1536 eventq_index=0
1537 fake_mem=false
1538 pio_addr=8804615848304
1539 pio_latency=100000
1540 pio_size=8
1541 ret_bad_addr=false
1542 ret_data16=65535
1543 ret_data32=4294967295
1544 ret_data64=18446744073709551615
1545 ret_data8=255
1546 system=system
1547 update_data=false
1548 warn_access=
1549 pio=system.iobus.master[20]
1550
1551 [system.tsunami.fake_pnp_addr]
1552 type=IsaFake
1553 clk_domain=system.clk_domain
1554 eventq_index=0
1555 fake_mem=false
1556 pio_addr=8804615848569
1557 pio_latency=100000
1558 pio_size=8
1559 ret_bad_addr=false
1560 ret_data16=65535
1561 ret_data32=4294967295
1562 ret_data64=18446744073709551615
1563 ret_data8=255
1564 system=system
1565 update_data=false
1566 warn_access=
1567 pio=system.iobus.master[9]
1568
1569 [system.tsunami.fake_pnp_read0]
1570 type=IsaFake
1571 clk_domain=system.clk_domain
1572 eventq_index=0
1573 fake_mem=false
1574 pio_addr=8804615848451
1575 pio_latency=100000
1576 pio_size=8
1577 ret_bad_addr=false
1578 ret_data16=65535
1579 ret_data32=4294967295
1580 ret_data64=18446744073709551615
1581 ret_data8=255
1582 system=system
1583 update_data=false
1584 warn_access=
1585 pio=system.iobus.master[11]
1586
1587 [system.tsunami.fake_pnp_read1]
1588 type=IsaFake
1589 clk_domain=system.clk_domain
1590 eventq_index=0
1591 fake_mem=false
1592 pio_addr=8804615848515
1593 pio_latency=100000
1594 pio_size=8
1595 ret_bad_addr=false
1596 ret_data16=65535
1597 ret_data32=4294967295
1598 ret_data64=18446744073709551615
1599 ret_data8=255
1600 system=system
1601 update_data=false
1602 warn_access=
1603 pio=system.iobus.master[12]
1604
1605 [system.tsunami.fake_pnp_read2]
1606 type=IsaFake
1607 clk_domain=system.clk_domain
1608 eventq_index=0
1609 fake_mem=false
1610 pio_addr=8804615848579
1611 pio_latency=100000
1612 pio_size=8
1613 ret_bad_addr=false
1614 ret_data16=65535
1615 ret_data32=4294967295
1616 ret_data64=18446744073709551615
1617 ret_data8=255
1618 system=system
1619 update_data=false
1620 warn_access=
1621 pio=system.iobus.master[13]
1622
1623 [system.tsunami.fake_pnp_read3]
1624 type=IsaFake
1625 clk_domain=system.clk_domain
1626 eventq_index=0
1627 fake_mem=false
1628 pio_addr=8804615848643
1629 pio_latency=100000
1630 pio_size=8
1631 ret_bad_addr=false
1632 ret_data16=65535
1633 ret_data32=4294967295
1634 ret_data64=18446744073709551615
1635 ret_data8=255
1636 system=system
1637 update_data=false
1638 warn_access=
1639 pio=system.iobus.master[14]
1640
1641 [system.tsunami.fake_pnp_read4]
1642 type=IsaFake
1643 clk_domain=system.clk_domain
1644 eventq_index=0
1645 fake_mem=false
1646 pio_addr=8804615848707
1647 pio_latency=100000
1648 pio_size=8
1649 ret_bad_addr=false
1650 ret_data16=65535
1651 ret_data32=4294967295
1652 ret_data64=18446744073709551615
1653 ret_data8=255
1654 system=system
1655 update_data=false
1656 warn_access=
1657 pio=system.iobus.master[15]
1658
1659 [system.tsunami.fake_pnp_read5]
1660 type=IsaFake
1661 clk_domain=system.clk_domain
1662 eventq_index=0
1663 fake_mem=false
1664 pio_addr=8804615848771
1665 pio_latency=100000
1666 pio_size=8
1667 ret_bad_addr=false
1668 ret_data16=65535
1669 ret_data32=4294967295
1670 ret_data64=18446744073709551615
1671 ret_data8=255
1672 system=system
1673 update_data=false
1674 warn_access=
1675 pio=system.iobus.master[16]
1676
1677 [system.tsunami.fake_pnp_read6]
1678 type=IsaFake
1679 clk_domain=system.clk_domain
1680 eventq_index=0
1681 fake_mem=false
1682 pio_addr=8804615848835
1683 pio_latency=100000
1684 pio_size=8
1685 ret_bad_addr=false
1686 ret_data16=65535
1687 ret_data32=4294967295
1688 ret_data64=18446744073709551615
1689 ret_data8=255
1690 system=system
1691 update_data=false
1692 warn_access=
1693 pio=system.iobus.master[17]
1694
1695 [system.tsunami.fake_pnp_read7]
1696 type=IsaFake
1697 clk_domain=system.clk_domain
1698 eventq_index=0
1699 fake_mem=false
1700 pio_addr=8804615848899
1701 pio_latency=100000
1702 pio_size=8
1703 ret_bad_addr=false
1704 ret_data16=65535
1705 ret_data32=4294967295
1706 ret_data64=18446744073709551615
1707 ret_data8=255
1708 system=system
1709 update_data=false
1710 warn_access=
1711 pio=system.iobus.master[18]
1712
1713 [system.tsunami.fake_pnp_write]
1714 type=IsaFake
1715 clk_domain=system.clk_domain
1716 eventq_index=0
1717 fake_mem=false
1718 pio_addr=8804615850617
1719 pio_latency=100000
1720 pio_size=8
1721 ret_bad_addr=false
1722 ret_data16=65535
1723 ret_data32=4294967295
1724 ret_data64=18446744073709551615
1725 ret_data8=255
1726 system=system
1727 update_data=false
1728 warn_access=
1729 pio=system.iobus.master[10]
1730
1731 [system.tsunami.fake_ppc]
1732 type=IsaFake
1733 clk_domain=system.clk_domain
1734 eventq_index=0
1735 fake_mem=false
1736 pio_addr=8804615848891
1737 pio_latency=100000
1738 pio_size=8
1739 ret_bad_addr=false
1740 ret_data16=65535
1741 ret_data32=4294967295
1742 ret_data64=18446744073709551615
1743 ret_data8=255
1744 system=system
1745 update_data=false
1746 warn_access=
1747 pio=system.iobus.master[7]
1748
1749 [system.tsunami.fake_sm_chip]
1750 type=IsaFake
1751 clk_domain=system.clk_domain
1752 eventq_index=0
1753 fake_mem=false
1754 pio_addr=8804615848816
1755 pio_latency=100000
1756 pio_size=8
1757 ret_bad_addr=false
1758 ret_data16=65535
1759 ret_data32=4294967295
1760 ret_data64=18446744073709551615
1761 ret_data8=255
1762 system=system
1763 update_data=false
1764 warn_access=
1765 pio=system.iobus.master[2]
1766
1767 [system.tsunami.fake_uart1]
1768 type=IsaFake
1769 clk_domain=system.clk_domain
1770 eventq_index=0
1771 fake_mem=false
1772 pio_addr=8804615848696
1773 pio_latency=100000
1774 pio_size=8
1775 ret_bad_addr=false
1776 ret_data16=65535
1777 ret_data32=4294967295
1778 ret_data64=18446744073709551615
1779 ret_data8=255
1780 system=system
1781 update_data=false
1782 warn_access=
1783 pio=system.iobus.master[3]
1784
1785 [system.tsunami.fake_uart2]
1786 type=IsaFake
1787 clk_domain=system.clk_domain
1788 eventq_index=0
1789 fake_mem=false
1790 pio_addr=8804615848936
1791 pio_latency=100000
1792 pio_size=8
1793 ret_bad_addr=false
1794 ret_data16=65535
1795 ret_data32=4294967295
1796 ret_data64=18446744073709551615
1797 ret_data8=255
1798 system=system
1799 update_data=false
1800 warn_access=
1801 pio=system.iobus.master[4]
1802
1803 [system.tsunami.fake_uart3]
1804 type=IsaFake
1805 clk_domain=system.clk_domain
1806 eventq_index=0
1807 fake_mem=false
1808 pio_addr=8804615848680
1809 pio_latency=100000
1810 pio_size=8
1811 ret_bad_addr=false
1812 ret_data16=65535
1813 ret_data32=4294967295
1814 ret_data64=18446744073709551615
1815 ret_data8=255
1816 system=system
1817 update_data=false
1818 warn_access=
1819 pio=system.iobus.master[5]
1820
1821 [system.tsunami.fake_uart4]
1822 type=IsaFake
1823 clk_domain=system.clk_domain
1824 eventq_index=0
1825 fake_mem=false
1826 pio_addr=8804615848944
1827 pio_latency=100000
1828 pio_size=8
1829 ret_bad_addr=false
1830 ret_data16=65535
1831 ret_data32=4294967295
1832 ret_data64=18446744073709551615
1833 ret_data8=255
1834 system=system
1835 update_data=false
1836 warn_access=
1837 pio=system.iobus.master[6]
1838
1839 [system.tsunami.fb]
1840 type=BadDevice
1841 clk_domain=system.clk_domain
1842 devicename=FrameBuffer
1843 eventq_index=0
1844 pio_addr=8804615848912
1845 pio_latency=100000
1846 system=system
1847 pio=system.iobus.master[21]
1848
1849 [system.tsunami.ide]
1850 type=IdeController
1851 BAR0=1
1852 BAR0LegacyIO=false
1853 BAR0Size=8
1854 BAR1=1
1855 BAR1LegacyIO=false
1856 BAR1Size=4
1857 BAR2=1
1858 BAR2LegacyIO=false
1859 BAR2Size=8
1860 BAR3=1
1861 BAR3LegacyIO=false
1862 BAR3Size=4
1863 BAR4=1
1864 BAR4LegacyIO=false
1865 BAR4Size=16
1866 BAR5=1
1867 BAR5LegacyIO=false
1868 BAR5Size=0
1869 BIST=0
1870 CacheLineSize=0
1871 CapabilityPtr=0
1872 CardbusCIS=0
1873 ClassCode=1
1874 Command=0
1875 DeviceID=28945
1876 ExpansionROM=0
1877 HeaderType=0
1878 InterruptLine=31
1879 InterruptPin=1
1880 LatencyTimer=0
1881 LegacyIOBase=0
1882 MSICAPBaseOffset=0
1883 MSICAPCapId=0
1884 MSICAPMaskBits=0
1885 MSICAPMsgAddr=0
1886 MSICAPMsgCtrl=0
1887 MSICAPMsgData=0
1888 MSICAPMsgUpperAddr=0
1889 MSICAPNextCapability=0
1890 MSICAPPendingBits=0
1891 MSIXCAPBaseOffset=0
1892 MSIXCAPCapId=0
1893 MSIXCAPNextCapability=0
1894 MSIXMsgCtrl=0
1895 MSIXPbaOffset=0
1896 MSIXTableOffset=0
1897 MaximumLatency=0
1898 MinimumGrant=0
1899 PMCAPBaseOffset=0
1900 PMCAPCapId=0
1901 PMCAPCapabilities=0
1902 PMCAPCtrlStatus=0
1903 PMCAPNextCapability=0
1904 PXCAPBaseOffset=0
1905 PXCAPCapId=0
1906 PXCAPCapabilities=0
1907 PXCAPDevCap2=0
1908 PXCAPDevCapabilities=0
1909 PXCAPDevCtrl=0
1910 PXCAPDevCtrl2=0
1911 PXCAPDevStatus=0
1912 PXCAPLinkCap=0
1913 PXCAPLinkCtrl=0
1914 PXCAPLinkStatus=0
1915 PXCAPNextCapability=0
1916 ProgIF=133
1917 Revision=0
1918 Status=640
1919 SubClassCode=1
1920 SubsystemID=0
1921 SubsystemVendorID=0
1922 VendorID=32902
1923 clk_domain=system.clk_domain
1924 config_latency=20000
1925 ctrl_offset=0
1926 disks=system.disk0 system.disk2
1927 eventq_index=0
1928 io_shift=0
1929 pci_bus=0
1930 pci_dev=0
1931 pci_func=0
1932 pio_latency=30000
1933 platform=system.tsunami
1934 system=system
1935 config=system.iobus.master[26]
1936 dma=system.iobus.slave[1]
1937 pio=system.iobus.master[25]
1938
1939 [system.tsunami.io]
1940 type=TsunamiIO
1941 clk_domain=system.clk_domain
1942 eventq_index=0
1943 frequency=976562500
1944 pio_addr=8804615847936
1945 pio_latency=100000
1946 system=system
1947 time=Thu Jan  1 00:00:00 2009
1948 tsunami=system.tsunami
1949 year_is_bcd=false
1950 pio=system.iobus.master[22]
1951
1952 [system.tsunami.pchip]
1953 type=TsunamiPChip
1954 clk_domain=system.clk_domain
1955 eventq_index=0
1956 pio_addr=8802535473152
1957 pio_latency=100000
1958 system=system
1959 tsunami=system.tsunami
1960 pio=system.iobus.master[1]
1961
1962 [system.tsunami.pciconfig]
1963 type=PciConfigAll
1964 bus=0
1965 clk_domain=system.clk_domain
1966 eventq_index=0
1967 pio_addr=0
1968 pio_latency=30000
1969 platform=system.tsunami
1970 size=16777216
1971 system=system
1972 pio=system.iobus.default
1973
1974 [system.tsunami.uart]
1975 type=Uart8250
1976 clk_domain=system.clk_domain
1977 eventq_index=0
1978 pio_addr=8804615848952
1979 pio_latency=100000
1980 platform=system.tsunami
1981 system=system
1982 terminal=system.terminal
1983 pio=system.iobus.master[23]
1984
1985 [system.voltage_domain]
1986 type=VoltageDomain
1987 eventq_index=0
1988 voltage=1.000000
1989