2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.900728 # Number of seconds simulated
4 sim_ticks 1900727697500 # Number of ticks simulated
5 final_tick 1900727697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 95395 # Simulator instruction rate (inst/s)
8 host_op_rate 95395 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3185234659 # Simulator tick rate (ticks/s)
10 host_mem_usage 355712 # Number of bytes of host memory used
11 host_seconds 596.73 # Real time elapsed on the host
12 sim_insts 56925219 # Number of instructions simulated
13 sim_ops 56925219 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 854208 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 24595840 # Number of bytes read from this memory
16 system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.inst 123328 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.data 541952 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 28767232 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu0.inst 854208 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::cpu1.inst 123328 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 7730048 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7730048 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu0.inst 13347 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu0.data 384310 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu1.inst 1927 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu1.data 8468 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 449488 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 120782 # Number of write requests responded to by this memory
32 system.physmem.num_writes::total 120782 # Number of write requests responded to by this memory
33 system.physmem.bw_read::cpu0.inst 449411 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu0.data 12940223 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu1.inst 64885 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu1.data 285129 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::total 15134852 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::cpu0.inst 449411 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu1.inst 64885 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 514296 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 4066889 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 4066889 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 4066889 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu0.inst 449411 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu0.data 12940223 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu1.inst 64885 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu1.data 285129 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 19201740 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 449488 # Total number of read requests seen
52 system.physmem.writeReqs 120782 # Total number of write requests seen
53 system.physmem.cpureqs 575881 # Reqs generatd by CPU via cache - shady
54 system.physmem.bytesRead 28767232 # Total number of bytes read from memory
55 system.physmem.bytesWritten 7730048 # Total number of bytes written to memory
56 system.physmem.bytesConsumedRd 28767232 # bytesRead derated as per pkt->getSize()
57 system.physmem.bytesConsumedWr 7730048 # bytesWritten derated as per pkt->getSize()
58 system.physmem.servicedByWrQ 76 # Number of read reqs serviced by write Q
59 system.physmem.neitherReadNorWrite 5601 # Reqs where no action is needed
60 system.physmem.perBankRdReqs::0 28386 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::1 28227 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::2 28192 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::3 27982 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::5 28241 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::6 28220 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::7 28022 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::8 28087 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::9 28039 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::11 27938 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::12 27835 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::13 28000 # Track reads on a per bank basis
74 system.physmem.perBankRdReqs::14 27859 # Track reads on a per bank basis
75 system.physmem.perBankRdReqs::15 27848 # Track reads on a per bank basis
76 system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::1 7706 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::2 7703 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::3 7519 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::6 7606 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::7 7518 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::8 7651 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::9 7586 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::10 7578 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::11 7350 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::12 7241 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::13 7443 # Track writes on a per bank basis
90 system.physmem.perBankWrReqs::14 7270 # Track writes on a per bank basis
91 system.physmem.perBankWrReqs::15 7347 # Track writes on a per bank basis
92 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
93 system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
94 system.physmem.totGap 1900723138000 # Total gap between requests
95 system.physmem.readPktSize::0 0 # Categorize read packet sizes
96 system.physmem.readPktSize::1 0 # Categorize read packet sizes
97 system.physmem.readPktSize::2 0 # Categorize read packet sizes
98 system.physmem.readPktSize::3 0 # Categorize read packet sizes
99 system.physmem.readPktSize::4 0 # Categorize read packet sizes
100 system.physmem.readPktSize::5 0 # Categorize read packet sizes
101 system.physmem.readPktSize::6 449488 # Categorize read packet sizes
102 system.physmem.writePktSize::0 0 # Categorize write packet sizes
103 system.physmem.writePktSize::1 0 # Categorize write packet sizes
104 system.physmem.writePktSize::2 0 # Categorize write packet sizes
105 system.physmem.writePktSize::3 0 # Categorize write packet sizes
106 system.physmem.writePktSize::4 0 # Categorize write packet sizes
107 system.physmem.writePktSize::5 0 # Categorize write packet sizes
108 system.physmem.writePktSize::6 120782 # Categorize write packet sizes
109 system.physmem.rdQLenPdf::0 319759 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::1 59264 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::2 32659 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::3 7637 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::5 2957 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::6 2688 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::7 2676 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::8 2637 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::9 2595 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::10 1524 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::11 1455 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::15 1389 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::16 1622 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::17 1546 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::18 914 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
141 system.physmem.wrQLenPdf::0 3169 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::1 3807 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::2 4327 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::3 4374 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::4 4886 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::5 5229 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::7 5236 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::8 5239 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::9 5251 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::10 5251 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::11 5251 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::12 5251 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::13 5251 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::14 5251 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::15 5251 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::16 5251 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::17 5251 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::23 2083 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::24 1445 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::26 878 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::27 366 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
173 system.physmem.totQLat 7717714750 # Total cycles spent in queuing delays
174 system.physmem.totMemAccLat 15508692250 # Sum of mem lat for all requests
175 system.physmem.totBusLat 2247060000 # Total cycles spent in databus access
176 system.physmem.totBankLat 5543917500 # Total cycles spent in bank access
177 system.physmem.avgQLat 17172.92 # Average queueing delay per request
178 system.physmem.avgBankLat 12335.94 # Average bank access latency per request
179 system.physmem.avgBusLat 5000.00 # Average bus latency per request
180 system.physmem.avgMemAccLat 34508.85 # Average memory access latency
181 system.physmem.avgRdBW 15.13 # Average achieved read bandwidth in MB/s
182 system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s
183 system.physmem.avgConsumedRdBW 15.13 # Average consumed read bandwidth in MB/s
184 system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s
185 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
186 system.physmem.busUtil 0.15 # Data bus utilization in percentage
187 system.physmem.avgRdQLen 0.01 # Average read queue length over time
188 system.physmem.avgWrQLen 9.47 # Average write queue length over time
189 system.physmem.readRowHits 421565 # Number of row buffer hits during reads
190 system.physmem.writeRowHits 92877 # Number of row buffer hits during writes
191 system.physmem.readRowHitRate 93.80 # Row buffer hit rate for reads
192 system.physmem.writeRowHitRate 76.90 # Row buffer hit rate for writes
193 system.physmem.avgGap 3333023.20 # Average gap between requests
194 system.l2c.replacements 342612 # number of replacements
195 system.l2c.tagsinuse 65284.978501 # Cycle average of tags in use
196 system.l2c.total_refs 2568846 # Total number of references to valid blocks.
197 system.l2c.sampled_refs 407591 # Sample count of references to valid blocks.
198 system.l2c.avg_refs 6.302509 # Average number of references to valid blocks.
199 system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit.
200 system.l2c.occ_blocks::writebacks 53776.613719 # Average occupied blocks per requestor
201 system.l2c.occ_blocks::cpu0.inst 5305.208058 # Average occupied blocks per requestor
202 system.l2c.occ_blocks::cpu0.data 5913.214949 # Average occupied blocks per requestor
203 system.l2c.occ_blocks::cpu1.inst 209.652371 # Average occupied blocks per requestor
204 system.l2c.occ_blocks::cpu1.data 80.289403 # Average occupied blocks per requestor
205 system.l2c.occ_percent::writebacks 0.820566 # Average percentage of cache occupancy
206 system.l2c.occ_percent::cpu0.inst 0.080951 # Average percentage of cache occupancy
207 system.l2c.occ_percent::cpu0.data 0.090228 # Average percentage of cache occupancy
208 system.l2c.occ_percent::cpu1.inst 0.003199 # Average percentage of cache occupancy
209 system.l2c.occ_percent::cpu1.data 0.001225 # Average percentage of cache occupancy
210 system.l2c.occ_percent::total 0.996170 # Average percentage of cache occupancy
211 system.l2c.ReadReq_hits::cpu0.inst 815517 # number of ReadReq hits
212 system.l2c.ReadReq_hits::cpu0.data 714323 # number of ReadReq hits
213 system.l2c.ReadReq_hits::cpu1.inst 262022 # number of ReadReq hits
214 system.l2c.ReadReq_hits::cpu1.data 83603 # number of ReadReq hits
215 system.l2c.ReadReq_hits::total 1875465 # number of ReadReq hits
216 system.l2c.Writeback_hits::writebacks 814738 # number of Writeback hits
217 system.l2c.Writeback_hits::total 814738 # number of Writeback hits
218 system.l2c.UpgradeReq_hits::cpu0.data 171 # number of UpgradeReq hits
219 system.l2c.UpgradeReq_hits::cpu1.data 348 # number of UpgradeReq hits
220 system.l2c.UpgradeReq_hits::total 519 # number of UpgradeReq hits
221 system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits
222 system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits
223 system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
224 system.l2c.ReadExReq_hits::cpu0.data 146870 # number of ReadExReq hits
225 system.l2c.ReadExReq_hits::cpu1.data 31835 # number of ReadExReq hits
226 system.l2c.ReadExReq_hits::total 178705 # number of ReadExReq hits
227 system.l2c.demand_hits::cpu0.inst 815517 # number of demand (read+write) hits
228 system.l2c.demand_hits::cpu0.data 861193 # number of demand (read+write) hits
229 system.l2c.demand_hits::cpu1.inst 262022 # number of demand (read+write) hits
230 system.l2c.demand_hits::cpu1.data 115438 # number of demand (read+write) hits
231 system.l2c.demand_hits::total 2054170 # number of demand (read+write) hits
232 system.l2c.overall_hits::cpu0.inst 815517 # number of overall hits
233 system.l2c.overall_hits::cpu0.data 861193 # number of overall hits
234 system.l2c.overall_hits::cpu1.inst 262022 # number of overall hits
235 system.l2c.overall_hits::cpu1.data 115438 # number of overall hits
236 system.l2c.overall_hits::total 2054170 # number of overall hits
237 system.l2c.ReadReq_misses::cpu0.inst 13350 # number of ReadReq misses
238 system.l2c.ReadReq_misses::cpu0.data 272975 # number of ReadReq misses
239 system.l2c.ReadReq_misses::cpu1.inst 1943 # number of ReadReq misses
240 system.l2c.ReadReq_misses::cpu1.data 909 # number of ReadReq misses
241 system.l2c.ReadReq_misses::total 289177 # number of ReadReq misses
242 system.l2c.UpgradeReq_misses::cpu0.data 2763 # number of UpgradeReq misses
243 system.l2c.UpgradeReq_misses::cpu1.data 1336 # number of UpgradeReq misses
244 system.l2c.UpgradeReq_misses::total 4099 # number of UpgradeReq misses
245 system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses
246 system.l2c.SCUpgradeReq_misses::cpu1.data 587 # number of SCUpgradeReq misses
247 system.l2c.SCUpgradeReq_misses::total 1147 # number of SCUpgradeReq misses
248 system.l2c.ReadExReq_misses::cpu0.data 111935 # number of ReadExReq misses
249 system.l2c.ReadExReq_misses::cpu1.data 7677 # number of ReadExReq misses
250 system.l2c.ReadExReq_misses::total 119612 # number of ReadExReq misses
251 system.l2c.demand_misses::cpu0.inst 13350 # number of demand (read+write) misses
252 system.l2c.demand_misses::cpu0.data 384910 # number of demand (read+write) misses
253 system.l2c.demand_misses::cpu1.inst 1943 # number of demand (read+write) misses
254 system.l2c.demand_misses::cpu1.data 8586 # number of demand (read+write) misses
255 system.l2c.demand_misses::total 408789 # number of demand (read+write) misses
256 system.l2c.overall_misses::cpu0.inst 13350 # number of overall misses
257 system.l2c.overall_misses::cpu0.data 384910 # number of overall misses
258 system.l2c.overall_misses::cpu1.inst 1943 # number of overall misses
259 system.l2c.overall_misses::cpu1.data 8586 # number of overall misses
260 system.l2c.overall_misses::total 408789 # number of overall misses
261 system.l2c.ReadReq_miss_latency::cpu0.inst 905376000 # number of ReadReq miss cycles
262 system.l2c.ReadReq_miss_latency::cpu0.data 11896032500 # number of ReadReq miss cycles
263 system.l2c.ReadReq_miss_latency::cpu1.inst 147196500 # number of ReadReq miss cycles
264 system.l2c.ReadReq_miss_latency::cpu1.data 67006500 # number of ReadReq miss cycles
265 system.l2c.ReadReq_miss_latency::total 13015611500 # number of ReadReq miss cycles
266 system.l2c.UpgradeReq_miss_latency::cpu0.data 1013500 # number of UpgradeReq miss cycles
267 system.l2c.UpgradeReq_miss_latency::cpu1.data 6347986 # number of UpgradeReq miss cycles
268 system.l2c.UpgradeReq_miss_latency::total 7361486 # number of UpgradeReq miss cycles
269 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 894999 # number of SCUpgradeReq miss cycles
270 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 135500 # number of SCUpgradeReq miss cycles
271 system.l2c.SCUpgradeReq_miss_latency::total 1030499 # number of SCUpgradeReq miss cycles
272 system.l2c.ReadExReq_miss_latency::cpu0.data 7317066000 # number of ReadExReq miss cycles
273 system.l2c.ReadExReq_miss_latency::cpu1.data 777197999 # number of ReadExReq miss cycles
274 system.l2c.ReadExReq_miss_latency::total 8094263999 # number of ReadExReq miss cycles
275 system.l2c.demand_miss_latency::cpu0.inst 905376000 # number of demand (read+write) miss cycles
276 system.l2c.demand_miss_latency::cpu0.data 19213098500 # number of demand (read+write) miss cycles
277 system.l2c.demand_miss_latency::cpu1.inst 147196500 # number of demand (read+write) miss cycles
278 system.l2c.demand_miss_latency::cpu1.data 844204499 # number of demand (read+write) miss cycles
279 system.l2c.demand_miss_latency::total 21109875499 # number of demand (read+write) miss cycles
280 system.l2c.overall_miss_latency::cpu0.inst 905376000 # number of overall miss cycles
281 system.l2c.overall_miss_latency::cpu0.data 19213098500 # number of overall miss cycles
282 system.l2c.overall_miss_latency::cpu1.inst 147196500 # number of overall miss cycles
283 system.l2c.overall_miss_latency::cpu1.data 844204499 # number of overall miss cycles
284 system.l2c.overall_miss_latency::total 21109875499 # number of overall miss cycles
285 system.l2c.ReadReq_accesses::cpu0.inst 828867 # number of ReadReq accesses(hits+misses)
286 system.l2c.ReadReq_accesses::cpu0.data 987298 # number of ReadReq accesses(hits+misses)
287 system.l2c.ReadReq_accesses::cpu1.inst 263965 # number of ReadReq accesses(hits+misses)
288 system.l2c.ReadReq_accesses::cpu1.data 84512 # number of ReadReq accesses(hits+misses)
289 system.l2c.ReadReq_accesses::total 2164642 # number of ReadReq accesses(hits+misses)
290 system.l2c.Writeback_accesses::writebacks 814738 # number of Writeback accesses(hits+misses)
291 system.l2c.Writeback_accesses::total 814738 # number of Writeback accesses(hits+misses)
292 system.l2c.UpgradeReq_accesses::cpu0.data 2934 # number of UpgradeReq accesses(hits+misses)
293 system.l2c.UpgradeReq_accesses::cpu1.data 1684 # number of UpgradeReq accesses(hits+misses)
294 system.l2c.UpgradeReq_accesses::total 4618 # number of UpgradeReq accesses(hits+misses)
295 system.l2c.SCUpgradeReq_accesses::cpu0.data 608 # number of SCUpgradeReq accesses(hits+misses)
296 system.l2c.SCUpgradeReq_accesses::cpu1.data 614 # number of SCUpgradeReq accesses(hits+misses)
297 system.l2c.SCUpgradeReq_accesses::total 1222 # number of SCUpgradeReq accesses(hits+misses)
298 system.l2c.ReadExReq_accesses::cpu0.data 258805 # number of ReadExReq accesses(hits+misses)
299 system.l2c.ReadExReq_accesses::cpu1.data 39512 # number of ReadExReq accesses(hits+misses)
300 system.l2c.ReadExReq_accesses::total 298317 # number of ReadExReq accesses(hits+misses)
301 system.l2c.demand_accesses::cpu0.inst 828867 # number of demand (read+write) accesses
302 system.l2c.demand_accesses::cpu0.data 1246103 # number of demand (read+write) accesses
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317 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793349 # miss rate for UpgradeReq accesses
318 system.l2c.UpgradeReq_miss_rate::total 0.887614 # miss rate for UpgradeReq accesses
319 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921053 # miss rate for SCUpgradeReq accesses
320 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956026 # miss rate for SCUpgradeReq accesses
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341 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4751.486527 # average UpgradeReq miss latency
342 system.l2c.UpgradeReq_avg_miss_latency::total 1795.922420 # average UpgradeReq miss latency
343 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1598.212500 # average SCUpgradeReq miss latency
344 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 230.834753 # average SCUpgradeReq miss latency
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360 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
361 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
362 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
363 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
364 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
365 system.l2c.fast_writes 0 # number of fast writes performed
366 system.l2c.cache_copies 0 # number of cache copies performed
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368 system.l2c.writebacks::total 79262 # number of writebacks
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430 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28759000 # number of ReadReq MSHR uncacheable cycles
431 system.l2c.ReadReq_mshr_uncacheable_latency::total 1389083000 # number of ReadReq MSHR uncacheable cycles
432 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2032921000 # number of WriteReq MSHR uncacheable cycles
433 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637490500 # number of WriteReq MSHR uncacheable cycles
434 system.l2c.WriteReq_mshr_uncacheable_latency::total 2670411500 # number of WriteReq MSHR uncacheable cycles
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439 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276487 # mshr miss rate for ReadReq accesses
440 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for ReadReq accesses
441 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010744 # mshr miss rate for ReadReq accesses
442 system.l2c.ReadReq_mshr_miss_rate::total 0.133583 # mshr miss rate for ReadReq accesses
443 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941718 # mshr miss rate for UpgradeReq accesses
444 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.793349 # mshr miss rate for UpgradeReq accesses
445 system.l2c.UpgradeReq_mshr_miss_rate::total 0.887614 # mshr miss rate for UpgradeReq accesses
446 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921053 # mshr miss rate for SCUpgradeReq accesses
447 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956026 # mshr miss rate for SCUpgradeReq accesses
448 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.938625 # mshr miss rate for SCUpgradeReq accesses
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450 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.194295 # mshr miss rate for ReadExReq accesses
451 system.l2c.ReadExReq_mshr_miss_rate::total 0.400956 # mshr miss rate for ReadExReq accesses
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453 system.l2c.demand_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for demand accesses
454 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for demand accesses
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456 system.l2c.demand_mshr_miss_rate::total 0.165967 # mshr miss rate for demand accesses
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460 system.l2c.overall_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for overall accesses
461 system.l2c.overall_mshr_miss_rate::total 0.165967 # mshr miss rate for overall accesses
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463 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31335.411763 # average ReadReq mshr miss latency
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465 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61506.550661 # average ReadReq mshr miss latency
466 system.l2c.ReadReq_avg_mshr_miss_latency::total 32753.464222 # average ReadReq mshr miss latency
467 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10074.820123 # average UpgradeReq mshr miss latency
468 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.529940 # average UpgradeReq mshr miss latency
469 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10064.295682 # average UpgradeReq mshr miss latency
470 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.796429 # average SCUpgradeReq mshr miss latency
471 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494 # average SCUpgradeReq mshr miss latency
472 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.834350 # average SCUpgradeReq mshr miss latency
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474 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89017.938387 # average ReadExReq mshr miss latency
475 system.l2c.ReadExReq_avg_mshr_miss_latency::total 55482.280482 # average ReadExReq mshr miss latency
476 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
477 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
478 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
479 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
480 system.l2c.demand_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
481 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
482 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
483 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
484 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
485 system.l2c.overall_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
486 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
487 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
488 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
489 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
490 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
491 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
492 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
493 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
494 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
495 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
496 system.iocache.replacements 41699 # number of replacements
497 system.iocache.tagsinuse 0.509421 # Cycle average of tags in use
498 system.iocache.total_refs 0 # Total number of references to valid blocks.
499 system.iocache.sampled_refs 41715 # Sample count of references to valid blocks.
500 system.iocache.avg_refs 0 # Average number of references to valid blocks.
501 system.iocache.warmup_cycle 1705456216000 # Cycle when the warmup percentage was hit.
502 system.iocache.occ_blocks::tsunami.ide 0.509421 # Average occupied blocks per requestor
503 system.iocache.occ_percent::tsunami.ide 0.031839 # Average percentage of cache occupancy
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505 system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
506 system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
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516 system.iocache.WriteReq_miss_latency::total 10647231164 # number of WriteReq miss cycles
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522 system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
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528 system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
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530 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
531 system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
532 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
533 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
534 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
535 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
536 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
537 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120759.765363 # average ReadReq miss latency
538 system.iocache.ReadReq_avg_miss_latency::total 120759.765363 # average ReadReq miss latency
539 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885 # average WriteReq miss latency
540 system.iocache.WriteReq_avg_miss_latency::total 256238.716885 # average WriteReq miss latency
541 system.iocache.demand_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency
542 system.iocache.demand_avg_miss_latency::total 255657.596559 # average overall miss latency
543 system.iocache.overall_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency
544 system.iocache.overall_avg_miss_latency::total 255657.596559 # average overall miss latency
545 system.iocache.blocked_cycles::no_mshrs 286486 # number of cycles access was blocked
546 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
547 system.iocache.blocked::no_mshrs 27218 # number of cycles access was blocked
548 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
549 system.iocache.avg_blocked_cycles::no_mshrs 10.525608 # average number of cycles each access was blocked
550 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
551 system.iocache.fast_writes 0 # number of fast writes performed
552 system.iocache.cache_copies 0 # number of cache copies performed
553 system.iocache.writebacks::writebacks 41520 # number of writebacks
554 system.iocache.writebacks::total 41520 # number of writebacks
555 system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses
556 system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses
557 system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
558 system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
559 system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses
560 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses
561 system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses
562 system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses
563 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12307249 # number of ReadReq MSHR miss cycles
564 system.iocache.ReadReq_mshr_miss_latency::total 12307249 # number of ReadReq MSHR miss cycles
565 system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8485239667 # number of WriteReq MSHR miss cycles
566 system.iocache.WriteReq_mshr_miss_latency::total 8485239667 # number of WriteReq MSHR miss cycles
567 system.iocache.demand_mshr_miss_latency::tsunami.ide 8497546916 # number of demand (read+write) MSHR miss cycles
568 system.iocache.demand_mshr_miss_latency::total 8497546916 # number of demand (read+write) MSHR miss cycles
569 system.iocache.overall_mshr_miss_latency::tsunami.ide 8497546916 # number of overall MSHR miss cycles
570 system.iocache.overall_mshr_miss_latency::total 8497546916 # number of overall MSHR miss cycles
571 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
572 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
573 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
574 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
575 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
576 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
577 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
578 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
579 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68755.581006 # average ReadReq mshr miss latency
580 system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006 # average ReadReq mshr miss latency
581 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204207.731686 # average WriteReq mshr miss latency
582 system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686 # average WriteReq mshr miss latency
583 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency
584 system.iocache.demand_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
585 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency
586 system.iocache.overall_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
587 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
588 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
589 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
590 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
591 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
592 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
593 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
594 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
595 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
596 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
597 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
598 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
599 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
600 system.cpu0.branchPred.lookups 12035820 # Number of BP lookups
601 system.cpu0.branchPred.condPredicted 10146181 # Number of conditional branches predicted
602 system.cpu0.branchPred.condIncorrect 320311 # Number of conditional branches incorrect
603 system.cpu0.branchPred.BTBLookups 7799891 # Number of BTB lookups
604 system.cpu0.branchPred.BTBHits 5138186 # Number of BTB hits
605 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
606 system.cpu0.branchPred.BTBHitPct 65.875100 # BTB Hit Percentage
607 system.cpu0.branchPred.usedRAS 760204 # Number of times the RAS was used to get a target.
608 system.cpu0.branchPred.RASInCorrect 30176 # Number of incorrect RAS predictions.
609 system.cpu0.dtb.fetch_hits 0 # ITB hits
610 system.cpu0.dtb.fetch_misses 0 # ITB misses
611 system.cpu0.dtb.fetch_acv 0 # ITB acv
612 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
613 system.cpu0.dtb.read_hits 8551483 # DTB read hits
614 system.cpu0.dtb.read_misses 30199 # DTB read misses
615 system.cpu0.dtb.read_acv 541 # DTB read access violations
616 system.cpu0.dtb.read_accesses 624803 # DTB read accesses
617 system.cpu0.dtb.write_hits 5601236 # DTB write hits
618 system.cpu0.dtb.write_misses 7972 # DTB write misses
619 system.cpu0.dtb.write_acv 345 # DTB write access violations
620 system.cpu0.dtb.write_accesses 208308 # DTB write accesses
621 system.cpu0.dtb.data_hits 14152719 # DTB hits
622 system.cpu0.dtb.data_misses 38171 # DTB misses
623 system.cpu0.dtb.data_acv 886 # DTB access violations
624 system.cpu0.dtb.data_accesses 833111 # DTB accesses
625 system.cpu0.itb.fetch_hits 970030 # ITB hits
626 system.cpu0.itb.fetch_misses 28776 # ITB misses
627 system.cpu0.itb.fetch_acv 920 # ITB acv
628 system.cpu0.itb.fetch_accesses 998806 # ITB accesses
629 system.cpu0.itb.read_hits 0 # DTB read hits
630 system.cpu0.itb.read_misses 0 # DTB read misses
631 system.cpu0.itb.read_acv 0 # DTB read access violations
632 system.cpu0.itb.read_accesses 0 # DTB read accesses
633 system.cpu0.itb.write_hits 0 # DTB write hits
634 system.cpu0.itb.write_misses 0 # DTB write misses
635 system.cpu0.itb.write_acv 0 # DTB write access violations
636 system.cpu0.itb.write_accesses 0 # DTB write accesses
637 system.cpu0.itb.data_hits 0 # DTB hits
638 system.cpu0.itb.data_misses 0 # DTB misses
639 system.cpu0.itb.data_acv 0 # DTB access violations
640 system.cpu0.itb.data_accesses 0 # DTB accesses
641 system.cpu0.numCycles 100119117 # number of cpu cycles simulated
642 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
643 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
644 system.cpu0.fetch.icacheStallCycles 24086973 # Number of cycles fetch is stalled on an Icache miss
645 system.cpu0.fetch.Insts 61837518 # Number of instructions fetch has processed
646 system.cpu0.fetch.Branches 12035820 # Number of branches that fetch encountered
647 system.cpu0.fetch.predictedBranches 5898390 # Number of branches that fetch has predicted taken
648 system.cpu0.fetch.Cycles 11653378 # Number of cycles fetch has run and was not squashing or blocked
649 system.cpu0.fetch.SquashCycles 1636628 # Number of cycles fetch has spent squashing
650 system.cpu0.fetch.BlockedCycles 36048574 # Number of cycles fetch has spent blocked
651 system.cpu0.fetch.MiscStallCycles 32004 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
652 system.cpu0.fetch.PendingTrapStallCycles 195358 # Number of stall cycles due to pending traps
653 system.cpu0.fetch.PendingQuiesceStallCycles 286105 # Number of stall cycles due to pending quiesce instructions
654 system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
655 system.cpu0.fetch.CacheLines 7499654 # Number of cache lines fetched
656 system.cpu0.fetch.IcacheSquashes 215735 # Number of outstanding Icache misses that were squashed
657 system.cpu0.fetch.rateDist::samples 73358875 # Number of instructions fetched each cycle (Total)
658 system.cpu0.fetch.rateDist::mean 0.842945 # Number of instructions fetched each cycle (Total)
659 system.cpu0.fetch.rateDist::stdev 2.179502 # Number of instructions fetched each cycle (Total)
660 system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
661 system.cpu0.fetch.rateDist::0 61705497 84.11% 84.11% # Number of instructions fetched each cycle (Total)
662 system.cpu0.fetch.rateDist::1 747609 1.02% 85.13% # Number of instructions fetched each cycle (Total)
663 system.cpu0.fetch.rateDist::2 1536097 2.09% 87.23% # Number of instructions fetched each cycle (Total)
664 system.cpu0.fetch.rateDist::3 679694 0.93% 88.15% # Number of instructions fetched each cycle (Total)
665 system.cpu0.fetch.rateDist::4 2532720 3.45% 91.61% # Number of instructions fetched each cycle (Total)
666 system.cpu0.fetch.rateDist::5 506441 0.69% 92.30% # Number of instructions fetched each cycle (Total)
667 system.cpu0.fetch.rateDist::6 557934 0.76% 93.06% # Number of instructions fetched each cycle (Total)
668 system.cpu0.fetch.rateDist::7 775120 1.06% 94.11% # Number of instructions fetched each cycle (Total)
669 system.cpu0.fetch.rateDist::8 4317763 5.89% 100.00% # Number of instructions fetched each cycle (Total)
670 system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
671 system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
672 system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
673 system.cpu0.fetch.rateDist::total 73358875 # Number of instructions fetched each cycle (Total)
674 system.cpu0.fetch.branchRate 0.120215 # Number of branch fetches per cycle
675 system.cpu0.fetch.rate 0.617639 # Number of inst fetches per cycle
676 system.cpu0.decode.IdleCycles 25314409 # Number of cycles decode is idle
677 system.cpu0.decode.BlockedCycles 35520182 # Number of cycles decode is blocked
678 system.cpu0.decode.RunCycles 10594612 # Number of cycles decode is running
679 system.cpu0.decode.UnblockCycles 907065 # Number of cycles decode is unblocking
680 system.cpu0.decode.SquashCycles 1022606 # Number of cycles decode is squashing
681 system.cpu0.decode.BranchResolved 498090 # Number of times decode resolved a branch
682 system.cpu0.decode.BranchMispred 33900 # Number of times decode detected a branch misprediction
683 system.cpu0.decode.DecodedInsts 60717129 # Number of instructions handled by decode
684 system.cpu0.decode.SquashedInsts 100549 # Number of squashed instructions handled by decode
685 system.cpu0.rename.SquashCycles 1022606 # Number of cycles rename is squashing
686 system.cpu0.rename.IdleCycles 26293542 # Number of cycles rename is idle
687 system.cpu0.rename.BlockCycles 14517617 # Number of cycles rename is blocking
688 system.cpu0.rename.serializeStallCycles 17593984 # count of cycles rename stalled for serializing inst
689 system.cpu0.rename.RunCycles 9931348 # Number of cycles rename is running
690 system.cpu0.rename.UnblockCycles 3999776 # Number of cycles rename is unblocking
691 system.cpu0.rename.RenamedInsts 57516764 # Number of instructions processed by rename
692 system.cpu0.rename.ROBFullEvents 6773 # Number of times rename has blocked due to ROB full
693 system.cpu0.rename.IQFullEvents 634732 # Number of times rename has blocked due to IQ full
694 system.cpu0.rename.LSQFullEvents 1395914 # Number of times rename has blocked due to LSQ full
695 system.cpu0.rename.RenamedOperands 38573698 # Number of destination operands rename has renamed
696 system.cpu0.rename.RenameLookups 70135572 # Number of register rename lookups that rename has made
697 system.cpu0.rename.int_rename_lookups 69772127 # Number of integer rename lookups
698 system.cpu0.rename.fp_rename_lookups 363445 # Number of floating rename lookups
699 system.cpu0.rename.CommittedMaps 33935332 # Number of HB maps that are committed
700 system.cpu0.rename.UndoneMaps 4638358 # Number of HB maps that are undone due to squashing
701 system.cpu0.rename.serializingInsts 1391962 # count of serializing insts renamed
702 system.cpu0.rename.tempSerializingInsts 201915 # count of temporary serializing insts renamed
703 system.cpu0.rename.skidInsts 10849961 # count of insts added to the skid buffer
704 system.cpu0.memDep0.insertedLoads 8944130 # Number of loads inserted to the mem dependence unit.
705 system.cpu0.memDep0.insertedStores 5848227 # Number of stores inserted to the mem dependence unit.
706 system.cpu0.memDep0.conflictingLoads 1106835 # Number of conflicting loads.
707 system.cpu0.memDep0.conflictingStores 734658 # Number of conflicting stores.
708 system.cpu0.iq.iqInstsAdded 51076458 # Number of instructions added to the IQ (excludes non-spec)
709 system.cpu0.iq.iqNonSpecInstsAdded 1725873 # Number of non-speculative instructions added to the IQ
710 system.cpu0.iq.iqInstsIssued 49974476 # Number of instructions issued
711 system.cpu0.iq.iqSquashedInstsIssued 73247 # Number of squashed instructions issued
712 system.cpu0.iq.iqSquashedInstsExamined 5675710 # Number of squashed instructions iterated over during squash; mainly for profiling
713 system.cpu0.iq.iqSquashedOperandsExamined 2876244 # Number of squashed operands that are examined and possibly removed from graph
714 system.cpu0.iq.iqSquashedNonSpecRemoved 1167818 # Number of squashed non-spec instructions that were removed
715 system.cpu0.iq.issued_per_cycle::samples 73358875 # Number of insts issued each cycle
716 system.cpu0.iq.issued_per_cycle::mean 0.681233 # Number of insts issued each cycle
717 system.cpu0.iq.issued_per_cycle::stdev 1.330312 # Number of insts issued each cycle
718 system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
719 system.cpu0.iq.issued_per_cycle::0 51151747 69.73% 69.73% # Number of insts issued each cycle
720 system.cpu0.iq.issued_per_cycle::1 10102031 13.77% 83.50% # Number of insts issued each cycle
721 system.cpu0.iq.issued_per_cycle::2 4555933 6.21% 89.71% # Number of insts issued each cycle
722 system.cpu0.iq.issued_per_cycle::3 2996125 4.08% 93.79% # Number of insts issued each cycle
723 system.cpu0.iq.issued_per_cycle::4 2381484 3.25% 97.04% # Number of insts issued each cycle
724 system.cpu0.iq.issued_per_cycle::5 1187378 1.62% 98.66% # Number of insts issued each cycle
725 system.cpu0.iq.issued_per_cycle::6 631915 0.86% 99.52% # Number of insts issued each cycle
726 system.cpu0.iq.issued_per_cycle::7 300208 0.41% 99.93% # Number of insts issued each cycle
727 system.cpu0.iq.issued_per_cycle::8 52054 0.07% 100.00% # Number of insts issued each cycle
728 system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
729 system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
730 system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
731 system.cpu0.iq.issued_per_cycle::total 73358875 # Number of insts issued each cycle
732 system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
733 system.cpu0.iq.fu_full::IntAlu 82701 12.59% 12.59% # attempts to use FU when none available
734 system.cpu0.iq.fu_full::IntMult 0 0.00% 12.59% # attempts to use FU when none available
735 system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.59% # attempts to use FU when none available
736 system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.59% # attempts to use FU when none available
737 system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available
738 system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available
739 system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available
740 system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available
741 system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
742 system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available
743 system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available
744 system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available
745 system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available
746 system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available
747 system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available
748 system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available
749 system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available
750 system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available
751 system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available
752 system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available
753 system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available
754 system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available
755 system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available
756 system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available
757 system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available
758 system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available
759 system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available
760 system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available
761 system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
762 system.cpu0.iq.fu_full::MemRead 300975 45.82% 58.41% # attempts to use FU when none available
763 system.cpu0.iq.fu_full::MemWrite 273171 41.59% 100.00% # attempts to use FU when none available
764 system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
765 system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
766 system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued
767 system.cpu0.iq.FU_type_0::IntAlu 34554089 69.14% 69.15% # Type of FU issued
768 system.cpu0.iq.FU_type_0::IntMult 54830 0.11% 69.26% # Type of FU issued
769 system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued
770 system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued
771 system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued
772 system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued
773 system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued
774 system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued
775 system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued
776 system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued
777 system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued
778 system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued
779 system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued
780 system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued
781 system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued
782 system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued
783 system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued
784 system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued
785 system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued
786 system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued
787 system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.30% # Type of FU issued
788 system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued
789 system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued
790 system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued
791 system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued
792 system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued
793 system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued
794 system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued
795 system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued
796 system.cpu0.iq.FU_type_0::MemRead 8894109 17.80% 87.09% # Type of FU issued
797 system.cpu0.iq.FU_type_0::MemWrite 5667707 11.34% 98.43% # Type of FU issued
798 system.cpu0.iq.FU_type_0::IprAccess 782820 1.57% 100.00% # Type of FU issued
799 system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
800 system.cpu0.iq.FU_type_0::total 49974476 # Type of FU issued
801 system.cpu0.iq.rate 0.499150 # Inst issue rate
802 system.cpu0.iq.fu_busy_cnt 656847 # FU busy when requested
803 system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst)
804 system.cpu0.iq.int_inst_queue_reads 173517181 # Number of integer instruction queue reads
805 system.cpu0.iq.int_inst_queue_writes 58238103 # Number of integer instruction queue writes
806 system.cpu0.iq.int_inst_queue_wakeup_accesses 48994356 # Number of integer instruction queue wakeup accesses
807 system.cpu0.iq.fp_inst_queue_reads 520739 # Number of floating instruction queue reads
808 system.cpu0.iq.fp_inst_queue_writes 252277 # Number of floating instruction queue writes
809 system.cpu0.iq.fp_inst_queue_wakeup_accesses 246003 # Number of floating instruction queue wakeup accesses
810 system.cpu0.iq.int_alu_accesses 50355146 # Number of integer alu accesses
811 system.cpu0.iq.fp_alu_accesses 272403 # Number of floating point alu accesses
812 system.cpu0.iew.lsq.thread0.forwLoads 532794 # Number of loads that had data forwarded from stores
813 system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
814 system.cpu0.iew.lsq.thread0.squashedLoads 1055829 # Number of loads squashed
815 system.cpu0.iew.lsq.thread0.ignoredResponses 3465 # Number of memory responses ignored because the instruction is squashed
816 system.cpu0.iew.lsq.thread0.memOrderViolation 12581 # Number of memory ordering violations
817 system.cpu0.iew.lsq.thread0.squashedStores 434891 # Number of stores squashed
818 system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
819 system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
820 system.cpu0.iew.lsq.thread0.rescheduledLoads 18411 # Number of loads that were rescheduled
821 system.cpu0.iew.lsq.thread0.cacheBlocked 121190 # Number of times an access to memory failed due to the cache being blocked
822 system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
823 system.cpu0.iew.iewSquashCycles 1022606 # Number of cycles IEW is squashing
824 system.cpu0.iew.iewBlockCycles 10355478 # Number of cycles IEW is blocking
825 system.cpu0.iew.iewUnblockCycles 778603 # Number of cycles IEW is unblocking
826 system.cpu0.iew.iewDispatchedInsts 55935625 # Number of instructions dispatched to IQ
827 system.cpu0.iew.iewDispSquashedInsts 586886 # Number of squashed instructions skipped by dispatch
828 system.cpu0.iew.iewDispLoadInsts 8944130 # Number of dispatched load instructions
829 system.cpu0.iew.iewDispStoreInsts 5848227 # Number of dispatched store instructions
830 system.cpu0.iew.iewDispNonSpecInsts 1520110 # Number of dispatched non-speculative instructions
831 system.cpu0.iew.iewIQFullEvents 566642 # Number of times the IQ has become full, causing a stall
832 system.cpu0.iew.iewLSQFullEvents 4768 # Number of times the LSQ has become full, causing a stall
833 system.cpu0.iew.memOrderViolationEvents 12581 # Number of memory order violations
834 system.cpu0.iew.predictedTakenIncorrect 160372 # Number of branches that were predicted taken incorrectly
835 system.cpu0.iew.predictedNotTakenIncorrect 334885 # Number of branches that were predicted not taken incorrectly
836 system.cpu0.iew.branchMispredicts 495257 # Number of branch mispredicts detected at execute
837 system.cpu0.iew.iewExecutedInsts 49597141 # Number of executed instructions
838 system.cpu0.iew.iewExecLoadInsts 8604090 # Number of load instructions executed
839 system.cpu0.iew.iewExecSquashedInsts 377334 # Number of squashed instructions skipped in execute
840 system.cpu0.iew.exec_swp 0 # number of swp insts executed
841 system.cpu0.iew.exec_nop 3133294 # number of nop insts executed
842 system.cpu0.iew.exec_refs 14226525 # number of memory reference insts executed
843 system.cpu0.iew.exec_branches 7904799 # Number of branches executed
844 system.cpu0.iew.exec_stores 5622435 # Number of stores executed
845 system.cpu0.iew.exec_rate 0.495381 # Inst execution rate
846 system.cpu0.iew.wb_sent 49326582 # cumulative count of insts sent to commit
847 system.cpu0.iew.wb_count 49240359 # cumulative count of insts written-back
848 system.cpu0.iew.wb_producers 24624844 # num instructions producing a value
849 system.cpu0.iew.wb_consumers 33143444 # num instructions consuming a value
850 system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
851 system.cpu0.iew.wb_rate 0.491818 # insts written-back per cycle
852 system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back
853 system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
854 system.cpu0.commit.commitSquashedInsts 6108836 # The number of squashed insts skipped by commit
855 system.cpu0.commit.commitNonSpecStalls 558055 # The number of times commit has been forced to stall to communicate backwards
856 system.cpu0.commit.branchMispredicts 462633 # The number of times a branch was mispredicted
857 system.cpu0.commit.committed_per_cycle::samples 72336269 # Number of insts commited each cycle
858 system.cpu0.commit.committed_per_cycle::mean 0.687326 # Number of insts commited each cycle
859 system.cpu0.commit.committed_per_cycle::stdev 1.603373 # Number of insts commited each cycle
860 system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
861 system.cpu0.commit.committed_per_cycle::0 53637775 74.15% 74.15% # Number of insts commited each cycle
862 system.cpu0.commit.committed_per_cycle::1 7794815 10.78% 84.93% # Number of insts commited each cycle
863 system.cpu0.commit.committed_per_cycle::2 4279099 5.92% 90.84% # Number of insts commited each cycle
864 system.cpu0.commit.committed_per_cycle::3 2307939 3.19% 94.03% # Number of insts commited each cycle
865 system.cpu0.commit.committed_per_cycle::4 1284633 1.78% 95.81% # Number of insts commited each cycle
866 system.cpu0.commit.committed_per_cycle::5 537599 0.74% 96.55% # Number of insts commited each cycle
867 system.cpu0.commit.committed_per_cycle::6 458507 0.63% 97.19% # Number of insts commited each cycle
868 system.cpu0.commit.committed_per_cycle::7 423032 0.58% 97.77% # Number of insts commited each cycle
869 system.cpu0.commit.committed_per_cycle::8 1612870 2.23% 100.00% # Number of insts commited each cycle
870 system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
871 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
872 system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
873 system.cpu0.commit.committed_per_cycle::total 72336269 # Number of insts commited each cycle
874 system.cpu0.commit.committedInsts 49718583 # Number of instructions committed
875 system.cpu0.commit.committedOps 49718583 # Number of ops (including micro ops) committed
876 system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
877 system.cpu0.commit.refs 13301637 # Number of memory references committed
878 system.cpu0.commit.loads 7888301 # Number of loads committed
879 system.cpu0.commit.membars 189589 # Number of memory barriers committed
880 system.cpu0.commit.branches 7515884 # Number of branches committed
881 system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions.
882 system.cpu0.commit.int_insts 46055357 # Number of committed integer instructions.
883 system.cpu0.commit.function_calls 629203 # Number of function calls committed.
884 system.cpu0.commit.bw_lim_events 1612870 # number cycles where commit BW limit reached
885 system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
886 system.cpu0.rob.rob_reads 126355419 # The number of ROB reads
887 system.cpu0.rob.rob_writes 112677687 # The number of ROB writes
888 system.cpu0.timesIdled 1033455 # Number of times that the entire CPU went into an idle state and unscheduled itself
889 system.cpu0.idleCycles 26760242 # Total number of cycles that the CPU has spent unscheduled due to idling
890 system.cpu0.quiesceCycles 3701329669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
891 system.cpu0.committedInsts 46863203 # Number of Instructions Simulated
892 system.cpu0.committedOps 46863203 # Number of Ops (including micro ops) Simulated
893 system.cpu0.committedInsts_total 46863203 # Number of Instructions Simulated
894 system.cpu0.cpi 2.136412 # CPI: Cycles Per Instruction
895 system.cpu0.cpi_total 2.136412 # CPI: Total CPI of All Threads
896 system.cpu0.ipc 0.468074 # IPC: Instructions Per Cycle
897 system.cpu0.ipc_total 0.468074 # IPC: Total IPC of All Threads
898 system.cpu0.int_regfile_reads 65361385 # number of integer regfile reads
899 system.cpu0.int_regfile_writes 35679513 # number of integer regfile writes
900 system.cpu0.fp_regfile_reads 120846 # number of floating regfile reads
901 system.cpu0.fp_regfile_writes 122066 # number of floating regfile writes
902 system.cpu0.misc_regfile_reads 1631915 # number of misc regfile reads
903 system.cpu0.misc_regfile_writes 781460 # number of misc regfile writes
904 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
905 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
906 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
907 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
908 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
909 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
910 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
911 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
912 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
913 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
914 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
915 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
916 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
917 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
918 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
919 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
920 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
921 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
922 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
923 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
924 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
925 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
926 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
927 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
928 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
929 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
930 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
931 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
932 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
933 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
934 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
935 system.cpu0.icache.replacements 828283 # number of replacements
936 system.cpu0.icache.tagsinuse 510.309737 # Cycle average of tags in use
937 system.cpu0.icache.total_refs 6629306 # Total number of references to valid blocks.
938 system.cpu0.icache.sampled_refs 828795 # Sample count of references to valid blocks.
939 system.cpu0.icache.avg_refs 7.998728 # Average number of references to valid blocks.
940 system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit.
941 system.cpu0.icache.occ_blocks::cpu0.inst 510.309737 # Average occupied blocks per requestor
942 system.cpu0.icache.occ_percent::cpu0.inst 0.996699 # Average percentage of cache occupancy
943 system.cpu0.icache.occ_percent::total 0.996699 # Average percentage of cache occupancy
944 system.cpu0.icache.ReadReq_hits::cpu0.inst 6629306 # number of ReadReq hits
945 system.cpu0.icache.ReadReq_hits::total 6629306 # number of ReadReq hits
946 system.cpu0.icache.demand_hits::cpu0.inst 6629306 # number of demand (read+write) hits
947 system.cpu0.icache.demand_hits::total 6629306 # number of demand (read+write) hits
948 system.cpu0.icache.overall_hits::cpu0.inst 6629306 # number of overall hits
949 system.cpu0.icache.overall_hits::total 6629306 # number of overall hits
950 system.cpu0.icache.ReadReq_misses::cpu0.inst 870348 # number of ReadReq misses
951 system.cpu0.icache.ReadReq_misses::total 870348 # number of ReadReq misses
952 system.cpu0.icache.demand_misses::cpu0.inst 870348 # number of demand (read+write) misses
953 system.cpu0.icache.demand_misses::total 870348 # number of demand (read+write) misses
954 system.cpu0.icache.overall_misses::cpu0.inst 870348 # number of overall misses
955 system.cpu0.icache.overall_misses::total 870348 # number of overall misses
956 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12313538494 # number of ReadReq miss cycles
957 system.cpu0.icache.ReadReq_miss_latency::total 12313538494 # number of ReadReq miss cycles
958 system.cpu0.icache.demand_miss_latency::cpu0.inst 12313538494 # number of demand (read+write) miss cycles
959 system.cpu0.icache.demand_miss_latency::total 12313538494 # number of demand (read+write) miss cycles
960 system.cpu0.icache.overall_miss_latency::cpu0.inst 12313538494 # number of overall miss cycles
961 system.cpu0.icache.overall_miss_latency::total 12313538494 # number of overall miss cycles
962 system.cpu0.icache.ReadReq_accesses::cpu0.inst 7499654 # number of ReadReq accesses(hits+misses)
963 system.cpu0.icache.ReadReq_accesses::total 7499654 # number of ReadReq accesses(hits+misses)
964 system.cpu0.icache.demand_accesses::cpu0.inst 7499654 # number of demand (read+write) accesses
965 system.cpu0.icache.demand_accesses::total 7499654 # number of demand (read+write) accesses
966 system.cpu0.icache.overall_accesses::cpu0.inst 7499654 # number of overall (read+write) accesses
967 system.cpu0.icache.overall_accesses::total 7499654 # number of overall (read+write) accesses
968 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116052 # miss rate for ReadReq accesses
969 system.cpu0.icache.ReadReq_miss_rate::total 0.116052 # miss rate for ReadReq accesses
970 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116052 # miss rate for demand accesses
971 system.cpu0.icache.demand_miss_rate::total 0.116052 # miss rate for demand accesses
972 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116052 # miss rate for overall accesses
973 system.cpu0.icache.overall_miss_rate::total 0.116052 # miss rate for overall accesses
974 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388 # average ReadReq miss latency
975 system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388 # average ReadReq miss latency
976 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
977 system.cpu0.icache.demand_avg_miss_latency::total 14147.833388 # average overall miss latency
978 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
979 system.cpu0.icache.overall_avg_miss_latency::total 14147.833388 # average overall miss latency
980 system.cpu0.icache.blocked_cycles::no_mshrs 3221 # number of cycles access was blocked
981 system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked
982 system.cpu0.icache.blocked::no_mshrs 147 # number of cycles access was blocked
983 system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
984 system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.911565 # average number of cycles each access was blocked
985 system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked
986 system.cpu0.icache.fast_writes 0 # number of fast writes performed
987 system.cpu0.icache.cache_copies 0 # number of cache copies performed
988 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41379 # number of ReadReq MSHR hits
989 system.cpu0.icache.ReadReq_mshr_hits::total 41379 # number of ReadReq MSHR hits
990 system.cpu0.icache.demand_mshr_hits::cpu0.inst 41379 # number of demand (read+write) MSHR hits
991 system.cpu0.icache.demand_mshr_hits::total 41379 # number of demand (read+write) MSHR hits
992 system.cpu0.icache.overall_mshr_hits::cpu0.inst 41379 # number of overall MSHR hits
993 system.cpu0.icache.overall_mshr_hits::total 41379 # number of overall MSHR hits
994 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 828969 # number of ReadReq MSHR misses
995 system.cpu0.icache.ReadReq_mshr_misses::total 828969 # number of ReadReq MSHR misses
996 system.cpu0.icache.demand_mshr_misses::cpu0.inst 828969 # number of demand (read+write) MSHR misses
997 system.cpu0.icache.demand_mshr_misses::total 828969 # number of demand (read+write) MSHR misses
998 system.cpu0.icache.overall_mshr_misses::cpu0.inst 828969 # number of overall MSHR misses
999 system.cpu0.icache.overall_mshr_misses::total 828969 # number of overall MSHR misses
1000 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10141631994 # number of ReadReq MSHR miss cycles
1001 system.cpu0.icache.ReadReq_mshr_miss_latency::total 10141631994 # number of ReadReq MSHR miss cycles
1002 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10141631994 # number of demand (read+write) MSHR miss cycles
1003 system.cpu0.icache.demand_mshr_miss_latency::total 10141631994 # number of demand (read+write) MSHR miss cycles
1004 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10141631994 # number of overall MSHR miss cycles
1005 system.cpu0.icache.overall_mshr_miss_latency::total 10141631994 # number of overall MSHR miss cycles
1006 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for ReadReq accesses
1007 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110534 # mshr miss rate for ReadReq accesses
1008 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for demand accesses
1009 system.cpu0.icache.demand_mshr_miss_rate::total 0.110534 # mshr miss rate for demand accesses
1010 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for overall accesses
1011 system.cpu0.icache.overall_mshr_miss_rate::total 0.110534 # mshr miss rate for overall accesses
1012 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average ReadReq mshr miss latency
1013 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.030457 # average ReadReq mshr miss latency
1014 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency
1015 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency
1016 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency
1017 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency
1018 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1019 system.cpu0.dcache.replacements 1248455 # number of replacements
1020 system.cpu0.dcache.tagsinuse 505.645673 # Cycle average of tags in use
1021 system.cpu0.dcache.total_refs 10073371 # Total number of references to valid blocks.
1022 system.cpu0.dcache.sampled_refs 1248967 # Sample count of references to valid blocks.
1023 system.cpu0.dcache.avg_refs 8.065362 # Average number of references to valid blocks.
1024 system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit.
1025 system.cpu0.dcache.occ_blocks::cpu0.data 505.645673 # Average occupied blocks per requestor
1026 system.cpu0.dcache.occ_percent::cpu0.data 0.987589 # Average percentage of cache occupancy
1027 system.cpu0.dcache.occ_percent::total 0.987589 # Average percentage of cache occupancy
1028 system.cpu0.dcache.ReadReq_hits::cpu0.data 6208704 # number of ReadReq hits
1029 system.cpu0.dcache.ReadReq_hits::total 6208704 # number of ReadReq hits
1030 system.cpu0.dcache.WriteReq_hits::cpu0.data 3519183 # number of WriteReq hits
1031 system.cpu0.dcache.WriteReq_hits::total 3519183 # number of WriteReq hits
1032 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154511 # number of LoadLockedReq hits
1033 system.cpu0.dcache.LoadLockedReq_hits::total 154511 # number of LoadLockedReq hits
1034 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177820 # number of StoreCondReq hits
1035 system.cpu0.dcache.StoreCondReq_hits::total 177820 # number of StoreCondReq hits
1036 system.cpu0.dcache.demand_hits::cpu0.data 9727887 # number of demand (read+write) hits
1037 system.cpu0.dcache.demand_hits::total 9727887 # number of demand (read+write) hits
1038 system.cpu0.dcache.overall_hits::cpu0.data 9727887 # number of overall hits
1039 system.cpu0.dcache.overall_hits::total 9727887 # number of overall hits
1040 system.cpu0.dcache.ReadReq_misses::cpu0.data 1543041 # number of ReadReq misses
1041 system.cpu0.dcache.ReadReq_misses::total 1543041 # number of ReadReq misses
1042 system.cpu0.dcache.WriteReq_misses::cpu0.data 1697976 # number of WriteReq misses
1043 system.cpu0.dcache.WriteReq_misses::total 1697976 # number of WriteReq misses
1044 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses
1045 system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses
1046 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3730 # number of StoreCondReq misses
1047 system.cpu0.dcache.StoreCondReq_misses::total 3730 # number of StoreCondReq misses
1048 system.cpu0.dcache.demand_misses::cpu0.data 3241017 # number of demand (read+write) misses
1049 system.cpu0.dcache.demand_misses::total 3241017 # number of demand (read+write) misses
1050 system.cpu0.dcache.overall_misses::cpu0.data 3241017 # number of overall misses
1051 system.cpu0.dcache.overall_misses::total 3241017 # number of overall misses
1052 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33524463000 # number of ReadReq miss cycles
1053 system.cpu0.dcache.ReadReq_miss_latency::total 33524463000 # number of ReadReq miss cycles
1054 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64948533233 # number of WriteReq miss cycles
1055 system.cpu0.dcache.WriteReq_miss_latency::total 64948533233 # number of WriteReq miss cycles
1056 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277752500 # number of LoadLockedReq miss cycles
1057 system.cpu0.dcache.LoadLockedReq_miss_latency::total 277752500 # number of LoadLockedReq miss cycles
1058 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27309500 # number of StoreCondReq miss cycles
1059 system.cpu0.dcache.StoreCondReq_miss_latency::total 27309500 # number of StoreCondReq miss cycles
1060 system.cpu0.dcache.demand_miss_latency::cpu0.data 98472996233 # number of demand (read+write) miss cycles
1061 system.cpu0.dcache.demand_miss_latency::total 98472996233 # number of demand (read+write) miss cycles
1062 system.cpu0.dcache.overall_miss_latency::cpu0.data 98472996233 # number of overall miss cycles
1063 system.cpu0.dcache.overall_miss_latency::total 98472996233 # number of overall miss cycles
1064 system.cpu0.dcache.ReadReq_accesses::cpu0.data 7751745 # number of ReadReq accesses(hits+misses)
1065 system.cpu0.dcache.ReadReq_accesses::total 7751745 # number of ReadReq accesses(hits+misses)
1066 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217159 # number of WriteReq accesses(hits+misses)
1067 system.cpu0.dcache.WriteReq_accesses::total 5217159 # number of WriteReq accesses(hits+misses)
1068 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174240 # number of LoadLockedReq accesses(hits+misses)
1069 system.cpu0.dcache.LoadLockedReq_accesses::total 174240 # number of LoadLockedReq accesses(hits+misses)
1070 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181550 # number of StoreCondReq accesses(hits+misses)
1071 system.cpu0.dcache.StoreCondReq_accesses::total 181550 # number of StoreCondReq accesses(hits+misses)
1072 system.cpu0.dcache.demand_accesses::cpu0.data 12968904 # number of demand (read+write) accesses
1073 system.cpu0.dcache.demand_accesses::total 12968904 # number of demand (read+write) accesses
1074 system.cpu0.dcache.overall_accesses::cpu0.data 12968904 # number of overall (read+write) accesses
1075 system.cpu0.dcache.overall_accesses::total 12968904 # number of overall (read+write) accesses
1076 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199057 # miss rate for ReadReq accesses
1077 system.cpu0.dcache.ReadReq_miss_rate::total 0.199057 # miss rate for ReadReq accesses
1078 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325460 # miss rate for WriteReq accesses
1079 system.cpu0.dcache.WriteReq_miss_rate::total 0.325460 # miss rate for WriteReq accesses
1080 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113229 # miss rate for LoadLockedReq accesses
1081 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113229 # miss rate for LoadLockedReq accesses
1082 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020545 # miss rate for StoreCondReq accesses
1083 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020545 # miss rate for StoreCondReq accesses
1084 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249907 # miss rate for demand accesses
1085 system.cpu0.dcache.demand_miss_rate::total 0.249907 # miss rate for demand accesses
1086 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249907 # miss rate for overall accesses
1087 system.cpu0.dcache.overall_miss_rate::total 0.249907 # miss rate for overall accesses
1088 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21726.229569 # average ReadReq miss latency
1089 system.cpu0.dcache.ReadReq_avg_miss_latency::total 21726.229569 # average ReadReq miss latency
1090 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38250.560216 # average WriteReq miss latency
1091 system.cpu0.dcache.WriteReq_avg_miss_latency::total 38250.560216 # average WriteReq miss latency
1092 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14078.387146 # average LoadLockedReq miss latency
1093 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146 # average LoadLockedReq miss latency
1094 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7321.581769 # average StoreCondReq miss latency
1095 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7321.581769 # average StoreCondReq miss latency
1096 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency
1097 system.cpu0.dcache.demand_avg_miss_latency::total 30383.363072 # average overall miss latency
1098 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency
1099 system.cpu0.dcache.overall_avg_miss_latency::total 30383.363072 # average overall miss latency
1100 system.cpu0.dcache.blocked_cycles::no_mshrs 2097721 # number of cycles access was blocked
1101 system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked
1102 system.cpu0.dcache.blocked::no_mshrs 47310 # number of cycles access was blocked
1103 system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
1104 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.339907 # average number of cycles each access was blocked
1105 system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked
1106 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1107 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1108 system.cpu0.dcache.writebacks::writebacks 729852 # number of writebacks
1109 system.cpu0.dcache.writebacks::total 729852 # number of writebacks
1110 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558383 # number of ReadReq MSHR hits
1111 system.cpu0.dcache.ReadReq_mshr_hits::total 558383 # number of ReadReq MSHR hits
1112 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432185 # number of WriteReq MSHR hits
1113 system.cpu0.dcache.WriteReq_mshr_hits::total 1432185 # number of WriteReq MSHR hits
1114 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4312 # number of LoadLockedReq MSHR hits
1115 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4312 # number of LoadLockedReq MSHR hits
1116 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990568 # number of demand (read+write) MSHR hits
1117 system.cpu0.dcache.demand_mshr_hits::total 1990568 # number of demand (read+write) MSHR hits
1118 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990568 # number of overall MSHR hits
1119 system.cpu0.dcache.overall_mshr_hits::total 1990568 # number of overall MSHR hits
1120 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984658 # number of ReadReq MSHR misses
1121 system.cpu0.dcache.ReadReq_mshr_misses::total 984658 # number of ReadReq MSHR misses
1122 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265791 # number of WriteReq MSHR misses
1123 system.cpu0.dcache.WriteReq_mshr_misses::total 265791 # number of WriteReq MSHR misses
1124 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15417 # number of LoadLockedReq MSHR misses
1125 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15417 # number of LoadLockedReq MSHR misses
1126 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3730 # number of StoreCondReq MSHR misses
1127 system.cpu0.dcache.StoreCondReq_mshr_misses::total 3730 # number of StoreCondReq MSHR misses
1128 system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250449 # number of demand (read+write) MSHR misses
1129 system.cpu0.dcache.demand_mshr_misses::total 1250449 # number of demand (read+write) MSHR misses
1130 system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250449 # number of overall MSHR misses
1131 system.cpu0.dcache.overall_mshr_misses::total 1250449 # number of overall MSHR misses
1132 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21282308500 # number of ReadReq MSHR miss cycles
1133 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21282308500 # number of ReadReq MSHR miss cycles
1134 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9459587261 # number of WriteReq MSHR miss cycles
1135 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9459587261 # number of WriteReq MSHR miss cycles
1136 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170557000 # number of LoadLockedReq MSHR miss cycles
1137 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170557000 # number of LoadLockedReq MSHR miss cycles
1138 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19849500 # number of StoreCondReq MSHR miss cycles
1139 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19849500 # number of StoreCondReq MSHR miss cycles
1140 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30741895761 # number of demand (read+write) MSHR miss cycles
1141 system.cpu0.dcache.demand_mshr_miss_latency::total 30741895761 # number of demand (read+write) MSHR miss cycles
1142 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30741895761 # number of overall MSHR miss cycles
1143 system.cpu0.dcache.overall_mshr_miss_latency::total 30741895761 # number of overall MSHR miss cycles
1144 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451668000 # number of ReadReq MSHR uncacheable cycles
1145 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451668000 # number of ReadReq MSHR uncacheable cycles
1146 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2155602499 # number of WriteReq MSHR uncacheable cycles
1147 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2155602499 # number of WriteReq MSHR uncacheable cycles
1148 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607270499 # number of overall MSHR uncacheable cycles
1149 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607270499 # number of overall MSHR uncacheable cycles
1150 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127024 # mshr miss rate for ReadReq accesses
1151 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127024 # mshr miss rate for ReadReq accesses
1152 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050946 # mshr miss rate for WriteReq accesses
1153 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050946 # mshr miss rate for WriteReq accesses
1154 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088481 # mshr miss rate for LoadLockedReq accesses
1155 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088481 # mshr miss rate for LoadLockedReq accesses
1156 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020545 # mshr miss rate for StoreCondReq accesses
1157 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020545 # mshr miss rate for StoreCondReq accesses
1158 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for demand accesses
1159 system.cpu0.dcache.demand_mshr_miss_rate::total 0.096419 # mshr miss rate for demand accesses
1160 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for overall accesses
1161 system.cpu0.dcache.overall_mshr_miss_rate::total 0.096419 # mshr miss rate for overall accesses
1162 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093 # average ReadReq mshr miss latency
1163 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093 # average ReadReq mshr miss latency
1164 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948 # average WriteReq mshr miss latency
1165 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948 # average WriteReq mshr miss latency
1166 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559 # average LoadLockedReq mshr miss latency
1167 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559 # average LoadLockedReq mshr miss latency
1168 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5321.581769 # average StoreCondReq mshr miss latency
1169 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5321.581769 # average StoreCondReq mshr miss latency
1170 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
1171 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
1172 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
1173 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
1174 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1175 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1176 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1177 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1178 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1179 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1180 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1181 system.cpu1.branchPred.lookups 2951275 # Number of BP lookups
1182 system.cpu1.branchPred.condPredicted 2437405 # Number of conditional branches predicted
1183 system.cpu1.branchPred.condIncorrect 83356 # Number of conditional branches incorrect
1184 system.cpu1.branchPred.BTBLookups 1836683 # Number of BTB lookups
1185 system.cpu1.branchPred.BTBHits 994148 # Number of BTB hits
1186 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1187 system.cpu1.branchPred.BTBHitPct 54.127359 # BTB Hit Percentage
1188 system.cpu1.branchPred.usedRAS 203977 # Number of times the RAS was used to get a target.
1189 system.cpu1.branchPred.RASInCorrect 9132 # Number of incorrect RAS predictions.
1190 system.cpu1.dtb.fetch_hits 0 # ITB hits
1191 system.cpu1.dtb.fetch_misses 0 # ITB misses
1192 system.cpu1.dtb.fetch_acv 0 # ITB acv
1193 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1194 system.cpu1.dtb.read_hits 2175721 # DTB read hits
1195 system.cpu1.dtb.read_misses 10990 # DTB read misses
1196 system.cpu1.dtb.read_acv 22 # DTB read access violations
1197 system.cpu1.dtb.read_accesses 324709 # DTB read accesses
1198 system.cpu1.dtb.write_hits 1432957 # DTB write hits
1199 system.cpu1.dtb.write_misses 2208 # DTB write misses
1200 system.cpu1.dtb.write_acv 64 # DTB write access violations
1201 system.cpu1.dtb.write_accesses 133156 # DTB write accesses
1202 system.cpu1.dtb.data_hits 3608678 # DTB hits
1203 system.cpu1.dtb.data_misses 13198 # DTB misses
1204 system.cpu1.dtb.data_acv 86 # DTB access violations
1205 system.cpu1.dtb.data_accesses 457865 # DTB accesses
1206 system.cpu1.itb.fetch_hits 458401 # ITB hits
1207 system.cpu1.itb.fetch_misses 7664 # ITB misses
1208 system.cpu1.itb.fetch_acv 238 # ITB acv
1209 system.cpu1.itb.fetch_accesses 466065 # ITB accesses
1210 system.cpu1.itb.read_hits 0 # DTB read hits
1211 system.cpu1.itb.read_misses 0 # DTB read misses
1212 system.cpu1.itb.read_acv 0 # DTB read access violations
1213 system.cpu1.itb.read_accesses 0 # DTB read accesses
1214 system.cpu1.itb.write_hits 0 # DTB write hits
1215 system.cpu1.itb.write_misses 0 # DTB write misses
1216 system.cpu1.itb.write_acv 0 # DTB write access violations
1217 system.cpu1.itb.write_accesses 0 # DTB write accesses
1218 system.cpu1.itb.data_hits 0 # DTB hits
1219 system.cpu1.itb.data_misses 0 # DTB misses
1220 system.cpu1.itb.data_acv 0 # DTB access violations
1221 system.cpu1.itb.data_accesses 0 # DTB accesses
1222 system.cpu1.numCycles 18142763 # number of cpu cycles simulated
1223 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1224 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1225 system.cpu1.fetch.icacheStallCycles 7059665 # Number of cycles fetch is stalled on an Icache miss
1226 system.cpu1.fetch.Insts 13904860 # Number of instructions fetch has processed
1227 system.cpu1.fetch.Branches 2951275 # Number of branches that fetch encountered
1228 system.cpu1.fetch.predictedBranches 1198125 # Number of branches that fetch has predicted taken
1229 system.cpu1.fetch.Cycles 2489767 # Number of cycles fetch has run and was not squashing or blocked
1230 system.cpu1.fetch.SquashCycles 435348 # Number of cycles fetch has spent squashing
1231 system.cpu1.fetch.BlockedCycles 7028149 # Number of cycles fetch has spent blocked
1232 system.cpu1.fetch.MiscStallCycles 27735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1233 system.cpu1.fetch.PendingTrapStallCycles 66683 # Number of stall cycles due to pending traps
1234 system.cpu1.fetch.PendingQuiesceStallCycles 53717 # Number of stall cycles due to pending quiesce instructions
1235 system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
1236 system.cpu1.fetch.CacheLines 1666090 # Number of cache lines fetched
1237 system.cpu1.fetch.IcacheSquashes 56854 # Number of outstanding Icache misses that were squashed
1238 system.cpu1.fetch.rateDist::samples 17001992 # Number of instructions fetched each cycle (Total)
1239 system.cpu1.fetch.rateDist::mean 0.817837 # Number of instructions fetched each cycle (Total)
1240 system.cpu1.fetch.rateDist::stdev 2.192062 # Number of instructions fetched each cycle (Total)
1241 system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1242 system.cpu1.fetch.rateDist::0 14512225 85.36% 85.36% # Number of instructions fetched each cycle (Total)
1243 system.cpu1.fetch.rateDist::1 164132 0.97% 86.32% # Number of instructions fetched each cycle (Total)
1244 system.cpu1.fetch.rateDist::2 264549 1.56% 87.88% # Number of instructions fetched each cycle (Total)
1245 system.cpu1.fetch.rateDist::3 196224 1.15% 89.03% # Number of instructions fetched each cycle (Total)
1246 system.cpu1.fetch.rateDist::4 340931 2.01% 91.04% # Number of instructions fetched each cycle (Total)
1247 system.cpu1.fetch.rateDist::5 130664 0.77% 91.81% # Number of instructions fetched each cycle (Total)
1248 system.cpu1.fetch.rateDist::6 146583 0.86% 92.67% # Number of instructions fetched each cycle (Total)
1249 system.cpu1.fetch.rateDist::7 247056 1.45% 94.12% # Number of instructions fetched each cycle (Total)
1250 system.cpu1.fetch.rateDist::8 999628 5.88% 100.00% # Number of instructions fetched each cycle (Total)
1251 system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1252 system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1253 system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1254 system.cpu1.fetch.rateDist::total 17001992 # Number of instructions fetched each cycle (Total)
1255 system.cpu1.fetch.branchRate 0.162670 # Number of branch fetches per cycle
1256 system.cpu1.fetch.rate 0.766414 # Number of inst fetches per cycle
1257 system.cpu1.decode.IdleCycles 6935204 # Number of cycles decode is idle
1258 system.cpu1.decode.BlockedCycles 7342187 # Number of cycles decode is blocked
1259 system.cpu1.decode.RunCycles 2328189 # Number of cycles decode is running
1260 system.cpu1.decode.UnblockCycles 128213 # Number of cycles decode is unblocking
1261 system.cpu1.decode.SquashCycles 268198 # Number of cycles decode is squashing
1262 system.cpu1.decode.BranchResolved 130237 # Number of times decode resolved a branch
1263 system.cpu1.decode.BranchMispred 8176 # Number of times decode detected a branch misprediction
1264 system.cpu1.decode.DecodedInsts 13648246 # Number of instructions handled by decode
1265 system.cpu1.decode.SquashedInsts 24564 # Number of squashed instructions handled by decode
1266 system.cpu1.rename.SquashCycles 268198 # Number of cycles rename is squashing
1267 system.cpu1.rename.IdleCycles 7169583 # Number of cycles rename is idle
1268 system.cpu1.rename.BlockCycles 530321 # Number of cycles rename is blocking
1269 system.cpu1.rename.serializeStallCycles 6090332 # count of cycles rename stalled for serializing inst
1270 system.cpu1.rename.RunCycles 2220482 # Number of cycles rename is running
1271 system.cpu1.rename.UnblockCycles 723074 # Number of cycles rename is unblocking
1272 system.cpu1.rename.RenamedInsts 12659443 # Number of instructions processed by rename
1273 system.cpu1.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
1274 system.cpu1.rename.IQFullEvents 62425 # Number of times rename has blocked due to IQ full
1275 system.cpu1.rename.LSQFullEvents 176745 # Number of times rename has blocked due to LSQ full
1276 system.cpu1.rename.RenamedOperands 8295078 # Number of destination operands rename has renamed
1277 system.cpu1.rename.RenameLookups 15050859 # Number of register rename lookups that rename has made
1278 system.cpu1.rename.int_rename_lookups 14876046 # Number of integer rename lookups
1279 system.cpu1.rename.fp_rename_lookups 174813 # Number of floating rename lookups
1280 system.cpu1.rename.CommittedMaps 7154813 # Number of HB maps that are committed
1281 system.cpu1.rename.UndoneMaps 1140265 # Number of HB maps that are undone due to squashing
1282 system.cpu1.rename.serializingInsts 506846 # count of serializing insts renamed
1283 system.cpu1.rename.tempSerializingInsts 51390 # count of temporary serializing insts renamed
1284 system.cpu1.rename.skidInsts 2247067 # count of insts added to the skid buffer
1285 system.cpu1.memDep0.insertedLoads 2298271 # Number of loads inserted to the mem dependence unit.
1286 system.cpu1.memDep0.insertedStores 1513317 # Number of stores inserted to the mem dependence unit.
1287 system.cpu1.memDep0.conflictingLoads 213048 # Number of conflicting loads.
1288 system.cpu1.memDep0.conflictingStores 119189 # Number of conflicting stores.
1289 system.cpu1.iq.iqInstsAdded 11099753 # Number of instructions added to the IQ (excludes non-spec)
1290 system.cpu1.iq.iqNonSpecInstsAdded 565057 # Number of non-speculative instructions added to the IQ
1291 system.cpu1.iq.iqInstsIssued 10829119 # Number of instructions issued
1292 system.cpu1.iq.iqSquashedInstsIssued 31632 # Number of squashed instructions issued
1293 system.cpu1.iq.iqSquashedInstsExamined 1536258 # Number of squashed instructions iterated over during squash; mainly for profiling
1294 system.cpu1.iq.iqSquashedOperandsExamined 758334 # Number of squashed operands that are examined and possibly removed from graph
1295 system.cpu1.iq.iqSquashedNonSpecRemoved 401417 # Number of squashed non-spec instructions that were removed
1296 system.cpu1.iq.issued_per_cycle::samples 17001992 # Number of insts issued each cycle
1297 system.cpu1.iq.issued_per_cycle::mean 0.636932 # Number of insts issued each cycle
1298 system.cpu1.iq.issued_per_cycle::stdev 1.310611 # Number of insts issued each cycle
1299 system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1300 system.cpu1.iq.issued_per_cycle::0 12225446 71.91% 71.91% # Number of insts issued each cycle
1301 system.cpu1.iq.issued_per_cycle::1 2205450 12.97% 84.88% # Number of insts issued each cycle
1302 system.cpu1.iq.issued_per_cycle::2 929224 5.47% 90.34% # Number of insts issued each cycle
1303 system.cpu1.iq.issued_per_cycle::3 621702 3.66% 94.00% # Number of insts issued each cycle
1304 system.cpu1.iq.issued_per_cycle::4 537509 3.16% 97.16% # Number of insts issued each cycle
1305 system.cpu1.iq.issued_per_cycle::5 242497 1.43% 98.59% # Number of insts issued each cycle
1306 system.cpu1.iq.issued_per_cycle::6 153407 0.90% 99.49% # Number of insts issued each cycle
1307 system.cpu1.iq.issued_per_cycle::7 76904 0.45% 99.94% # Number of insts issued each cycle
1308 system.cpu1.iq.issued_per_cycle::8 9853 0.06% 100.00% # Number of insts issued each cycle
1309 system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1310 system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1311 system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1312 system.cpu1.iq.issued_per_cycle::total 17001992 # Number of insts issued each cycle
1313 system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1314 system.cpu1.iq.fu_full::IntAlu 3913 1.80% 1.80% # attempts to use FU when none available
1315 system.cpu1.iq.fu_full::IntMult 0 0.00% 1.80% # attempts to use FU when none available
1316 system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.80% # attempts to use FU when none available
1317 system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.80% # attempts to use FU when none available
1318 system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.80% # attempts to use FU when none available
1319 system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.80% # attempts to use FU when none available
1320 system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.80% # attempts to use FU when none available
1321 system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.80% # attempts to use FU when none available
1322 system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
1323 system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.80% # attempts to use FU when none available
1324 system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.80% # attempts to use FU when none available
1325 system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.80% # attempts to use FU when none available
1326 system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.80% # attempts to use FU when none available
1327 system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.80% # attempts to use FU when none available
1328 system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.80% # attempts to use FU when none available
1329 system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.80% # attempts to use FU when none available
1330 system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.80% # attempts to use FU when none available
1331 system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.80% # attempts to use FU when none available
1332 system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.80% # attempts to use FU when none available
1333 system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.80% # attempts to use FU when none available
1334 system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.80% # attempts to use FU when none available
1335 system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.80% # attempts to use FU when none available
1336 system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.80% # attempts to use FU when none available
1337 system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.80% # attempts to use FU when none available
1338 system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.80% # attempts to use FU when none available
1339 system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.80% # attempts to use FU when none available
1340 system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.80% # attempts to use FU when none available
1341 system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.80% # attempts to use FU when none available
1342 system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
1343 system.cpu1.iq.fu_full::MemRead 115549 53.23% 55.03% # attempts to use FU when none available
1344 system.cpu1.iq.fu_full::MemWrite 97618 44.97% 100.00% # attempts to use FU when none available
1345 system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1346 system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1347 system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued
1348 system.cpu1.iq.FU_type_0::IntAlu 6756968 62.40% 62.43% # Type of FU issued
1349 system.cpu1.iq.FU_type_0::IntMult 17928 0.17% 62.59% # Type of FU issued
1350 system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
1351 system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.70% # Type of FU issued
1352 system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued
1353 system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued
1354 system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued
1355 system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued
1356 system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued
1357 system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued
1358 system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued
1359 system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued
1360 system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued
1361 system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued
1362 system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued
1363 system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.72% # Type of FU issued
1364 system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.72% # Type of FU issued
1365 system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.72% # Type of FU issued
1366 system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.72% # Type of FU issued
1367 system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.72% # Type of FU issued
1368 system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.72% # Type of FU issued
1369 system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued
1370 system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued
1371 system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued
1372 system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued
1373 system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued
1374 system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
1375 system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
1376 system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
1377 system.cpu1.iq.FU_type_0::MemRead 2278200 21.04% 83.75% # Type of FU issued
1378 system.cpu1.iq.FU_type_0::MemWrite 1457808 13.46% 97.22% # Type of FU issued
1379 system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued
1380 system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1381 system.cpu1.iq.FU_type_0::total 10829119 # Type of FU issued
1382 system.cpu1.iq.rate 0.596884 # Inst issue rate
1383 system.cpu1.iq.fu_busy_cnt 217080 # FU busy when requested
1384 system.cpu1.iq.fu_busy_rate 0.020046 # FU busy rate (busy events/executed inst)
1385 system.cpu1.iq.int_inst_queue_reads 38657394 # Number of integer instruction queue reads
1386 system.cpu1.iq.int_inst_queue_writes 13080099 # Number of integer instruction queue writes
1387 system.cpu1.iq.int_inst_queue_wakeup_accesses 10523969 # Number of integer instruction queue wakeup accesses
1388 system.cpu1.iq.fp_inst_queue_reads 251548 # Number of floating instruction queue reads
1389 system.cpu1.iq.fp_inst_queue_writes 122819 # Number of floating instruction queue writes
1390 system.cpu1.iq.fp_inst_queue_wakeup_accesses 119141 # Number of floating instruction queue wakeup accesses
1391 system.cpu1.iq.int_alu_accesses 10911695 # Number of integer alu accesses
1392 system.cpu1.iq.fp_alu_accesses 130978 # Number of floating point alu accesses
1393 system.cpu1.iew.lsq.thread0.forwLoads 103489 # Number of loads that had data forwarded from stores
1394 system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1395 system.cpu1.iew.lsq.thread0.squashedLoads 301882 # Number of loads squashed
1396 system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed
1397 system.cpu1.iew.lsq.thread0.memOrderViolation 1924 # Number of memory ordering violations
1398 system.cpu1.iew.lsq.thread0.squashedStores 130297 # Number of stores squashed
1399 system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1400 system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1401 system.cpu1.iew.lsq.thread0.rescheduledLoads 383 # Number of loads that were rescheduled
1402 system.cpu1.iew.lsq.thread0.cacheBlocked 9692 # Number of times an access to memory failed due to the cache being blocked
1403 system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1404 system.cpu1.iew.iewSquashCycles 268198 # Number of cycles IEW is squashing
1405 system.cpu1.iew.iewBlockCycles 347966 # Number of cycles IEW is blocking
1406 system.cpu1.iew.iewUnblockCycles 52179 # Number of cycles IEW is unblocking
1407 system.cpu1.iew.iewDispatchedInsts 12265641 # Number of instructions dispatched to IQ
1408 system.cpu1.iew.iewDispSquashedInsts 165598 # Number of squashed instructions skipped by dispatch
1409 system.cpu1.iew.iewDispLoadInsts 2298271 # Number of dispatched load instructions
1410 system.cpu1.iew.iewDispStoreInsts 1513317 # Number of dispatched store instructions
1411 system.cpu1.iew.iewDispNonSpecInsts 508976 # Number of dispatched non-speculative instructions
1412 system.cpu1.iew.iewIQFullEvents 44383 # Number of times the IQ has become full, causing a stall
1413 system.cpu1.iew.iewLSQFullEvents 2331 # Number of times the LSQ has become full, causing a stall
1414 system.cpu1.iew.memOrderViolationEvents 1924 # Number of memory order violations
1415 system.cpu1.iew.predictedTakenIncorrect 37819 # Number of branches that were predicted taken incorrectly
1416 system.cpu1.iew.predictedNotTakenIncorrect 111790 # Number of branches that were predicted not taken incorrectly
1417 system.cpu1.iew.branchMispredicts 149609 # Number of branch mispredicts detected at execute
1418 system.cpu1.iew.iewExecutedInsts 10726333 # Number of executed instructions
1419 system.cpu1.iew.iewExecLoadInsts 2195343 # Number of load instructions executed
1420 system.cpu1.iew.iewExecSquashedInsts 102786 # Number of squashed instructions skipped in execute
1421 system.cpu1.iew.exec_swp 0 # number of swp insts executed
1422 system.cpu1.iew.exec_nop 600831 # number of nop insts executed
1423 system.cpu1.iew.exec_refs 3637407 # number of memory reference insts executed
1424 system.cpu1.iew.exec_branches 1609945 # Number of branches executed
1425 system.cpu1.iew.exec_stores 1442064 # Number of stores executed
1426 system.cpu1.iew.exec_rate 0.591218 # Inst execution rate
1427 system.cpu1.iew.wb_sent 10671459 # cumulative count of insts sent to commit
1428 system.cpu1.iew.wb_count 10643110 # cumulative count of insts written-back
1429 system.cpu1.iew.wb_producers 4954176 # num instructions producing a value
1430 system.cpu1.iew.wb_consumers 6965889 # num instructions consuming a value
1431 system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1432 system.cpu1.iew.wb_rate 0.586631 # insts written-back per cycle
1433 system.cpu1.iew.wb_fanout 0.711205 # average fanout of values written-back
1434 system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1435 system.cpu1.commit.commitSquashedInsts 1581528 # The number of squashed insts skipped by commit
1436 system.cpu1.commit.commitNonSpecStalls 163640 # The number of times commit has been forced to stall to communicate backwards
1437 system.cpu1.commit.branchMispredicts 139954 # The number of times a branch was mispredicted
1438 system.cpu1.commit.committed_per_cycle::samples 16733794 # Number of insts commited each cycle
1439 system.cpu1.commit.committed_per_cycle::mean 0.633013 # Number of insts commited each cycle
1440 system.cpu1.commit.committed_per_cycle::stdev 1.579692 # Number of insts commited each cycle
1441 system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1442 system.cpu1.commit.committed_per_cycle::0 12789139 76.43% 76.43% # Number of insts commited each cycle
1443 system.cpu1.commit.committed_per_cycle::1 1829893 10.94% 87.36% # Number of insts commited each cycle
1444 system.cpu1.commit.committed_per_cycle::2 688745 4.12% 91.48% # Number of insts commited each cycle
1445 system.cpu1.commit.committed_per_cycle::3 420012 2.51% 93.99% # Number of insts commited each cycle
1446 system.cpu1.commit.committed_per_cycle::4 300647 1.80% 95.78% # Number of insts commited each cycle
1447 system.cpu1.commit.committed_per_cycle::5 117990 0.71% 96.49% # Number of insts commited each cycle
1448 system.cpu1.commit.committed_per_cycle::6 119790 0.72% 97.21% # Number of insts commited each cycle
1449 system.cpu1.commit.committed_per_cycle::7 126616 0.76% 97.96% # Number of insts commited each cycle
1450 system.cpu1.commit.committed_per_cycle::8 340962 2.04% 100.00% # Number of insts commited each cycle
1451 system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1452 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1453 system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1454 system.cpu1.commit.committed_per_cycle::total 16733794 # Number of insts commited each cycle
1455 system.cpu1.commit.committedInsts 10592705 # Number of instructions committed
1456 system.cpu1.commit.committedOps 10592705 # Number of ops (including micro ops) committed
1457 system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1458 system.cpu1.commit.refs 3379409 # Number of memory references committed
1459 system.cpu1.commit.loads 1996389 # Number of loads committed
1460 system.cpu1.commit.membars 53397 # Number of memory barriers committed
1461 system.cpu1.commit.branches 1516939 # Number of branches committed
1462 system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions.
1463 system.cpu1.commit.int_insts 9798676 # Number of committed integer instructions.
1464 system.cpu1.commit.function_calls 169964 # Number of function calls committed.
1465 system.cpu1.commit.bw_lim_events 340962 # number cycles where commit BW limit reached
1466 system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1467 system.cpu1.rob.rob_reads 28474562 # The number of ROB reads
1468 system.cpu1.rob.rob_writes 24615096 # The number of ROB writes
1469 system.cpu1.timesIdled 153586 # Number of times that the entire CPU went into an idle state and unscheduled itself
1470 system.cpu1.idleCycles 1140771 # Total number of cycles that the CPU has spent unscheduled due to idling
1471 system.cpu1.quiesceCycles 3782727730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1472 system.cpu1.committedInsts 10062016 # Number of Instructions Simulated
1473 system.cpu1.committedOps 10062016 # Number of Ops (including micro ops) Simulated
1474 system.cpu1.committedInsts_total 10062016 # Number of Instructions Simulated
1475 system.cpu1.cpi 1.803094 # CPI: Cycles Per Instruction
1476 system.cpu1.cpi_total 1.803094 # CPI: Total CPI of All Threads
1477 system.cpu1.ipc 0.554602 # IPC: Instructions Per Cycle
1478 system.cpu1.ipc_total 0.554602 # IPC: Total IPC of All Threads
1479 system.cpu1.int_regfile_reads 13798564 # number of integer regfile reads
1480 system.cpu1.int_regfile_writes 7546386 # number of integer regfile writes
1481 system.cpu1.fp_regfile_reads 63884 # number of floating regfile reads
1482 system.cpu1.fp_regfile_writes 63971 # number of floating regfile writes
1483 system.cpu1.misc_regfile_reads 608483 # number of misc regfile reads
1484 system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes
1485 system.cpu1.icache.replacements 263412 # number of replacements
1486 system.cpu1.icache.tagsinuse 470.047023 # Cycle average of tags in use
1487 system.cpu1.icache.total_refs 1392951 # Total number of references to valid blocks.
1488 system.cpu1.icache.sampled_refs 263924 # Sample count of references to valid blocks.
1489 system.cpu1.icache.avg_refs 5.277849 # Average number of references to valid blocks.
1490 system.cpu1.icache.warmup_cycle 1875177958000 # Cycle when the warmup percentage was hit.
1491 system.cpu1.icache.occ_blocks::cpu1.inst 470.047023 # Average occupied blocks per requestor
1492 system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy
1493 system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy
1494 system.cpu1.icache.ReadReq_hits::cpu1.inst 1392951 # number of ReadReq hits
1495 system.cpu1.icache.ReadReq_hits::total 1392951 # number of ReadReq hits
1496 system.cpu1.icache.demand_hits::cpu1.inst 1392951 # number of demand (read+write) hits
1497 system.cpu1.icache.demand_hits::total 1392951 # number of demand (read+write) hits
1498 system.cpu1.icache.overall_hits::cpu1.inst 1392951 # number of overall hits
1499 system.cpu1.icache.overall_hits::total 1392951 # number of overall hits
1500 system.cpu1.icache.ReadReq_misses::cpu1.inst 273139 # number of ReadReq misses
1501 system.cpu1.icache.ReadReq_misses::total 273139 # number of ReadReq misses
1502 system.cpu1.icache.demand_misses::cpu1.inst 273139 # number of demand (read+write) misses
1503 system.cpu1.icache.demand_misses::total 273139 # number of demand (read+write) misses
1504 system.cpu1.icache.overall_misses::cpu1.inst 273139 # number of overall misses
1505 system.cpu1.icache.overall_misses::total 273139 # number of overall misses
1506 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3753112000 # number of ReadReq miss cycles
1507 system.cpu1.icache.ReadReq_miss_latency::total 3753112000 # number of ReadReq miss cycles
1508 system.cpu1.icache.demand_miss_latency::cpu1.inst 3753112000 # number of demand (read+write) miss cycles
1509 system.cpu1.icache.demand_miss_latency::total 3753112000 # number of demand (read+write) miss cycles
1510 system.cpu1.icache.overall_miss_latency::cpu1.inst 3753112000 # number of overall miss cycles
1511 system.cpu1.icache.overall_miss_latency::total 3753112000 # number of overall miss cycles
1512 system.cpu1.icache.ReadReq_accesses::cpu1.inst 1666090 # number of ReadReq accesses(hits+misses)
1513 system.cpu1.icache.ReadReq_accesses::total 1666090 # number of ReadReq accesses(hits+misses)
1514 system.cpu1.icache.demand_accesses::cpu1.inst 1666090 # number of demand (read+write) accesses
1515 system.cpu1.icache.demand_accesses::total 1666090 # number of demand (read+write) accesses
1516 system.cpu1.icache.overall_accesses::cpu1.inst 1666090 # number of overall (read+write) accesses
1517 system.cpu1.icache.overall_accesses::total 1666090 # number of overall (read+write) accesses
1518 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163940 # miss rate for ReadReq accesses
1519 system.cpu1.icache.ReadReq_miss_rate::total 0.163940 # miss rate for ReadReq accesses
1520 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163940 # miss rate for demand accesses
1521 system.cpu1.icache.demand_miss_rate::total 0.163940 # miss rate for demand accesses
1522 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163940 # miss rate for overall accesses
1523 system.cpu1.icache.overall_miss_rate::total 0.163940 # miss rate for overall accesses
1524 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13740.666840 # average ReadReq miss latency
1525 system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840 # average ReadReq miss latency
1526 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency
1527 system.cpu1.icache.demand_avg_miss_latency::total 13740.666840 # average overall miss latency
1528 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency
1529 system.cpu1.icache.overall_avg_miss_latency::total 13740.666840 # average overall miss latency
1530 system.cpu1.icache.blocked_cycles::no_mshrs 264 # number of cycles access was blocked
1531 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1532 system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked
1533 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1534 system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.666667 # average number of cycles each access was blocked
1535 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1536 system.cpu1.icache.fast_writes 0 # number of fast writes performed
1537 system.cpu1.icache.cache_copies 0 # number of cache copies performed
1538 system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9144 # number of ReadReq MSHR hits
1539 system.cpu1.icache.ReadReq_mshr_hits::total 9144 # number of ReadReq MSHR hits
1540 system.cpu1.icache.demand_mshr_hits::cpu1.inst 9144 # number of demand (read+write) MSHR hits
1541 system.cpu1.icache.demand_mshr_hits::total 9144 # number of demand (read+write) MSHR hits
1542 system.cpu1.icache.overall_mshr_hits::cpu1.inst 9144 # number of overall MSHR hits
1543 system.cpu1.icache.overall_mshr_hits::total 9144 # number of overall MSHR hits
1544 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 263995 # number of ReadReq MSHR misses
1545 system.cpu1.icache.ReadReq_mshr_misses::total 263995 # number of ReadReq MSHR misses
1546 system.cpu1.icache.demand_mshr_misses::cpu1.inst 263995 # number of demand (read+write) MSHR misses
1547 system.cpu1.icache.demand_mshr_misses::total 263995 # number of demand (read+write) MSHR misses
1548 system.cpu1.icache.overall_mshr_misses::cpu1.inst 263995 # number of overall MSHR misses
1549 system.cpu1.icache.overall_mshr_misses::total 263995 # number of overall MSHR misses
1550 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3126547000 # number of ReadReq MSHR miss cycles
1551 system.cpu1.icache.ReadReq_mshr_miss_latency::total 3126547000 # number of ReadReq MSHR miss cycles
1552 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3126547000 # number of demand (read+write) MSHR miss cycles
1553 system.cpu1.icache.demand_mshr_miss_latency::total 3126547000 # number of demand (read+write) MSHR miss cycles
1554 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3126547000 # number of overall MSHR miss cycles
1555 system.cpu1.icache.overall_mshr_miss_latency::total 3126547000 # number of overall MSHR miss cycles
1556 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for ReadReq accesses
1557 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158452 # mshr miss rate for ReadReq accesses
1558 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for demand accesses
1559 system.cpu1.icache.demand_mshr_miss_rate::total 0.158452 # mshr miss rate for demand accesses
1560 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for overall accesses
1561 system.cpu1.icache.overall_mshr_miss_rate::total 0.158452 # mshr miss rate for overall accesses
1562 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average ReadReq mshr miss latency
1563 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364 # average ReadReq mshr miss latency
1564 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
1565 system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
1566 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
1567 system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
1568 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1569 system.cpu1.dcache.replacements 126526 # number of replacements
1570 system.cpu1.dcache.tagsinuse 490.827782 # Cycle average of tags in use
1571 system.cpu1.dcache.total_refs 2952051 # Total number of references to valid blocks.
1572 system.cpu1.dcache.sampled_refs 126931 # Sample count of references to valid blocks.
1573 system.cpu1.dcache.avg_refs 23.257132 # Average number of references to valid blocks.
1574 system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit.
1575 system.cpu1.dcache.occ_blocks::cpu1.data 490.827782 # Average occupied blocks per requestor
1576 system.cpu1.dcache.occ_percent::cpu1.data 0.958648 # Average percentage of cache occupancy
1577 system.cpu1.dcache.occ_percent::total 0.958648 # Average percentage of cache occupancy
1578 system.cpu1.dcache.ReadReq_hits::cpu1.data 1783702 # number of ReadReq hits
1579 system.cpu1.dcache.ReadReq_hits::total 1783702 # number of ReadReq hits
1580 system.cpu1.dcache.WriteReq_hits::cpu1.data 1082593 # number of WriteReq hits
1581 system.cpu1.dcache.WriteReq_hits::total 1082593 # number of WriteReq hits
1582 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39936 # number of LoadLockedReq hits
1583 system.cpu1.dcache.LoadLockedReq_hits::total 39936 # number of LoadLockedReq hits
1584 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38619 # number of StoreCondReq hits
1585 system.cpu1.dcache.StoreCondReq_hits::total 38619 # number of StoreCondReq hits
1586 system.cpu1.dcache.demand_hits::cpu1.data 2866295 # number of demand (read+write) hits
1587 system.cpu1.dcache.demand_hits::total 2866295 # number of demand (read+write) hits
1588 system.cpu1.dcache.overall_hits::cpu1.data 2866295 # number of overall hits
1589 system.cpu1.dcache.overall_hits::total 2866295 # number of overall hits
1590 system.cpu1.dcache.ReadReq_misses::cpu1.data 242985 # number of ReadReq misses
1591 system.cpu1.dcache.ReadReq_misses::total 242985 # number of ReadReq misses
1592 system.cpu1.dcache.WriteReq_misses::cpu1.data 251423 # number of WriteReq misses
1593 system.cpu1.dcache.WriteReq_misses::total 251423 # number of WriteReq misses
1594 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6626 # number of LoadLockedReq misses
1595 system.cpu1.dcache.LoadLockedReq_misses::total 6626 # number of LoadLockedReq misses
1596 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3957 # number of StoreCondReq misses
1597 system.cpu1.dcache.StoreCondReq_misses::total 3957 # number of StoreCondReq misses
1598 system.cpu1.dcache.demand_misses::cpu1.data 494408 # number of demand (read+write) misses
1599 system.cpu1.dcache.demand_misses::total 494408 # number of demand (read+write) misses
1600 system.cpu1.dcache.overall_misses::cpu1.data 494408 # number of overall misses
1601 system.cpu1.dcache.overall_misses::total 494408 # number of overall misses
1602 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3665622000 # number of ReadReq miss cycles
1603 system.cpu1.dcache.ReadReq_miss_latency::total 3665622000 # number of ReadReq miss cycles
1604 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8223225631 # number of WriteReq miss cycles
1605 system.cpu1.dcache.WriteReq_miss_latency::total 8223225631 # number of WriteReq miss cycles
1606 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67675500 # number of LoadLockedReq miss cycles
1607 system.cpu1.dcache.LoadLockedReq_miss_latency::total 67675500 # number of LoadLockedReq miss cycles
1608 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29039500 # number of StoreCondReq miss cycles
1609 system.cpu1.dcache.StoreCondReq_miss_latency::total 29039500 # number of StoreCondReq miss cycles
1610 system.cpu1.dcache.demand_miss_latency::cpu1.data 11888847631 # number of demand (read+write) miss cycles
1611 system.cpu1.dcache.demand_miss_latency::total 11888847631 # number of demand (read+write) miss cycles
1612 system.cpu1.dcache.overall_miss_latency::cpu1.data 11888847631 # number of overall miss cycles
1613 system.cpu1.dcache.overall_miss_latency::total 11888847631 # number of overall miss cycles
1614 system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026687 # number of ReadReq accesses(hits+misses)
1615 system.cpu1.dcache.ReadReq_accesses::total 2026687 # number of ReadReq accesses(hits+misses)
1616 system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses)
1617 system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses)
1618 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46562 # number of LoadLockedReq accesses(hits+misses)
1619 system.cpu1.dcache.LoadLockedReq_accesses::total 46562 # number of LoadLockedReq accesses(hits+misses)
1620 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42576 # number of StoreCondReq accesses(hits+misses)
1621 system.cpu1.dcache.StoreCondReq_accesses::total 42576 # number of StoreCondReq accesses(hits+misses)
1622 system.cpu1.dcache.demand_accesses::cpu1.data 3360703 # number of demand (read+write) accesses
1623 system.cpu1.dcache.demand_accesses::total 3360703 # number of demand (read+write) accesses
1624 system.cpu1.dcache.overall_accesses::cpu1.data 3360703 # number of overall (read+write) accesses
1625 system.cpu1.dcache.overall_accesses::total 3360703 # number of overall (read+write) accesses
1626 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119893 # miss rate for ReadReq accesses
1627 system.cpu1.dcache.ReadReq_miss_rate::total 0.119893 # miss rate for ReadReq accesses
1628 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188471 # miss rate for WriteReq accesses
1629 system.cpu1.dcache.WriteReq_miss_rate::total 0.188471 # miss rate for WriteReq accesses
1630 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142305 # miss rate for LoadLockedReq accesses
1631 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142305 # miss rate for LoadLockedReq accesses
1632 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092940 # miss rate for StoreCondReq accesses
1633 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092940 # miss rate for StoreCondReq accesses
1634 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147114 # miss rate for demand accesses
1635 system.cpu1.dcache.demand_miss_rate::total 0.147114 # miss rate for demand accesses
1636 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147114 # miss rate for overall accesses
1637 system.cpu1.dcache.overall_miss_rate::total 0.147114 # miss rate for overall accesses
1638 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15085.795419 # average ReadReq miss latency
1639 system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419 # average ReadReq miss latency
1640 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32706.735784 # average WriteReq miss latency
1641 system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784 # average WriteReq miss latency
1642 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10213.628132 # average LoadLockedReq miss latency
1643 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132 # average LoadLockedReq miss latency
1644 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7338.766742 # average StoreCondReq miss latency
1645 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7338.766742 # average StoreCondReq miss latency
1646 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
1647 system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803 # average overall miss latency
1648 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
1649 system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803 # average overall miss latency
1650 system.cpu1.dcache.blocked_cycles::no_mshrs 255815 # number of cycles access was blocked
1651 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1652 system.cpu1.dcache.blocked::no_mshrs 3992 # number of cycles access was blocked
1653 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1654 system.cpu1.dcache.avg_blocked_cycles::no_mshrs 64.081914 # average number of cycles each access was blocked
1655 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1656 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1657 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1658 system.cpu1.dcache.writebacks::writebacks 84886 # number of writebacks
1659 system.cpu1.dcache.writebacks::total 84886 # number of writebacks
1660 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150812 # number of ReadReq MSHR hits
1661 system.cpu1.dcache.ReadReq_mshr_hits::total 150812 # number of ReadReq MSHR hits
1662 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205594 # number of WriteReq MSHR hits
1663 system.cpu1.dcache.WriteReq_mshr_hits::total 205594 # number of WriteReq MSHR hits
1664 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 644 # number of LoadLockedReq MSHR hits
1665 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 644 # number of LoadLockedReq MSHR hits
1666 system.cpu1.dcache.demand_mshr_hits::cpu1.data 356406 # number of demand (read+write) MSHR hits
1667 system.cpu1.dcache.demand_mshr_hits::total 356406 # number of demand (read+write) MSHR hits
1668 system.cpu1.dcache.overall_mshr_hits::cpu1.data 356406 # number of overall MSHR hits
1669 system.cpu1.dcache.overall_mshr_hits::total 356406 # number of overall MSHR hits
1670 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92173 # number of ReadReq MSHR misses
1671 system.cpu1.dcache.ReadReq_mshr_misses::total 92173 # number of ReadReq MSHR misses
1672 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45829 # number of WriteReq MSHR misses
1673 system.cpu1.dcache.WriteReq_mshr_misses::total 45829 # number of WriteReq MSHR misses
1674 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5982 # number of LoadLockedReq MSHR misses
1675 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5982 # number of LoadLockedReq MSHR misses
1676 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3957 # number of StoreCondReq MSHR misses
1677 system.cpu1.dcache.StoreCondReq_mshr_misses::total 3957 # number of StoreCondReq MSHR misses
1678 system.cpu1.dcache.demand_mshr_misses::cpu1.data 138002 # number of demand (read+write) MSHR misses
1679 system.cpu1.dcache.demand_mshr_misses::total 138002 # number of demand (read+write) MSHR misses
1680 system.cpu1.dcache.overall_mshr_misses::cpu1.data 138002 # number of overall MSHR misses
1681 system.cpu1.dcache.overall_mshr_misses::total 138002 # number of overall MSHR misses
1682 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1122474000 # number of ReadReq MSHR miss cycles
1683 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1122474000 # number of ReadReq MSHR miss cycles
1684 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1228877987 # number of WriteReq MSHR miss cycles
1685 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1228877987 # number of WriteReq MSHR miss cycles
1686 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47579000 # number of LoadLockedReq MSHR miss cycles
1687 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47579000 # number of LoadLockedReq MSHR miss cycles
1688 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21125500 # number of StoreCondReq MSHR miss cycles
1689 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21125500 # number of StoreCondReq MSHR miss cycles
1690 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2351351987 # number of demand (read+write) MSHR miss cycles
1691 system.cpu1.dcache.demand_mshr_miss_latency::total 2351351987 # number of demand (read+write) MSHR miss cycles
1692 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2351351987 # number of overall MSHR miss cycles
1693 system.cpu1.dcache.overall_mshr_miss_latency::total 2351351987 # number of overall MSHR miss cycles
1694 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30976000 # number of ReadReq MSHR uncacheable cycles
1695 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30976000 # number of ReadReq MSHR uncacheable cycles
1696 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675219000 # number of WriteReq MSHR uncacheable cycles
1697 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675219000 # number of WriteReq MSHR uncacheable cycles
1698 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706195000 # number of overall MSHR uncacheable cycles
1699 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706195000 # number of overall MSHR uncacheable cycles
1700 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045480 # mshr miss rate for ReadReq accesses
1701 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045480 # mshr miss rate for ReadReq accesses
1702 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034354 # mshr miss rate for WriteReq accesses
1703 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034354 # mshr miss rate for WriteReq accesses
1704 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128474 # mshr miss rate for LoadLockedReq accesses
1705 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128474 # mshr miss rate for LoadLockedReq accesses
1706 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092940 # mshr miss rate for StoreCondReq accesses
1707 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092940 # mshr miss rate for StoreCondReq accesses
1708 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for demand accesses
1709 system.cpu1.dcache.demand_mshr_miss_rate::total 0.041063 # mshr miss rate for demand accesses
1710 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for overall accesses
1711 system.cpu1.dcache.overall_mshr_miss_rate::total 0.041063 # mshr miss rate for overall accesses
1712 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592 # average ReadReq mshr miss latency
1713 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592 # average ReadReq mshr miss latency
1714 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534 # average WriteReq mshr miss latency
1715 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534 # average WriteReq mshr miss latency
1716 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7953.694417 # average LoadLockedReq mshr miss latency
1717 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7953.694417 # average LoadLockedReq mshr miss latency
1718 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5338.766742 # average StoreCondReq mshr miss latency
1719 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5338.766742 # average StoreCondReq mshr miss latency
1720 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
1721 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
1722 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
1723 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
1724 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1725 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1726 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1727 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1728 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1729 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1730 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1731 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1732 system.cpu0.kern.inst.quiesce 6610 # number of quiesce instructions executed
1733 system.cpu0.kern.inst.hwrei 175912 # number of hwrei instructions executed
1734 system.cpu0.kern.ipl_count::0 61740 40.36% 40.36% # number of times we switched to this ipl
1735 system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl
1736 system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl
1737 system.cpu0.kern.ipl_count::30 255 0.17% 41.88% # number of times we switched to this ipl
1738 system.cpu0.kern.ipl_count::31 88907 58.12% 100.00% # number of times we switched to this ipl
1739 system.cpu0.kern.ipl_count::total 152961 # number of times we switched to this ipl
1740 system.cpu0.kern.ipl_good::0 60876 49.17% 49.17% # number of times we switched to this ipl from a different ipl
1741 system.cpu0.kern.ipl_good::21 131 0.11% 49.27% # number of times we switched to this ipl from a different ipl
1742 system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl
1743 system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl
1744 system.cpu0.kern.ipl_good::31 60621 48.96% 100.00% # number of times we switched to this ipl from a different ipl
1745 system.cpu0.kern.ipl_good::total 123811 # number of times we switched to this ipl from a different ipl
1746 system.cpu0.kern.ipl_ticks::0 1865672058500 98.16% 98.16% # number of cycles we spent at this ipl
1747 system.cpu0.kern.ipl_ticks::21 62377000 0.00% 98.16% # number of cycles we spent at this ipl
1748 system.cpu0.kern.ipl_ticks::22 564179500 0.03% 98.19% # number of cycles we spent at this ipl
1749 system.cpu0.kern.ipl_ticks::30 124028500 0.01% 98.20% # number of cycles we spent at this ipl
1750 system.cpu0.kern.ipl_ticks::31 34304214500 1.80% 100.00% # number of cycles we spent at this ipl
1751 system.cpu0.kern.ipl_ticks::total 1900726858000 # number of cycles we spent at this ipl
1752 system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl
1753 system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
1754 system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1755 system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1756 system.cpu0.kern.ipl_used::31 0.681847 # fraction of swpipl calls that actually changed the ipl
1757 system.cpu0.kern.ipl_used::total 0.809429 # fraction of swpipl calls that actually changed the ipl
1758 system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
1759 system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
1760 system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
1761 system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed
1762 system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed
1763 system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed
1764 system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed
1765 system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed
1766 system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed
1767 system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed
1768 system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed
1769 system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed
1770 system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed
1771 system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed
1772 system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed
1773 system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed
1774 system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed
1775 system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed
1776 system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed
1777 system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed
1778 system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed
1779 system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed
1780 system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed
1781 system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed
1782 system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed
1783 system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed
1784 system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed
1785 system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed
1786 system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
1787 system.cpu0.kern.syscall::total 202 # number of syscalls executed
1788 system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1789 system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed
1790 system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed
1791 system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed
1792 system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed
1793 system.cpu0.kern.callpal::swpctx 3342 2.08% 2.30% # number of callpals executed
1794 system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed
1795 system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed
1796 system.cpu0.kern.callpal::swpipl 146221 90.79% 93.12% # number of callpals executed
1797 system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed
1798 system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed
1799 system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed
1800 system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed
1801 system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
1802 system.cpu0.kern.callpal::rti 4425 2.75% 99.71% # number of callpals executed
1803 system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed
1804 system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
1805 system.cpu0.kern.callpal::total 161059 # number of callpals executed
1806 system.cpu0.kern.mode_switch::kernel 6926 # number of protection mode switches
1807 system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches
1808 system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
1809 system.cpu0.kern.mode_good::kernel 1256
1810 system.cpu0.kern.mode_good::user 1257
1811 system.cpu0.kern.mode_good::idle 0
1812 system.cpu0.kern.mode_switch_good::kernel 0.181346 # fraction of useful protection mode switches
1813 system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1814 system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
1815 system.cpu0.kern.mode_switch_good::total 0.307100 # fraction of useful protection mode switches
1816 system.cpu0.kern.mode_ticks::kernel 1898828643000 99.90% 99.90% # number of ticks spent at the given mode
1817 system.cpu0.kern.mode_ticks::user 1898207000 0.10% 100.00% # number of ticks spent at the given mode
1818 system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
1819 system.cpu0.kern.swap_context 3343 # number of times the context was actually changed
1820 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1821 system.cpu1.kern.inst.quiesce 2523 # number of quiesce instructions executed
1822 system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed
1823 system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl
1824 system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl
1825 system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl
1826 system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl
1827 system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl
1828 system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl
1829 system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl
1830 system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl
1831 system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl
1832 system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl
1833 system.cpu1.kern.ipl_ticks::0 1875010715500 98.66% 98.66% # number of cycles we spent at this ipl
1834 system.cpu1.kern.ipl_ticks::22 532408500 0.03% 98.69% # number of cycles we spent at this ipl
1835 system.cpu1.kern.ipl_ticks::30 162327000 0.01% 98.70% # number of cycles we spent at this ipl
1836 system.cpu1.kern.ipl_ticks::31 24731034000 1.30% 100.00% # number of cycles we spent at this ipl
1837 system.cpu1.kern.ipl_ticks::total 1900436485000 # number of cycles we spent at this ipl
1838 system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl
1839 system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1840 system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1841 system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl
1842 system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl
1843 system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
1844 system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
1845 system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
1846 system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed
1847 system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed
1848 system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed
1849 system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed
1850 system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed
1851 system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed
1852 system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed
1853 system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed
1854 system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed
1855 system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed
1856 system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed
1857 system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed
1858 system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed
1859 system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed
1860 system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed
1861 system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed
1862 system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed
1863 system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
1864 system.cpu1.kern.syscall::total 124 # number of syscalls executed
1865 system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1866 system.cpu1.kern.callpal::wripir 255 0.44% 0.44% # number of callpals executed
1867 system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
1868 system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed
1869 system.cpu1.kern.callpal::swpctx 1393 2.41% 2.86% # number of callpals executed
1870 system.cpu1.kern.callpal::tbi 6 0.01% 2.87% # number of callpals executed
1871 system.cpu1.kern.callpal::wrent 7 0.01% 2.88% # number of callpals executed
1872 system.cpu1.kern.callpal::swpipl 49964 86.52% 89.41% # number of callpals executed
1873 system.cpu1.kern.callpal::rdps 2595 4.49% 93.90% # number of callpals executed
1874 system.cpu1.kern.callpal::wrkgp 1 0.00% 93.90% # number of callpals executed
1875 system.cpu1.kern.callpal::wrusp 4 0.01% 93.91% # number of callpals executed
1876 system.cpu1.kern.callpal::rdusp 1 0.00% 93.91% # number of callpals executed
1877 system.cpu1.kern.callpal::whami 3 0.01% 93.91% # number of callpals executed
1878 system.cpu1.kern.callpal::rti 3286 5.69% 99.61% # number of callpals executed
1879 system.cpu1.kern.callpal::callsys 184 0.32% 99.92% # number of callpals executed
1880 system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed
1881 system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
1882 system.cpu1.kern.callpal::total 57746 # number of callpals executed
1883 system.cpu1.kern.mode_switch::kernel 1619 # number of protection mode switches
1884 system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
1885 system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches
1886 system.cpu1.kern.mode_good::kernel 771
1887 system.cpu1.kern.mode_good::user 488
1888 system.cpu1.kern.mode_good::idle 283
1889 system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches
1890 system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1891 system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches
1892 system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches
1893 system.cpu1.kern.mode_ticks::kernel 5768410500 0.30% 0.30% # number of ticks spent at the given mode
1894 system.cpu1.kern.mode_ticks::user 833727500 0.04% 0.35% # number of ticks spent at the given mode
1895 system.cpu1.kern.mode_ticks::idle 1893823776000 99.65% 100.00% # number of ticks spent at the given mode
1896 system.cpu1.kern.swap_context 1394 # number of times the context was actually changed
1898 ---------- End Simulation Statistics ----------
projects / gem5.git / blob