2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.841723 # Number of seconds simulated
4 sim_ticks 1841722715000 # Number of ticks simulated
5 final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 105391 # Simulator instruction rate (inst/s)
8 host_op_rate 105391 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2775370642 # Simulator tick rate (ticks/s)
10 host_mem_usage 350548 # Number of bytes of host memory used
11 host_seconds 663.60 # Real time elapsed on the host
12 sim_insts 69936964 # Number of instructions simulated
13 sim_ops 69936964 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory
16 system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory
26 system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory
27 system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory
28 system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory
30 system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory
35 system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory
36 system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory
37 system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory
38 system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s)
47 system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s)
48 system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s)
51 system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s)
52 system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s)
56 system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.readReqs 109804 # Total number of read requests seen
62 system.physmem.writeReqs 45341 # Total number of write requests seen
63 system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady
64 system.physmem.bytesRead 7027456 # Total number of bytes read from memory
65 system.physmem.bytesWritten 2901824 # Total number of bytes written to memory
66 system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize()
67 system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize()
68 system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
69 system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed
70 system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis
74 system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis
75 system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis
76 system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis
77 system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis
78 system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis
79 system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis
80 system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis
81 system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis
82 system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis
83 system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis
84 system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis
85 system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis
86 system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::1 2753 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis
90 system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis
91 system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis
92 system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis
93 system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis
94 system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis
95 system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis
96 system.physmem.perBankWrReqs::10 3191 # Track writes on a per bank basis
97 system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis
98 system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis
99 system.physmem.perBankWrReqs::13 2906 # Track writes on a per bank basis
100 system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis
101 system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis
102 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
103 system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
104 system.physmem.totGap 1840710411000 # Total gap between requests
105 system.physmem.readPktSize::0 0 # Categorize read packet sizes
106 system.physmem.readPktSize::1 0 # Categorize read packet sizes
107 system.physmem.readPktSize::2 0 # Categorize read packet sizes
108 system.physmem.readPktSize::3 0 # Categorize read packet sizes
109 system.physmem.readPktSize::4 0 # Categorize read packet sizes
110 system.physmem.readPktSize::5 0 # Categorize read packet sizes
111 system.physmem.readPktSize::6 109804 # Categorize read packet sizes
112 system.physmem.writePktSize::0 0 # Categorize write packet sizes
113 system.physmem.writePktSize::1 0 # Categorize write packet sizes
114 system.physmem.writePktSize::2 0 # Categorize write packet sizes
115 system.physmem.writePktSize::3 0 # Categorize write packet sizes
116 system.physmem.writePktSize::4 0 # Categorize write packet sizes
117 system.physmem.writePktSize::5 0 # Categorize write packet sizes
118 system.physmem.writePktSize::6 45341 # Categorize write packet sizes
119 system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::3 1970 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::4 1274 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::5 1187 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::6 1085 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::7 1083 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::8 1070 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::9 1047 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::10 612 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::11 589 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::12 568 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::13 553 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::14 554 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::15 577 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::16 669 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::18 359 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::19 305 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
151 system.physmem.wrQLenPdf::0 1251 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::1 1428 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::2 1611 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::3 1632 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::4 1823 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::5 1970 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::7 1968 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::8 1964 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::9 1971 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::10 1969 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::12 1963 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::17 1958 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::18 1958 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::19 1955 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::22 1949 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::23 775 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::24 572 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::25 377 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::26 354 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::27 162 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
183 system.physmem.totQLat 2345988500 # Total cycles spent in queuing delays
184 system.physmem.totMemAccLat 4348949750 # Sum of mem lat for all requests
185 system.physmem.totBusLat 548995000 # Total cycles spent in databus access
186 system.physmem.totBankLat 1453966250 # Total cycles spent in bank access
187 system.physmem.avgQLat 21366.21 # Average queueing delay per request
188 system.physmem.avgBankLat 13242.07 # Average bank access latency per request
189 system.physmem.avgBusLat 5000.00 # Average bus latency per request
190 system.physmem.avgMemAccLat 39608.28 # Average memory access latency
191 system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s
192 system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s
193 system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s
194 system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s
195 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
196 system.physmem.busUtil 0.04 # Data bus utilization in percentage
197 system.physmem.avgRdQLen 0.00 # Average read queue length over time
198 system.physmem.avgWrQLen 0.17 # Average write queue length over time
199 system.physmem.readRowHits 99788 # Number of row buffer hits during reads
200 system.physmem.writeRowHits 34189 # Number of row buffer hits during writes
201 system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads
202 system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes
203 system.physmem.avgGap 11864452.04 # Average gap between requests
204 system.l2c.replacements 337462 # number of replacements
205 system.l2c.tagsinuse 65423.385083 # Cycle average of tags in use
206 system.l2c.total_refs 2475374 # Total number of references to valid blocks.
207 system.l2c.sampled_refs 402624 # Sample count of references to valid blocks.
208 system.l2c.avg_refs 6.148103 # Average number of references to valid blocks.
209 system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
210 system.l2c.occ_blocks::writebacks 54864.603018 # Average occupied blocks per requestor
211 system.l2c.occ_blocks::cpu0.inst 2279.979000 # Average occupied blocks per requestor
212 system.l2c.occ_blocks::cpu0.data 2628.690447 # Average occupied blocks per requestor
213 system.l2c.occ_blocks::cpu1.inst 619.088006 # Average occupied blocks per requestor
214 system.l2c.occ_blocks::cpu1.data 659.286821 # Average occupied blocks per requestor
215 system.l2c.occ_blocks::cpu2.inst 2246.098023 # Average occupied blocks per requestor
216 system.l2c.occ_blocks::cpu2.data 2125.639768 # Average occupied blocks per requestor
217 system.l2c.occ_percent::writebacks 0.837167 # Average percentage of cache occupancy
218 system.l2c.occ_percent::cpu0.inst 0.034790 # Average percentage of cache occupancy
219 system.l2c.occ_percent::cpu0.data 0.040111 # Average percentage of cache occupancy
220 system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy
221 system.l2c.occ_percent::cpu1.data 0.010060 # Average percentage of cache occupancy
222 system.l2c.occ_percent::cpu2.inst 0.034273 # Average percentage of cache occupancy
223 system.l2c.occ_percent::cpu2.data 0.032435 # Average percentage of cache occupancy
224 system.l2c.occ_percent::total 0.998282 # Average percentage of cache occupancy
225 system.l2c.ReadReq_hits::cpu0.inst 516841 # number of ReadReq hits
226 system.l2c.ReadReq_hits::cpu0.data 491603 # number of ReadReq hits
227 system.l2c.ReadReq_hits::cpu1.inst 126887 # number of ReadReq hits
228 system.l2c.ReadReq_hits::cpu1.data 83607 # number of ReadReq hits
229 system.l2c.ReadReq_hits::cpu2.inst 295482 # number of ReadReq hits
230 system.l2c.ReadReq_hits::cpu2.data 241937 # number of ReadReq hits
231 system.l2c.ReadReq_hits::total 1756357 # number of ReadReq hits
232 system.l2c.Writeback_hits::writebacks 836151 # number of Writeback hits
233 system.l2c.Writeback_hits::total 836151 # number of Writeback hits
234 system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
235 system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
236 system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
237 system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits
238 system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits
239 system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
240 system.l2c.ReadExReq_hits::cpu0.data 92117 # number of ReadExReq hits
241 system.l2c.ReadExReq_hits::cpu1.data 27417 # number of ReadExReq hits
242 system.l2c.ReadExReq_hits::cpu2.data 67376 # number of ReadExReq hits
243 system.l2c.ReadExReq_hits::total 186910 # number of ReadExReq hits
244 system.l2c.demand_hits::cpu0.inst 516841 # number of demand (read+write) hits
245 system.l2c.demand_hits::cpu0.data 583720 # number of demand (read+write) hits
246 system.l2c.demand_hits::cpu1.inst 126887 # number of demand (read+write) hits
247 system.l2c.demand_hits::cpu1.data 111024 # number of demand (read+write) hits
248 system.l2c.demand_hits::cpu2.inst 295482 # number of demand (read+write) hits
249 system.l2c.demand_hits::cpu2.data 309313 # number of demand (read+write) hits
250 system.l2c.demand_hits::total 1943267 # number of demand (read+write) hits
251 system.l2c.overall_hits::cpu0.inst 516841 # number of overall hits
252 system.l2c.overall_hits::cpu0.data 583720 # number of overall hits
253 system.l2c.overall_hits::cpu1.inst 126887 # number of overall hits
254 system.l2c.overall_hits::cpu1.data 111024 # number of overall hits
255 system.l2c.overall_hits::cpu2.inst 295482 # number of overall hits
256 system.l2c.overall_hits::cpu2.data 309313 # number of overall hits
257 system.l2c.overall_hits::total 1943267 # number of overall hits
258 system.l2c.ReadReq_misses::cpu0.inst 7386 # number of ReadReq misses
259 system.l2c.ReadReq_misses::cpu0.data 225256 # number of ReadReq misses
260 system.l2c.ReadReq_misses::cpu1.inst 2379 # number of ReadReq misses
261 system.l2c.ReadReq_misses::cpu1.data 23009 # number of ReadReq misses
262 system.l2c.ReadReq_misses::cpu2.inst 4597 # number of ReadReq misses
263 system.l2c.ReadReq_misses::cpu2.data 24998 # number of ReadReq misses
264 system.l2c.ReadReq_misses::total 287625 # number of ReadReq misses
265 system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
266 system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses
267 system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses
268 system.l2c.ReadExReq_misses::cpu0.data 77538 # number of ReadExReq misses
269 system.l2c.ReadExReq_misses::cpu1.data 20985 # number of ReadExReq misses
270 system.l2c.ReadExReq_misses::cpu2.data 17224 # number of ReadExReq misses
271 system.l2c.ReadExReq_misses::total 115747 # number of ReadExReq misses
272 system.l2c.demand_misses::cpu0.inst 7386 # number of demand (read+write) misses
273 system.l2c.demand_misses::cpu0.data 302794 # number of demand (read+write) misses
274 system.l2c.demand_misses::cpu1.inst 2379 # number of demand (read+write) misses
275 system.l2c.demand_misses::cpu1.data 43994 # number of demand (read+write) misses
276 system.l2c.demand_misses::cpu2.inst 4597 # number of demand (read+write) misses
277 system.l2c.demand_misses::cpu2.data 42222 # number of demand (read+write) misses
278 system.l2c.demand_misses::total 403372 # number of demand (read+write) misses
279 system.l2c.overall_misses::cpu0.inst 7386 # number of overall misses
280 system.l2c.overall_misses::cpu0.data 302794 # number of overall misses
281 system.l2c.overall_misses::cpu1.inst 2379 # number of overall misses
282 system.l2c.overall_misses::cpu1.data 43994 # number of overall misses
283 system.l2c.overall_misses::cpu2.inst 4597 # number of overall misses
284 system.l2c.overall_misses::cpu2.data 42222 # number of overall misses
285 system.l2c.overall_misses::total 403372 # number of overall misses
286 system.l2c.ReadReq_miss_latency::cpu1.inst 156027500 # number of ReadReq miss cycles
287 system.l2c.ReadReq_miss_latency::cpu1.data 1047000000 # number of ReadReq miss cycles
288 system.l2c.ReadReq_miss_latency::cpu2.inst 315202000 # number of ReadReq miss cycles
289 system.l2c.ReadReq_miss_latency::cpu2.data 1118067500 # number of ReadReq miss cycles
290 system.l2c.ReadReq_miss_latency::total 2636297000 # number of ReadReq miss cycles
291 system.l2c.UpgradeReq_miss_latency::cpu2.data 291000 # number of UpgradeReq miss cycles
292 system.l2c.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles
293 system.l2c.ReadExReq_miss_latency::cpu1.data 973607000 # number of ReadExReq miss cycles
294 system.l2c.ReadExReq_miss_latency::cpu2.data 1279851000 # number of ReadExReq miss cycles
295 system.l2c.ReadExReq_miss_latency::total 2253458000 # number of ReadExReq miss cycles
296 system.l2c.demand_miss_latency::cpu1.inst 156027500 # number of demand (read+write) miss cycles
297 system.l2c.demand_miss_latency::cpu1.data 2020607000 # number of demand (read+write) miss cycles
298 system.l2c.demand_miss_latency::cpu2.inst 315202000 # number of demand (read+write) miss cycles
299 system.l2c.demand_miss_latency::cpu2.data 2397918500 # number of demand (read+write) miss cycles
300 system.l2c.demand_miss_latency::total 4889755000 # number of demand (read+write) miss cycles
301 system.l2c.overall_miss_latency::cpu1.inst 156027500 # number of overall miss cycles
302 system.l2c.overall_miss_latency::cpu1.data 2020607000 # number of overall miss cycles
303 system.l2c.overall_miss_latency::cpu2.inst 315202000 # number of overall miss cycles
304 system.l2c.overall_miss_latency::cpu2.data 2397918500 # number of overall miss cycles
305 system.l2c.overall_miss_latency::total 4889755000 # number of overall miss cycles
306 system.l2c.ReadReq_accesses::cpu0.inst 524227 # number of ReadReq accesses(hits+misses)
307 system.l2c.ReadReq_accesses::cpu0.data 716859 # number of ReadReq accesses(hits+misses)
308 system.l2c.ReadReq_accesses::cpu1.inst 129266 # number of ReadReq accesses(hits+misses)
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392 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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396 system.l2c.writebacks::total 75151 # number of writebacks
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469 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32592.129570 # average ReadReq mshr miss latency
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471 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23000.750000 # average UpgradeReq mshr miss latency
472 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23000.750000 # average UpgradeReq mshr miss latency
473 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34049.641315 # average ReadExReq mshr miss latency
474 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62101.622678 # average ReadExReq mshr miss latency
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479 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency
480 system.l2c.demand_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency
481 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average overall mshr miss latency
482 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33606.433946 # average overall mshr miss latency
483 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average overall mshr miss latency
484 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency
485 system.l2c.overall_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency
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487 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
488 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
489 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
490 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
491 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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493 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
494 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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496 system.iocache.replacements 41685 # number of replacements
497 system.iocache.tagsinuse 1.255752 # Cycle average of tags in use
498 system.iocache.total_refs 0 # Total number of references to valid blocks.
499 system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
500 system.iocache.avg_refs 0 # Average number of references to valid blocks.
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502 system.iocache.occ_blocks::tsunami.ide 1.255752 # Average occupied blocks per requestor
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506 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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516 system.iocache.WriteReq_miss_latency::total 4282592586 # number of WriteReq miss cycles
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530 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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532 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
533 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
534 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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536 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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538 system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency
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543 system.iocache.overall_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency
544 system.iocache.overall_avg_miss_latency::total 102858.492127 # average overall miss latency
545 system.iocache.blocked_cycles::no_mshrs 114365 # number of cycles access was blocked
546 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
547 system.iocache.blocked::no_mshrs 10981 # number of cycles access was blocked
548 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
549 system.iocache.avg_blocked_cycles::no_mshrs 10.414807 # average number of cycles each access was blocked
550 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
551 system.iocache.fast_writes 0 # number of fast writes performed
552 system.iocache.cache_copies 0 # number of cache copies performed
553 system.iocache.writebacks::writebacks 41512 # number of writebacks
554 system.iocache.writebacks::total 41512 # number of writebacks
555 system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
556 system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
557 system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses
558 system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses
559 system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses
560 system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses
561 system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses
562 system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses
563 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles
564 system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles
565 system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3410139151 # number of WriteReq MSHR miss cycles
566 system.iocache.WriteReq_mshr_miss_latency::total 3410139151 # number of WriteReq MSHR miss cycles
567 system.iocache.demand_mshr_miss_latency::tsunami.ide 3415728400 # number of demand (read+write) MSHR miss cycles
568 system.iocache.demand_mshr_miss_latency::total 3415728400 # number of demand (read+write) MSHR miss cycles
569 system.iocache.overall_mshr_miss_latency::tsunami.ide 3415728400 # number of overall MSHR miss cycles
570 system.iocache.overall_mshr_miss_latency::total 3415728400 # number of overall MSHR miss cycles
571 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
572 system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
573 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses
574 system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses
575 system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses
576 system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses
577 system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses
578 system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses
579 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency
580 system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency
581 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203371.848223 # average WriteReq mshr miss latency
582 system.iocache.WriteReq_avg_mshr_miss_latency::total 203371.848223 # average WriteReq mshr miss latency
583 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency
584 system.iocache.demand_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency
585 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency
586 system.iocache.overall_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency
587 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
588 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
589 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
590 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
591 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
592 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
593 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
594 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
595 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
596 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
597 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
598 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
599 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
600 system.cpu0.dtb.fetch_hits 0 # ITB hits
601 system.cpu0.dtb.fetch_misses 0 # ITB misses
602 system.cpu0.dtb.fetch_acv 0 # ITB acv
603 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
604 system.cpu0.dtb.read_hits 4882466 # DTB read hits
605 system.cpu0.dtb.read_misses 6004 # DTB read misses
606 system.cpu0.dtb.read_acv 119 # DTB read access violations
607 system.cpu0.dtb.read_accesses 427336 # DTB read accesses
608 system.cpu0.dtb.write_hits 3509197 # DTB write hits
609 system.cpu0.dtb.write_misses 661 # DTB write misses
610 system.cpu0.dtb.write_acv 82 # DTB write access violations
611 system.cpu0.dtb.write_accesses 162892 # DTB write accesses
612 system.cpu0.dtb.data_hits 8391663 # DTB hits
613 system.cpu0.dtb.data_misses 6665 # DTB misses
614 system.cpu0.dtb.data_acv 201 # DTB access violations
615 system.cpu0.dtb.data_accesses 590228 # DTB accesses
616 system.cpu0.itb.fetch_hits 2746663 # ITB hits
617 system.cpu0.itb.fetch_misses 2999 # ITB misses
618 system.cpu0.itb.fetch_acv 99 # ITB acv
619 system.cpu0.itb.fetch_accesses 2749662 # ITB accesses
620 system.cpu0.itb.read_hits 0 # DTB read hits
621 system.cpu0.itb.read_misses 0 # DTB read misses
622 system.cpu0.itb.read_acv 0 # DTB read access violations
623 system.cpu0.itb.read_accesses 0 # DTB read accesses
624 system.cpu0.itb.write_hits 0 # DTB write hits
625 system.cpu0.itb.write_misses 0 # DTB write misses
626 system.cpu0.itb.write_acv 0 # DTB write access violations
627 system.cpu0.itb.write_accesses 0 # DTB write accesses
628 system.cpu0.itb.data_hits 0 # DTB hits
629 system.cpu0.itb.data_misses 0 # DTB misses
630 system.cpu0.itb.data_acv 0 # DTB access violations
631 system.cpu0.itb.data_accesses 0 # DTB accesses
632 system.cpu0.numCycles 928532780 # number of cpu cycles simulated
633 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
634 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
635 system.cpu0.committedInsts 33005928 # Number of instructions committed
636 system.cpu0.committedOps 33005928 # Number of ops (including micro ops) committed
637 system.cpu0.num_int_alu_accesses 30880412 # Number of integer alu accesses
638 system.cpu0.num_fp_alu_accesses 168592 # Number of float alu accesses
639 system.cpu0.num_func_calls 809679 # number of times a function call or return occured
640 system.cpu0.num_conditional_control_insts 4456286 # number of instructions that are conditional controls
641 system.cpu0.num_int_insts 30880412 # number of integer instructions
642 system.cpu0.num_fp_insts 168592 # number of float instructions
643 system.cpu0.num_int_register_reads 43182890 # number of times the integer registers were read
644 system.cpu0.num_int_register_writes 22546428 # number of times the integer registers were written
645 system.cpu0.num_fp_register_reads 87049 # number of times the floating registers were read
646 system.cpu0.num_fp_register_writes 88627 # number of times the floating registers were written
647 system.cpu0.num_mem_refs 8421419 # number of memory refs
648 system.cpu0.num_load_insts 4903545 # Number of load instructions
649 system.cpu0.num_store_insts 3517874 # Number of store instructions
650 system.cpu0.num_idle_cycles 214028071508.499786 # Number of idle cycles
651 system.cpu0.num_busy_cycles -213099538728.499786 # Number of busy cycles
652 system.cpu0.not_idle_fraction -229.501363 # Percentage of non-idle cycles
653 system.cpu0.idle_fraction 230.501363 # Percentage of idle cycles
654 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
655 system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed
656 system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed
657 system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
658 system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
659 system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
660 system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl
661 system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl
662 system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
663 system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
664 system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
665 system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
666 system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
667 system.cpu0.kern.ipl_ticks::0 1818570193000 98.74% 98.74% # number of cycles we spent at this ipl
668 system.cpu0.kern.ipl_ticks::21 39079500 0.00% 98.75% # number of cycles we spent at this ipl
669 system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl
670 system.cpu0.kern.ipl_ticks::31 22747610500 1.24% 100.00% # number of cycles we spent at this ipl
671 system.cpu0.kern.ipl_ticks::total 1841721945500 # number of cycles we spent at this ipl
672 system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
673 system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
674 system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
675 system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl
676 system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl
677 system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
678 system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
679 system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
680 system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
681 system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
682 system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
683 system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
684 system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
685 system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
686 system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
687 system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
688 system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
689 system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
690 system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
691 system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
692 system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
693 system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
694 system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
695 system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
696 system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
697 system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
698 system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
699 system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
700 system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
701 system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
702 system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
703 system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
704 system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
705 system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
706 system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
707 system.cpu0.kern.syscall::total 326 # number of syscalls executed
708 system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
709 system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
710 system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
711 system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
712 system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
713 system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
714 system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
715 system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed
716 system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
717 system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
718 system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
719 system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
720 system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
721 system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
722 system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
723 system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
724 system.cpu0.kern.callpal::total 192207 # number of callpals executed
725 system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
726 system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
727 system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
728 system.cpu0.kern.mode_good::kernel 1908
729 system.cpu0.kern.mode_good::user 1739
730 system.cpu0.kern.mode_good::idle 169
731 system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches
732 system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
733 system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
734 system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches
735 system.cpu0.kern.mode_ticks::kernel 29799200000 1.62% 1.62% # number of ticks spent at the given mode
736 system.cpu0.kern.mode_ticks::user 2569954000 0.14% 1.76% # number of ticks spent at the given mode
737 system.cpu0.kern.mode_ticks::idle 1809352787000 98.24% 100.00% # number of ticks spent at the given mode
738 system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
739 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
740 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
741 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
742 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
743 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
744 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
745 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
746 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
747 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
748 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
749 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
750 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
751 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
752 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
753 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
754 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
755 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
756 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
757 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
758 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
759 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
760 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
761 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
762 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
763 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
764 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
765 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
766 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
767 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
768 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
769 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
770 system.cpu0.icache.replacements 952928 # number of replacements
771 system.cpu0.icache.tagsinuse 511.202677 # Cycle average of tags in use
772 system.cpu0.icache.total_refs 42504111 # Total number of references to valid blocks.
773 system.cpu0.icache.sampled_refs 953439 # Sample count of references to valid blocks.
774 system.cpu0.icache.avg_refs 44.579791 # Average number of references to valid blocks.
775 system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit.
776 system.cpu0.icache.occ_blocks::cpu0.inst 252.529954 # Average occupied blocks per requestor
777 system.cpu0.icache.occ_blocks::cpu1.inst 82.679092 # Average occupied blocks per requestor
778 system.cpu0.icache.occ_blocks::cpu2.inst 175.993631 # Average occupied blocks per requestor
779 system.cpu0.icache.occ_percent::cpu0.inst 0.493223 # Average percentage of cache occupancy
780 system.cpu0.icache.occ_percent::cpu1.inst 0.161483 # Average percentage of cache occupancy
781 system.cpu0.icache.occ_percent::cpu2.inst 0.343738 # Average percentage of cache occupancy
782 system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy
783 system.cpu0.icache.ReadReq_hits::cpu0.inst 32488547 # number of ReadReq hits
784 system.cpu0.icache.ReadReq_hits::cpu1.inst 7734067 # number of ReadReq hits
785 system.cpu0.icache.ReadReq_hits::cpu2.inst 2281497 # number of ReadReq hits
786 system.cpu0.icache.ReadReq_hits::total 42504111 # number of ReadReq hits
787 system.cpu0.icache.demand_hits::cpu0.inst 32488547 # number of demand (read+write) hits
788 system.cpu0.icache.demand_hits::cpu1.inst 7734067 # number of demand (read+write) hits
789 system.cpu0.icache.demand_hits::cpu2.inst 2281497 # number of demand (read+write) hits
790 system.cpu0.icache.demand_hits::total 42504111 # number of demand (read+write) hits
791 system.cpu0.icache.overall_hits::cpu0.inst 32488547 # number of overall hits
792 system.cpu0.icache.overall_hits::cpu1.inst 7734067 # number of overall hits
793 system.cpu0.icache.overall_hits::cpu2.inst 2281497 # number of overall hits
794 system.cpu0.icache.overall_hits::total 42504111 # number of overall hits
795 system.cpu0.icache.ReadReq_misses::cpu0.inst 524247 # number of ReadReq misses
796 system.cpu0.icache.ReadReq_misses::cpu1.inst 129266 # number of ReadReq misses
797 system.cpu0.icache.ReadReq_misses::cpu2.inst 316688 # number of ReadReq misses
798 system.cpu0.icache.ReadReq_misses::total 970201 # number of ReadReq misses
799 system.cpu0.icache.demand_misses::cpu0.inst 524247 # number of demand (read+write) misses
800 system.cpu0.icache.demand_misses::cpu1.inst 129266 # number of demand (read+write) misses
801 system.cpu0.icache.demand_misses::cpu2.inst 316688 # number of demand (read+write) misses
802 system.cpu0.icache.demand_misses::total 970201 # number of demand (read+write) misses
803 system.cpu0.icache.overall_misses::cpu0.inst 524247 # number of overall misses
804 system.cpu0.icache.overall_misses::cpu1.inst 129266 # number of overall misses
805 system.cpu0.icache.overall_misses::cpu2.inst 316688 # number of overall misses
806 system.cpu0.icache.overall_misses::total 970201 # number of overall misses
807 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820027500 # number of ReadReq miss cycles
808 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4433734984 # number of ReadReq miss cycles
809 system.cpu0.icache.ReadReq_miss_latency::total 6253762484 # number of ReadReq miss cycles
810 system.cpu0.icache.demand_miss_latency::cpu1.inst 1820027500 # number of demand (read+write) miss cycles
811 system.cpu0.icache.demand_miss_latency::cpu2.inst 4433734984 # number of demand (read+write) miss cycles
812 system.cpu0.icache.demand_miss_latency::total 6253762484 # number of demand (read+write) miss cycles
813 system.cpu0.icache.overall_miss_latency::cpu1.inst 1820027500 # number of overall miss cycles
814 system.cpu0.icache.overall_miss_latency::cpu2.inst 4433734984 # number of overall miss cycles
815 system.cpu0.icache.overall_miss_latency::total 6253762484 # number of overall miss cycles
816 system.cpu0.icache.ReadReq_accesses::cpu0.inst 33012794 # number of ReadReq accesses(hits+misses)
817 system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863333 # number of ReadReq accesses(hits+misses)
818 system.cpu0.icache.ReadReq_accesses::cpu2.inst 2598185 # number of ReadReq accesses(hits+misses)
819 system.cpu0.icache.ReadReq_accesses::total 43474312 # number of ReadReq accesses(hits+misses)
820 system.cpu0.icache.demand_accesses::cpu0.inst 33012794 # number of demand (read+write) accesses
821 system.cpu0.icache.demand_accesses::cpu1.inst 7863333 # number of demand (read+write) accesses
822 system.cpu0.icache.demand_accesses::cpu2.inst 2598185 # number of demand (read+write) accesses
823 system.cpu0.icache.demand_accesses::total 43474312 # number of demand (read+write) accesses
824 system.cpu0.icache.overall_accesses::cpu0.inst 33012794 # number of overall (read+write) accesses
825 system.cpu0.icache.overall_accesses::cpu1.inst 7863333 # number of overall (read+write) accesses
826 system.cpu0.icache.overall_accesses::cpu2.inst 2598185 # number of overall (read+write) accesses
827 system.cpu0.icache.overall_accesses::total 43474312 # number of overall (read+write) accesses
828 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015880 # miss rate for ReadReq accesses
829 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016439 # miss rate for ReadReq accesses
830 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121888 # miss rate for ReadReq accesses
831 system.cpu0.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses
832 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015880 # miss rate for demand accesses
833 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016439 # miss rate for demand accesses
834 system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121888 # miss rate for demand accesses
835 system.cpu0.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses
836 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015880 # miss rate for overall accesses
837 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016439 # miss rate for overall accesses
838 system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121888 # miss rate for overall accesses
839 system.cpu0.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses
840 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14079.707734 # average ReadReq miss latency
841 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14000.325191 # average ReadReq miss latency
842 system.cpu0.icache.ReadReq_avg_miss_latency::total 6445.842134 # average ReadReq miss latency
843 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency
844 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency
845 system.cpu0.icache.demand_avg_miss_latency::total 6445.842134 # average overall miss latency
846 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency
847 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency
848 system.cpu0.icache.overall_avg_miss_latency::total 6445.842134 # average overall miss latency
849 system.cpu0.icache.blocked_cycles::no_mshrs 6047 # number of cycles access was blocked
850 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
851 system.cpu0.icache.blocked::no_mshrs 177 # number of cycles access was blocked
852 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
853 system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.163842 # average number of cycles each access was blocked
854 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
855 system.cpu0.icache.fast_writes 0 # number of fast writes performed
856 system.cpu0.icache.cache_copies 0 # number of cache copies performed
857 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16592 # number of ReadReq MSHR hits
858 system.cpu0.icache.ReadReq_mshr_hits::total 16592 # number of ReadReq MSHR hits
859 system.cpu0.icache.demand_mshr_hits::cpu2.inst 16592 # number of demand (read+write) MSHR hits
860 system.cpu0.icache.demand_mshr_hits::total 16592 # number of demand (read+write) MSHR hits
861 system.cpu0.icache.overall_mshr_hits::cpu2.inst 16592 # number of overall MSHR hits
862 system.cpu0.icache.overall_mshr_hits::total 16592 # number of overall MSHR hits
863 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129266 # number of ReadReq MSHR misses
864 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 300096 # number of ReadReq MSHR misses
865 system.cpu0.icache.ReadReq_mshr_misses::total 429362 # number of ReadReq MSHR misses
866 system.cpu0.icache.demand_mshr_misses::cpu1.inst 129266 # number of demand (read+write) MSHR misses
867 system.cpu0.icache.demand_mshr_misses::cpu2.inst 300096 # number of demand (read+write) MSHR misses
868 system.cpu0.icache.demand_mshr_misses::total 429362 # number of demand (read+write) MSHR misses
869 system.cpu0.icache.overall_mshr_misses::cpu1.inst 129266 # number of overall MSHR misses
870 system.cpu0.icache.overall_mshr_misses::cpu2.inst 300096 # number of overall MSHR misses
871 system.cpu0.icache.overall_mshr_misses::total 429362 # number of overall MSHR misses
872 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1561495500 # number of ReadReq MSHR miss cycles
873 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3655561484 # number of ReadReq MSHR miss cycles
874 system.cpu0.icache.ReadReq_mshr_miss_latency::total 5217056984 # number of ReadReq MSHR miss cycles
875 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1561495500 # number of demand (read+write) MSHR miss cycles
876 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3655561484 # number of demand (read+write) MSHR miss cycles
877 system.cpu0.icache.demand_mshr_miss_latency::total 5217056984 # number of demand (read+write) MSHR miss cycles
878 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1561495500 # number of overall MSHR miss cycles
879 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3655561484 # number of overall MSHR miss cycles
880 system.cpu0.icache.overall_mshr_miss_latency::total 5217056984 # number of overall MSHR miss cycles
881 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for ReadReq accesses
882 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for ReadReq accesses
883 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses
884 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for demand accesses
885 system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for demand accesses
886 system.cpu0.icache.demand_mshr_miss_rate::total 0.009876 # mshr miss rate for demand accesses
887 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for overall accesses
888 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for overall accesses
889 system.cpu0.icache.overall_mshr_miss_rate::total 0.009876 # mshr miss rate for overall accesses
890 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average ReadReq mshr miss latency
891 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average ReadReq mshr miss latency
892 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.718936 # average ReadReq mshr miss latency
893 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency
894 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency
895 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency
896 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency
897 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency
898 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency
899 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
900 system.cpu0.dcache.replacements 1392518 # number of replacements
901 system.cpu0.dcache.tagsinuse 511.997811 # Cycle average of tags in use
902 system.cpu0.dcache.total_refs 13324693 # Total number of references to valid blocks.
903 system.cpu0.dcache.sampled_refs 1393030 # Sample count of references to valid blocks.
904 system.cpu0.dcache.avg_refs 9.565259 # Average number of references to valid blocks.
905 system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
906 system.cpu0.dcache.occ_blocks::cpu0.data 242.082942 # Average occupied blocks per requestor
907 system.cpu0.dcache.occ_blocks::cpu1.data 91.912647 # Average occupied blocks per requestor
908 system.cpu0.dcache.occ_blocks::cpu2.data 178.002223 # Average occupied blocks per requestor
909 system.cpu0.dcache.occ_percent::cpu0.data 0.472818 # Average percentage of cache occupancy
910 system.cpu0.dcache.occ_percent::cpu1.data 0.179517 # Average percentage of cache occupancy
911 system.cpu0.dcache.occ_percent::cpu2.data 0.347661 # Average percentage of cache occupancy
912 system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
913 system.cpu0.dcache.ReadReq_hits::cpu0.data 4059783 # number of ReadReq hits
914 system.cpu0.dcache.ReadReq_hits::cpu1.data 1097740 # number of ReadReq hits
915 system.cpu0.dcache.ReadReq_hits::cpu2.data 2407711 # number of ReadReq hits
916 system.cpu0.dcache.ReadReq_hits::total 7565234 # number of ReadReq hits
917 system.cpu0.dcache.WriteReq_hits::cpu0.data 3212644 # number of WriteReq hits
918 system.cpu0.dcache.WriteReq_hits::cpu1.data 860147 # number of WriteReq hits
919 system.cpu0.dcache.WriteReq_hits::cpu2.data 1303129 # number of WriteReq hits
920 system.cpu0.dcache.WriteReq_hits::total 5375920 # number of WriteReq hits
921 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116773 # number of LoadLockedReq hits
922 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19259 # number of LoadLockedReq hits
923 system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48170 # number of LoadLockedReq hits
924 system.cpu0.dcache.LoadLockedReq_hits::total 184202 # number of LoadLockedReq hits
925 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125878 # number of StoreCondReq hits
926 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21341 # number of StoreCondReq hits
927 system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52053 # number of StoreCondReq hits
928 system.cpu0.dcache.StoreCondReq_hits::total 199272 # number of StoreCondReq hits
929 system.cpu0.dcache.demand_hits::cpu0.data 7272427 # number of demand (read+write) hits
930 system.cpu0.dcache.demand_hits::cpu1.data 1957887 # number of demand (read+write) hits
931 system.cpu0.dcache.demand_hits::cpu2.data 3710840 # number of demand (read+write) hits
932 system.cpu0.dcache.demand_hits::total 12941154 # number of demand (read+write) hits
933 system.cpu0.dcache.overall_hits::cpu0.data 7272427 # number of overall hits
934 system.cpu0.dcache.overall_hits::cpu1.data 1957887 # number of overall hits
935 system.cpu0.dcache.overall_hits::cpu2.data 3710840 # number of overall hits
936 system.cpu0.dcache.overall_hits::total 12941154 # number of overall hits
937 system.cpu0.dcache.ReadReq_misses::cpu0.data 707193 # number of ReadReq misses
938 system.cpu0.dcache.ReadReq_misses::cpu1.data 104402 # number of ReadReq misses
939 system.cpu0.dcache.ReadReq_misses::cpu2.data 546003 # number of ReadReq misses
940 system.cpu0.dcache.ReadReq_misses::total 1357598 # number of ReadReq misses
941 system.cpu0.dcache.WriteReq_misses::cpu0.data 169666 # number of WriteReq misses
942 system.cpu0.dcache.WriteReq_misses::cpu1.data 48403 # number of WriteReq misses
943 system.cpu0.dcache.WriteReq_misses::cpu2.data 557126 # number of WriteReq misses
944 system.cpu0.dcache.WriteReq_misses::total 775195 # number of WriteReq misses
945 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9666 # number of LoadLockedReq misses
946 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2214 # number of LoadLockedReq misses
947 system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6955 # number of LoadLockedReq misses
948 system.cpu0.dcache.LoadLockedReq_misses::total 18835 # number of LoadLockedReq misses
949 system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses
950 system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
951 system.cpu0.dcache.demand_misses::cpu0.data 876859 # number of demand (read+write) misses
952 system.cpu0.dcache.demand_misses::cpu1.data 152805 # number of demand (read+write) misses
953 system.cpu0.dcache.demand_misses::cpu2.data 1103129 # number of demand (read+write) misses
954 system.cpu0.dcache.demand_misses::total 2132793 # number of demand (read+write) misses
955 system.cpu0.dcache.overall_misses::cpu0.data 876859 # number of overall misses
956 system.cpu0.dcache.overall_misses::cpu1.data 152805 # number of overall misses
957 system.cpu0.dcache.overall_misses::cpu2.data 1103129 # number of overall misses
958 system.cpu0.dcache.overall_misses::total 2132793 # number of overall misses
959 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2177012500 # number of ReadReq miss cycles
960 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9421187500 # number of ReadReq miss cycles
961 system.cpu0.dcache.ReadReq_miss_latency::total 11598200000 # number of ReadReq miss cycles
962 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393651000 # number of WriteReq miss cycles
963 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14650982812 # number of WriteReq miss cycles
964 system.cpu0.dcache.WriteReq_miss_latency::total 16044633812 # number of WriteReq miss cycles
965 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29146500 # number of LoadLockedReq miss cycles
966 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103568500 # number of LoadLockedReq miss cycles
967 system.cpu0.dcache.LoadLockedReq_miss_latency::total 132715000 # number of LoadLockedReq miss cycles
968 system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles
969 system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
970 system.cpu0.dcache.demand_miss_latency::cpu1.data 3570663500 # number of demand (read+write) miss cycles
971 system.cpu0.dcache.demand_miss_latency::cpu2.data 24072170312 # number of demand (read+write) miss cycles
972 system.cpu0.dcache.demand_miss_latency::total 27642833812 # number of demand (read+write) miss cycles
973 system.cpu0.dcache.overall_miss_latency::cpu1.data 3570663500 # number of overall miss cycles
974 system.cpu0.dcache.overall_miss_latency::cpu2.data 24072170312 # number of overall miss cycles
975 system.cpu0.dcache.overall_miss_latency::total 27642833812 # number of overall miss cycles
976 system.cpu0.dcache.ReadReq_accesses::cpu0.data 4766976 # number of ReadReq accesses(hits+misses)
977 system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202142 # number of ReadReq accesses(hits+misses)
978 system.cpu0.dcache.ReadReq_accesses::cpu2.data 2953714 # number of ReadReq accesses(hits+misses)
979 system.cpu0.dcache.ReadReq_accesses::total 8922832 # number of ReadReq accesses(hits+misses)
980 system.cpu0.dcache.WriteReq_accesses::cpu0.data 3382310 # number of WriteReq accesses(hits+misses)
981 system.cpu0.dcache.WriteReq_accesses::cpu1.data 908550 # number of WriteReq accesses(hits+misses)
982 system.cpu0.dcache.WriteReq_accesses::cpu2.data 1860255 # number of WriteReq accesses(hits+misses)
983 system.cpu0.dcache.WriteReq_accesses::total 6151115 # number of WriteReq accesses(hits+misses)
984 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126439 # number of LoadLockedReq accesses(hits+misses)
985 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21473 # number of LoadLockedReq accesses(hits+misses)
986 system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55125 # number of LoadLockedReq accesses(hits+misses)
987 system.cpu0.dcache.LoadLockedReq_accesses::total 203037 # number of LoadLockedReq accesses(hits+misses)
988 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125878 # number of StoreCondReq accesses(hits+misses)
989 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21341 # number of StoreCondReq accesses(hits+misses)
990 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52054 # number of StoreCondReq accesses(hits+misses)
991 system.cpu0.dcache.StoreCondReq_accesses::total 199273 # number of StoreCondReq accesses(hits+misses)
992 system.cpu0.dcache.demand_accesses::cpu0.data 8149286 # number of demand (read+write) accesses
993 system.cpu0.dcache.demand_accesses::cpu1.data 2110692 # number of demand (read+write) accesses
994 system.cpu0.dcache.demand_accesses::cpu2.data 4813969 # number of demand (read+write) accesses
995 system.cpu0.dcache.demand_accesses::total 15073947 # number of demand (read+write) accesses
996 system.cpu0.dcache.overall_accesses::cpu0.data 8149286 # number of overall (read+write) accesses
997 system.cpu0.dcache.overall_accesses::cpu1.data 2110692 # number of overall (read+write) accesses
998 system.cpu0.dcache.overall_accesses::cpu2.data 4813969 # number of overall (read+write) accesses
999 system.cpu0.dcache.overall_accesses::total 15073947 # number of overall (read+write) accesses
1000 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148353 # miss rate for ReadReq accesses
1001 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086847 # miss rate for ReadReq accesses
1002 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184853 # miss rate for ReadReq accesses
1003 system.cpu0.dcache.ReadReq_miss_rate::total 0.152149 # miss rate for ReadReq accesses
1004 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050163 # miss rate for WriteReq accesses
1005 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053275 # miss rate for WriteReq accesses
1006 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.299489 # miss rate for WriteReq accesses
1007 system.cpu0.dcache.WriteReq_miss_rate::total 0.126025 # miss rate for WriteReq accesses
1008 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076448 # miss rate for LoadLockedReq accesses
1009 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103106 # miss rate for LoadLockedReq accesses
1010 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.126168 # miss rate for LoadLockedReq accesses
1011 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092766 # miss rate for LoadLockedReq accesses
1012 system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
1013 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
1014 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107599 # miss rate for demand accesses
1015 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072396 # miss rate for demand accesses
1016 system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229152 # miss rate for demand accesses
1017 system.cpu0.dcache.demand_miss_rate::total 0.141489 # miss rate for demand accesses
1018 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107599 # miss rate for overall accesses
1019 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072396 # miss rate for overall accesses
1020 system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229152 # miss rate for overall accesses
1021 system.cpu0.dcache.overall_miss_rate::total 0.141489 # miss rate for overall accesses
1022 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20852.210686 # average ReadReq miss latency
1023 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17254.827354 # average ReadReq miss latency
1024 system.cpu0.dcache.ReadReq_avg_miss_latency::total 8543.176993 # average ReadReq miss latency
1025 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28792.657480 # average WriteReq miss latency
1026 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26297.431482 # average WriteReq miss latency
1027 system.cpu0.dcache.WriteReq_avg_miss_latency::total 20697.545536 # average WriteReq miss latency
1028 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13164.634146 # average LoadLockedReq miss latency
1029 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14891.229331 # average LoadLockedReq miss latency
1030 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7046.190603 # average LoadLockedReq miss latency
1031 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
1032 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
1033 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency
1034 system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency
1035 system.cpu0.dcache.demand_avg_miss_latency::total 12960.861092 # average overall miss latency
1036 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency
1037 system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency
1038 system.cpu0.dcache.overall_avg_miss_latency::total 12960.861092 # average overall miss latency
1039 system.cpu0.dcache.blocked_cycles::no_mshrs 423654 # number of cycles access was blocked
1040 system.cpu0.dcache.blocked_cycles::no_targets 2998 # number of cycles access was blocked
1041 system.cpu0.dcache.blocked::no_mshrs 16794 # number of cycles access was blocked
1042 system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
1043 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.226509 # average number of cycles each access was blocked
1044 system.cpu0.dcache.avg_blocked_cycles::no_targets 428.285714 # average number of cycles each access was blocked
1045 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1046 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1047 system.cpu0.dcache.writebacks::writebacks 836151 # number of writebacks
1048 system.cpu0.dcache.writebacks::total 836151 # number of writebacks
1049 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 284315 # number of ReadReq MSHR hits
1050 system.cpu0.dcache.ReadReq_mshr_hits::total 284315 # number of ReadReq MSHR hits
1051 system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 472764 # number of WriteReq MSHR hits
1052 system.cpu0.dcache.WriteReq_mshr_hits::total 472764 # number of WriteReq MSHR hits
1053 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1457 # number of LoadLockedReq MSHR hits
1054 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits
1055 system.cpu0.dcache.demand_mshr_hits::cpu2.data 757079 # number of demand (read+write) MSHR hits
1056 system.cpu0.dcache.demand_mshr_hits::total 757079 # number of demand (read+write) MSHR hits
1057 system.cpu0.dcache.overall_mshr_hits::cpu2.data 757079 # number of overall MSHR hits
1058 system.cpu0.dcache.overall_mshr_hits::total 757079 # number of overall MSHR hits
1059 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104402 # number of ReadReq MSHR misses
1060 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261688 # number of ReadReq MSHR misses
1061 system.cpu0.dcache.ReadReq_mshr_misses::total 366090 # number of ReadReq MSHR misses
1062 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48403 # number of WriteReq MSHR misses
1063 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84362 # number of WriteReq MSHR misses
1064 system.cpu0.dcache.WriteReq_mshr_misses::total 132765 # number of WriteReq MSHR misses
1065 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2214 # number of LoadLockedReq MSHR misses
1066 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5498 # number of LoadLockedReq MSHR misses
1067 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7712 # number of LoadLockedReq MSHR misses
1068 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
1069 system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
1070 system.cpu0.dcache.demand_mshr_misses::cpu1.data 152805 # number of demand (read+write) MSHR misses
1071 system.cpu0.dcache.demand_mshr_misses::cpu2.data 346050 # number of demand (read+write) MSHR misses
1072 system.cpu0.dcache.demand_mshr_misses::total 498855 # number of demand (read+write) MSHR misses
1073 system.cpu0.dcache.overall_mshr_misses::cpu1.data 152805 # number of overall MSHR misses
1074 system.cpu0.dcache.overall_mshr_misses::cpu2.data 346050 # number of overall MSHR misses
1075 system.cpu0.dcache.overall_mshr_misses::total 498855 # number of overall MSHR misses
1076 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1968208500 # number of ReadReq MSHR miss cycles
1077 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4300121500 # number of ReadReq MSHR miss cycles
1078 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6268330000 # number of ReadReq MSHR miss cycles
1079 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1296845000 # number of WriteReq MSHR miss cycles
1080 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131428631 # number of WriteReq MSHR miss cycles
1081 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3428273631 # number of WriteReq MSHR miss cycles
1082 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24718500 # number of LoadLockedReq MSHR miss cycles
1083 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69834500 # number of LoadLockedReq MSHR miss cycles
1084 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94553000 # number of LoadLockedReq MSHR miss cycles
1085 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles
1086 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
1087 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3265053500 # number of demand (read+write) MSHR miss cycles
1088 system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6431550131 # number of demand (read+write) MSHR miss cycles
1089 system.cpu0.dcache.demand_mshr_miss_latency::total 9696603631 # number of demand (read+write) MSHR miss cycles
1090 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3265053500 # number of overall MSHR miss cycles
1091 system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6431550131 # number of overall MSHR miss cycles
1092 system.cpu0.dcache.overall_mshr_miss_latency::total 9696603631 # number of overall MSHR miss cycles
1093 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287785000 # number of ReadReq MSHR uncacheable cycles
1094 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353197500 # number of ReadReq MSHR uncacheable cycles
1095 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 640982500 # number of ReadReq MSHR uncacheable cycles
1096 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356424500 # number of WriteReq MSHR uncacheable cycles
1097 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles
1098 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles
1099 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles
1100 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles
1101 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles
1102 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses
1103 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses
1104 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses
1105 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses
1106 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses
1107 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses
1108 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses
1109 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses
1110 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses
1111 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
1112 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
1113 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses
1114 system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses
1115 system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses
1116 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses
1117 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses
1118 system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses
1119 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency
1120 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency
1121 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency
1122 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency
1123 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency
1124 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency
1125 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency
1126 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency
1127 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency
1128 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
1129 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
1130 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency
1131 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency
1132 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency
1133 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency
1134 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency
1135 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency
1136 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1137 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
1138 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1139 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1140 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
1141 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1142 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1143 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
1144 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1145 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1146 system.cpu1.dtb.fetch_hits 0 # ITB hits
1147 system.cpu1.dtb.fetch_misses 0 # ITB misses
1148 system.cpu1.dtb.fetch_acv 0 # ITB acv
1149 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1150 system.cpu1.dtb.read_hits 1221293 # DTB read hits
1151 system.cpu1.dtb.read_misses 1489 # DTB read misses
1152 system.cpu1.dtb.read_acv 40 # DTB read access violations
1153 system.cpu1.dtb.read_accesses 143781 # DTB read accesses
1154 system.cpu1.dtb.write_hits 930282 # DTB write hits
1155 system.cpu1.dtb.write_misses 202 # DTB write misses
1156 system.cpu1.dtb.write_acv 24 # DTB write access violations
1157 system.cpu1.dtb.write_accesses 59266 # DTB write accesses
1158 system.cpu1.dtb.data_hits 2151575 # DTB hits
1159 system.cpu1.dtb.data_misses 1691 # DTB misses
1160 system.cpu1.dtb.data_acv 64 # DTB access violations
1161 system.cpu1.dtb.data_accesses 203047 # DTB accesses
1162 system.cpu1.itb.fetch_hits 872259 # ITB hits
1163 system.cpu1.itb.fetch_misses 756 # ITB misses
1164 system.cpu1.itb.fetch_acv 43 # ITB acv
1165 system.cpu1.itb.fetch_accesses 873015 # ITB accesses
1166 system.cpu1.itb.read_hits 0 # DTB read hits
1167 system.cpu1.itb.read_misses 0 # DTB read misses
1168 system.cpu1.itb.read_acv 0 # DTB read access violations
1169 system.cpu1.itb.read_accesses 0 # DTB read accesses
1170 system.cpu1.itb.write_hits 0 # DTB write hits
1171 system.cpu1.itb.write_misses 0 # DTB write misses
1172 system.cpu1.itb.write_acv 0 # DTB write access violations
1173 system.cpu1.itb.write_accesses 0 # DTB write accesses
1174 system.cpu1.itb.data_hits 0 # DTB hits
1175 system.cpu1.itb.data_misses 0 # DTB misses
1176 system.cpu1.itb.data_acv 0 # DTB access violations
1177 system.cpu1.itb.data_accesses 0 # DTB accesses
1178 system.cpu1.numCycles 953618286 # number of cpu cycles simulated
1179 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1180 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1181 system.cpu1.committedInsts 7861577 # Number of instructions committed
1182 system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed
1183 system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses
1184 system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses
1185 system.cpu1.num_func_calls 212083 # number of times a function call or return occured
1186 system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls
1187 system.cpu1.num_int_insts 7312995 # number of integer instructions
1188 system.cpu1.num_fp_insts 45507 # number of float instructions
1189 system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read
1190 system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written
1191 system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read
1192 system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written
1193 system.cpu1.num_mem_refs 2159267 # number of memory refs
1194 system.cpu1.num_load_insts 1226545 # Number of load instructions
1195 system.cpu1.num_store_insts 932722 # Number of store instructions
1196 system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles
1197 system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles
1198 system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles
1199 system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles
1200 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1201 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1202 system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
1203 system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
1204 system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
1205 system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
1206 system.cpu1.kern.mode_good::kernel 0
1207 system.cpu1.kern.mode_good::user 0
1208 system.cpu1.kern.mode_good::idle 0
1209 system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
1210 system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
1211 system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
1212 system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
1213 system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
1214 system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
1215 system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
1216 system.cpu1.kern.swap_context 0 # number of times the context was actually changed
1217 system.cpu2.branchPred.lookups 8378030 # Number of BP lookups
1218 system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted
1219 system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect
1220 system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups
1221 system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits
1222 system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1223 system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage
1224 system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target.
1225 system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions.
1226 system.cpu2.dtb.fetch_hits 0 # ITB hits
1227 system.cpu2.dtb.fetch_misses 0 # ITB misses
1228 system.cpu2.dtb.fetch_acv 0 # ITB acv
1229 system.cpu2.dtb.fetch_accesses 0 # ITB accesses
1230 system.cpu2.dtb.read_hits 3213070 # DTB read hits
1231 system.cpu2.dtb.read_misses 11858 # DTB read misses
1232 system.cpu2.dtb.read_acv 125 # DTB read access violations
1233 system.cpu2.dtb.read_accesses 216838 # DTB read accesses
1234 system.cpu2.dtb.write_hits 1985729 # DTB write hits
1235 system.cpu2.dtb.write_misses 2626 # DTB write misses
1236 system.cpu2.dtb.write_acv 132 # DTB write access violations
1237 system.cpu2.dtb.write_accesses 82100 # DTB write accesses
1238 system.cpu2.dtb.data_hits 5198799 # DTB hits
1239 system.cpu2.dtb.data_misses 14484 # DTB misses
1240 system.cpu2.dtb.data_acv 257 # DTB access violations
1241 system.cpu2.dtb.data_accesses 298938 # DTB accesses
1242 system.cpu2.itb.fetch_hits 371799 # ITB hits
1243 system.cpu2.itb.fetch_misses 5527 # ITB misses
1244 system.cpu2.itb.fetch_acv 268 # ITB acv
1245 system.cpu2.itb.fetch_accesses 377326 # ITB accesses
1246 system.cpu2.itb.read_hits 0 # DTB read hits
1247 system.cpu2.itb.read_misses 0 # DTB read misses
1248 system.cpu2.itb.read_acv 0 # DTB read access violations
1249 system.cpu2.itb.read_accesses 0 # DTB read accesses
1250 system.cpu2.itb.write_hits 0 # DTB write hits
1251 system.cpu2.itb.write_misses 0 # DTB write misses
1252 system.cpu2.itb.write_acv 0 # DTB write access violations
1253 system.cpu2.itb.write_accesses 0 # DTB write accesses
1254 system.cpu2.itb.data_hits 0 # DTB hits
1255 system.cpu2.itb.data_misses 0 # DTB misses
1256 system.cpu2.itb.data_acv 0 # DTB access violations
1257 system.cpu2.itb.data_accesses 0 # DTB accesses
1258 system.cpu2.numCycles 30456501 # number of cpu cycles simulated
1259 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1260 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1261 system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss
1262 system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed
1263 system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered
1264 system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken
1265 system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked
1266 system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing
1267 system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked
1268 system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1269 system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain
1270 system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps
1271 system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions
1272 system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
1273 system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched
1274 system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed
1275 system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total)
1276 system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total)
1277 system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total)
1278 system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1279 system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total)
1280 system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total)
1281 system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total)
1282 system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total)
1283 system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total)
1284 system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total)
1285 system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total)
1286 system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total)
1287 system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total)
1288 system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1289 system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1290 system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1291 system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total)
1292 system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle
1293 system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle
1294 system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle
1295 system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked
1296 system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running
1297 system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking
1298 system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing
1299 system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch
1300 system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction
1301 system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode
1302 system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode
1303 system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing
1304 system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle
1305 system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking
1306 system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst
1307 system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running
1308 system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking
1309 system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename
1310 system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full
1311 system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full
1312 system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full
1313 system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed
1314 system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made
1315 system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups
1316 system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups
1317 system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed
1318 system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing
1319 system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed
1320 system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed
1321 system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer
1322 system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit.
1323 system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit.
1324 system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads.
1325 system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores.
1326 system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec)
1327 system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ
1328 system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued
1329 system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued
1330 system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling
1331 system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph
1332 system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed
1333 system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle
1334 system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle
1335 system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle
1336 system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1337 system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle
1338 system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle
1339 system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle
1340 system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle
1341 system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle
1342 system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle
1343 system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle
1344 system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle
1345 system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle
1346 system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1347 system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1348 system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1349 system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle
1350 system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1351 system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available
1352 system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available
1353 system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available
1354 system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available
1355 system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available
1356 system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available
1357 system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available
1358 system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available
1359 system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
1360 system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available
1361 system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available
1362 system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available
1363 system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available
1364 system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available
1365 system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available
1366 system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available
1367 system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available
1368 system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available
1369 system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available
1370 system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available
1371 system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available
1372 system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available
1373 system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available
1374 system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available
1375 system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available
1376 system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available
1377 system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available
1378 system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available
1379 system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
1380 system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available
1381 system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available
1382 system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1383 system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1384 system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued
1385 system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued
1386 system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued
1387 system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued
1388 system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued
1389 system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued
1390 system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued
1391 system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued
1392 system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued
1393 system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued
1394 system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued
1395 system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued
1396 system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued
1397 system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued
1398 system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued
1399 system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued
1400 system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued
1401 system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued
1402 system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued
1403 system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued
1404 system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued
1405 system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued
1406 system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued
1407 system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued
1408 system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued
1409 system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued
1410 system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued
1411 system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued
1412 system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued
1413 system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued
1414 system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued
1415 system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued
1416 system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued
1417 system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1418 system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued
1419 system.cpu2.iq.rate 0.994264 # Inst issue rate
1420 system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested
1421 system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst)
1422 system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads
1423 system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes
1424 system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses
1425 system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads
1426 system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes
1427 system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses
1428 system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses
1429 system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses
1430 system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores
1431 system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1432 system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed
1433 system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed
1434 system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations
1435 system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed
1436 system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1437 system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1438 system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled
1439 system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked
1440 system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1441 system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing
1442 system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking
1443 system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking
1444 system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ
1445 system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch
1446 system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions
1447 system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions
1448 system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions
1449 system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall
1450 system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall
1451 system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations
1452 system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly
1453 system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly
1454 system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute
1455 system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions
1456 system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed
1457 system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute
1458 system.cpu2.iew.exec_swp 0 # number of swp insts executed
1459 system.cpu2.iew.exec_nop 1279986 # number of nop insts executed
1460 system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed
1461 system.cpu2.iew.exec_branches 6791959 # Number of branches executed
1462 system.cpu2.iew.exec_stores 1992832 # Number of stores executed
1463 system.cpu2.iew.exec_rate 0.989003 # Inst execution rate
1464 system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit
1465 system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back
1466 system.cpu2.iew.wb_producers 17325737 # num instructions producing a value
1467 system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value
1468 system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1469 system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle
1470 system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back
1471 system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1472 system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit
1473 system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards
1474 system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted
1475 system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle
1476 system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle
1477 system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle
1478 system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1479 system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle
1480 system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle
1481 system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle
1482 system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle
1483 system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle
1484 system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle
1485 system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle
1486 system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle
1487 system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle
1488 system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1489 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1490 system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1491 system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle
1492 system.cpu2.commit.committedInsts 30241196 # Number of instructions committed
1493 system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed
1494 system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1495 system.cpu2.commit.refs 4874767 # Number of memory references committed
1496 system.cpu2.commit.loads 2959021 # Number of loads committed
1497 system.cpu2.commit.membars 64729 # Number of memory barriers committed
1498 system.cpu2.commit.branches 6642526 # Number of branches committed
1499 system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions.
1500 system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions.
1501 system.cpu2.commit.function_calls 230913 # Number of function calls committed.
1502 system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached
1503 system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1504 system.cpu2.rob.rob_reads 58235962 # The number of ROB reads
1505 system.cpu2.rob.rob_writes 65598028 # The number of ROB writes
1506 system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself
1507 system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling
1508 system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1509 system.cpu2.committedInsts 29069459 # Number of Instructions Simulated
1510 system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated
1511 system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated
1512 system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction
1513 system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads
1514 system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle
1515 system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads
1516 system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads
1517 system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes
1518 system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads
1519 system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes
1520 system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads
1521 system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes
1522 system.cpu2.kern.inst.arm 0 # number of arm instructions executed
1523 system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
1524 system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
1525 system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
1526 system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
1527 system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
1528 system.cpu2.kern.mode_good::kernel 0
1529 system.cpu2.kern.mode_good::user 0
1530 system.cpu2.kern.mode_good::idle 0
1531 system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
1532 system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
1533 system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
1534 system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
1535 system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
1536 system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
1537 system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
1538 system.cpu2.kern.swap_context 0 # number of times the context was actually changed
1540 ---------- End Simulation Statistics ----------
projects / gem5.git / blob