8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
15 boot_loader=/work/gem5/dist/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
24 gic_cpu_addr=738205696
25 have_large_asid_64=false
28 have_virtualization=false
29 highest_el_is_64=false
31 kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
32 kernel_addr_check=true
33 load_addr_mask=268435455
34 load_offset=2147483648
35 machine_type=VExpress_EMM
37 mem_ranges=2147483648:2415919103
38 memories=system.physmem system.realview.nvmem system.realview.vram
39 mmap_using_noreserve=false
45 readfile=/work/gem5/outgoing/gem5/tests/halt.sh
48 work_begin_ckpt_count=0
49 work_begin_cpu_id_exit=-1
50 work_begin_exit_count=0
51 work_cpus_ckpt_count=0
55 system_port=system.membus.slave[1]
59 clk_domain=system.clk_domain
62 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
65 master=system.iobus.slave[0]
66 slave=system.membus.master[0]
74 image=system.cf0.image
79 child=system.cf0.image.child
85 [system.cf0.image.child]
88 image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
97 voltage_domain=system.voltage_domain
101 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
102 branchPred=system.cpu.branchPred
104 clk_domain=system.cpu_clk_domain
106 decodeCycleInput=true
107 decodeInputBufferSize=3
109 decodeToExecuteForwardDelay=1
110 do_checkpoint_insts=true
112 do_statistics_insts=true
113 dstage2_mmu=system.cpu.dstage2_mmu
117 executeAllowEarlyMemoryIssue=true
120 executeCycleInput=true
121 executeFuncUnits=system.cpu.executeFuncUnits
122 executeInputBufferSize=7
125 executeLSQMaxStoreBufferStoresPerCycle=2
126 executeLSQRequestsQueueSize=1
127 executeLSQStoreBufferSize=5
128 executeLSQTransfersQueueSize=2
129 executeMaxAccessesInMemory=2
130 executeMemoryCommitLimit=1
131 executeMemoryIssueLimit=1
133 executeSetTraceTimeOnCommit=true
134 executeSetTraceTimeOnIssue=false
136 fetch1LineSnapWidth=0
138 fetch1ToFetch2BackwardDelay=1
139 fetch1ToFetch2ForwardDelay=1
140 fetch2CycleInput=true
141 fetch2InputBufferSize=2
142 fetch2ToDecodeForwardDelay=1
144 function_trace_start=0
145 interrupts=system.cpu.interrupts
147 istage2_mmu=system.cpu.istage2_mmu
149 max_insts_all_threads=0
150 max_insts_any_thread=0
151 max_loads_all_threads=0
152 max_loads_any_thread=0
156 simpoint_start_insts=
160 tracer=system.cpu.tracer
162 dcache_port=system.cpu.dcache.cpu_side
163 icache_port=system.cpu.icache.cpu_side
165 [system.cpu.branchPred]
171 choicePredictorSize=8192
174 globalPredictorSize=8192
177 localHistoryTableSize=2048
178 localPredictorSize=2048
184 addr_ranges=0:18446744073709551615
186 clk_domain=system.cpu_clk_domain
187 demand_mshr_reserve=1
194 prefetch_on_access=false
197 sequential_access=false
200 tags=system.cpu.dcache.tags
203 cpu_side=system.cpu.dcache_port
204 mem_side=system.cpu.toL2Bus.slave[1]
206 [system.cpu.dcache.tags]
210 clk_domain=system.cpu_clk_domain
213 sequential_access=false
216 [system.cpu.dstage2_mmu]
220 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
224 [system.cpu.dstage2_mmu.stage2_tlb]
230 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
232 [system.cpu.dstage2_mmu.stage2_tlb.walker]
234 clk_domain=system.cpu_clk_domain
237 num_squash_per_cycle=2
246 walker=system.cpu.dtb.walker
248 [system.cpu.dtb.walker]
250 clk_domain=system.cpu_clk_domain
253 num_squash_per_cycle=2
255 port=system.cpu.toL2Bus.slave[3]
257 [system.cpu.executeFuncUnits]
259 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
261 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
263 [system.cpu.executeFuncUnits.funcUnits0]
265 children=opClasses timings
266 cantForwardFromFUIndices=
269 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
271 timings=system.cpu.executeFuncUnits.funcUnits0.timings
273 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
277 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
279 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
284 [system.cpu.executeFuncUnits.funcUnits0.timings]
291 extraCommitLatExpr=Null
294 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
295 srcRegsRelativeLats=2
298 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
303 [system.cpu.executeFuncUnits.funcUnits1]
305 children=opClasses timings
306 cantForwardFromFUIndices=
309 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
311 timings=system.cpu.executeFuncUnits.funcUnits1.timings
313 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
317 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
319 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
324 [system.cpu.executeFuncUnits.funcUnits1.timings]
331 extraCommitLatExpr=Null
334 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
335 srcRegsRelativeLats=2
338 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
343 [system.cpu.executeFuncUnits.funcUnits2]
345 children=opClasses timings
346 cantForwardFromFUIndices=
349 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
351 timings=system.cpu.executeFuncUnits.funcUnits2.timings
353 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
357 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
359 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
364 [system.cpu.executeFuncUnits.funcUnits2.timings]
371 extraCommitLatExpr=Null
374 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
375 srcRegsRelativeLats=0
378 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
383 [system.cpu.executeFuncUnits.funcUnits3]
386 cantForwardFromFUIndices=
389 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
393 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
397 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
399 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
404 [system.cpu.executeFuncUnits.funcUnits4]
406 children=opClasses timings
407 cantForwardFromFUIndices=
410 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
412 timings=system.cpu.executeFuncUnits.funcUnits4.timings
414 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
416 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
418 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
420 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
425 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
430 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
435 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
440 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
445 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
450 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
455 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
460 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
465 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
470 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
475 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
480 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
485 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
490 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
495 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
500 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
505 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
510 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
515 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
520 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
525 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
530 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
533 opClass=SimdFloatMisc
535 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
538 opClass=SimdFloatMult
540 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
543 opClass=SimdFloatMultAcc
545 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
548 opClass=SimdFloatSqrt
550 [system.cpu.executeFuncUnits.funcUnits4.timings]
553 description=FloatSimd
557 extraCommitLatExpr=Null
560 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
561 srcRegsRelativeLats=2
564 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
569 [system.cpu.executeFuncUnits.funcUnits5]
571 children=opClasses timings
572 cantForwardFromFUIndices=
575 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
577 timings=system.cpu.executeFuncUnits.funcUnits5.timings
579 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
581 children=opClasses0 opClasses1
583 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
585 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
590 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
595 [system.cpu.executeFuncUnits.funcUnits5.timings]
602 extraCommitLatExpr=Null
605 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
606 srcRegsRelativeLats=1
609 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
614 [system.cpu.executeFuncUnits.funcUnits6]
617 cantForwardFromFUIndices=
620 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
624 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
626 children=opClasses0 opClasses1
628 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
630 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
635 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
643 addr_ranges=0:18446744073709551615
645 clk_domain=system.cpu_clk_domain
646 demand_mshr_reserve=1
653 prefetch_on_access=false
656 sequential_access=false
659 tags=system.cpu.icache.tags
662 cpu_side=system.cpu.icache_port
663 mem_side=system.cpu.toL2Bus.slave[0]
665 [system.cpu.icache.tags]
669 clk_domain=system.cpu_clk_domain
672 sequential_access=false
675 [system.cpu.interrupts]
685 id_aa64dfr0_el1=1052678
689 id_aa64mmfr0_el1=15728642
709 [system.cpu.istage2_mmu]
713 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
717 [system.cpu.istage2_mmu.stage2_tlb]
723 walker=system.cpu.istage2_mmu.stage2_tlb.walker
725 [system.cpu.istage2_mmu.stage2_tlb.walker]
727 clk_domain=system.cpu_clk_domain
730 num_squash_per_cycle=2
739 walker=system.cpu.itb.walker
741 [system.cpu.itb.walker]
743 clk_domain=system.cpu_clk_domain
746 num_squash_per_cycle=2
748 port=system.cpu.toL2Bus.slave[2]
753 addr_ranges=0:18446744073709551615
755 clk_domain=system.cpu_clk_domain
756 demand_mshr_reserve=1
763 prefetch_on_access=false
766 sequential_access=false
769 tags=system.cpu.l2cache.tags
772 cpu_side=system.cpu.toL2Bus.master[0]
773 mem_side=system.membus.slave[2]
775 [system.cpu.l2cache.tags]
779 clk_domain=system.cpu_clk_domain
782 sequential_access=false
787 clk_domain=system.cpu_clk_domain
793 snoop_response_latency=1
795 use_default_range=false
797 master=system.cpu.l2cache.cpu_side
798 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
804 [system.cpu_clk_domain]
810 voltage_domain=system.voltage_domain
812 [system.dvfs_handler]
817 sys_clk_domain=system.clk_domain
818 transition_latency=100000000
827 clk_domain=system.clk_domain
832 use_default_range=true
834 default=system.realview.pciconfig.pio
835 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
836 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
841 addr_ranges=2147483648:2415919103
843 clk_domain=system.clk_domain
844 demand_mshr_reserve=1
851 prefetch_on_access=false
854 sequential_access=false
857 tags=system.iocache.tags
860 cpu_side=system.iobus.master[27]
861 mem_side=system.membus.slave[3]
863 [system.iocache.tags]
867 clk_domain=system.clk_domain
870 sequential_access=false
875 children=badaddr_responder
876 clk_domain=system.clk_domain
882 snoop_response_latency=4
884 use_default_range=false
886 default=system.membus.badaddr_responder.pio
887 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
888 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
890 [system.membus.badaddr_responder]
892 clk_domain=system.clk_domain
900 ret_data32=4294967295
901 ret_data64=18446744073709551615
906 pio=system.membus.default
935 addr_mapping=RoRaBaCoCh
936 bank_groups_per_rank=0
940 clk_domain=system.clk_domain
941 conf_table_reported=true
943 device_rowbuffer_size=1024
944 device_size=536870912
949 max_accesses_per_row=16
950 mem_sched_policy=frfcfs
951 min_writes_per_switch=16
953 page_policy=open_adaptive
954 range=2147483648:2415919103
957 static_backend_latency=10000
958 static_frontend_latency=10000
981 write_high_thresh_perc=85
982 write_low_thresh_perc=50
983 port=system.membus.master[5]
987 children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
989 intrctrl=system.intrctrl
990 pci_cfg_base=805306368
991 pci_cfg_gen_offsets=false
995 [system.realview.aaci_fake]
998 clk_domain=system.clk_domain
1004 pio=system.iobus.master[18]
1006 [system.realview.cf_ctrl]
1045 MSICAPMsgUpperAddr=0
1046 MSICAPNextCapability=0
1050 MSIXCAPNextCapability=0
1060 PMCAPNextCapability=0
1065 PXCAPDevCapabilities=0
1072 PXCAPNextCapability=0
1080 clk_domain=system.clk_domain
1081 config_latency=20000
1090 platform=system.realview
1092 config=system.iobus.master[9]
1093 dma=system.iobus.slave[2]
1094 pio=system.iobus.master[8]
1096 [system.realview.clcd]
1099 clk_domain=system.clk_domain
1102 gic=system.realview.gic
1108 vnc=system.vncserver
1109 dma=system.iobus.slave[1]
1110 pio=system.iobus.master[4]
1112 [system.realview.energy_ctrl]
1114 clk_domain=system.clk_domain
1115 dvfs_handler=system.dvfs_handler
1120 pio=system.iobus.master[22]
1122 [system.realview.ethernet]
1161 MSICAPMsgUpperAddr=0
1162 MSICAPNextCapability=0
1166 MSIXCAPNextCapability=0
1176 PMCAPNextCapability=0
1181 PXCAPDevCapabilities=0
1188 PXCAPNextCapability=0
1194 SubsystemVendorID=32902
1196 clk_domain=system.clk_domain
1197 config_latency=20000
1199 fetch_comp_delay=10000
1201 hardware_address=00:90:00:00:00:01
1208 platform=system.realview
1209 rx_desc_cache_size=64
1213 tx_desc_cache_size=64
1218 config=system.iobus.master[26]
1219 dma=system.iobus.slave[4]
1220 pio=system.iobus.master[25]
1222 [system.realview.generic_timer]
1225 gic=system.realview.gic
1230 [system.realview.gic]
1232 clk_domain=system.clk_domain
1236 dist_pio_delay=10000
1240 platform=system.realview
1242 pio=system.membus.master[2]
1244 [system.realview.hdlcd]
1247 clk_domain=system.clk_domain
1250 gic=system.realview.gic
1256 vnc=system.vncserver
1257 workaround_swap_rb=true
1258 dma=system.membus.slave[0]
1259 pio=system.iobus.master[5]
1261 [system.realview.ide]
1300 MSICAPMsgUpperAddr=0
1301 MSICAPNextCapability=0
1305 MSIXCAPNextCapability=0
1315 PMCAPNextCapability=0
1320 PXCAPDevCapabilities=0
1327 PXCAPNextCapability=0
1335 clk_domain=system.clk_domain
1336 config_latency=20000
1345 platform=system.realview
1347 config=system.iobus.master[24]
1348 dma=system.iobus.slave[3]
1349 pio=system.iobus.master[23]
1351 [system.realview.kmi0]
1354 clk_domain=system.clk_domain
1356 gic=system.realview.gic
1363 vnc=system.vncserver
1364 pio=system.iobus.master[6]
1366 [system.realview.kmi1]
1369 clk_domain=system.clk_domain
1371 gic=system.realview.gic
1378 vnc=system.vncserver
1379 pio=system.iobus.master[7]
1381 [system.realview.l2x0_fake]
1383 clk_domain=system.clk_domain
1391 ret_data32=4294967295
1392 ret_data64=18446744073709551615
1397 pio=system.iobus.master[12]
1399 [system.realview.lan_fake]
1401 clk_domain=system.clk_domain
1409 ret_data32=4294967295
1410 ret_data64=18446744073709551615
1415 pio=system.iobus.master[19]
1417 [system.realview.local_cpu_timer]
1419 clk_domain=system.clk_domain
1421 gic=system.realview.gic
1427 pio=system.membus.master[4]
1429 [system.realview.mmc_fake]
1432 clk_domain=system.clk_domain
1438 pio=system.iobus.master[21]
1440 [system.realview.nvmem]
1443 clk_domain=system.clk_domain
1444 conf_table_reported=false
1451 port=system.membus.master[1]
1453 [system.realview.pciconfig]
1456 clk_domain=system.clk_domain
1460 platform=system.realview
1463 pio=system.iobus.default
1465 [system.realview.realview_io]
1467 clk_domain=system.clk_domain
1475 pio=system.iobus.master[1]
1477 [system.realview.rtc]
1480 clk_domain=system.clk_domain
1482 gic=system.realview.gic
1488 time=Thu Jan 1 00:00:00 2009
1489 pio=system.iobus.master[10]
1491 [system.realview.sp810_fake]
1494 clk_domain=system.clk_domain
1500 pio=system.iobus.master[16]
1502 [system.realview.timer0]
1505 clk_domain=system.clk_domain
1509 gic=system.realview.gic
1515 pio=system.iobus.master[2]
1517 [system.realview.timer1]
1520 clk_domain=system.clk_domain
1524 gic=system.realview.gic
1530 pio=system.iobus.master[3]
1532 [system.realview.uart]
1534 clk_domain=system.clk_domain
1537 gic=system.realview.gic
1542 platform=system.realview
1544 terminal=system.terminal
1545 pio=system.iobus.master[0]
1547 [system.realview.uart1_fake]
1550 clk_domain=system.clk_domain
1556 pio=system.iobus.master[13]
1558 [system.realview.uart2_fake]
1561 clk_domain=system.clk_domain
1567 pio=system.iobus.master[14]
1569 [system.realview.uart3_fake]
1572 clk_domain=system.clk_domain
1578 pio=system.iobus.master[15]
1580 [system.realview.usb_fake]
1582 clk_domain=system.clk_domain
1590 ret_data32=4294967295
1591 ret_data64=18446744073709551615
1596 pio=system.iobus.master[20]
1598 [system.realview.vgic]
1600 clk_domain=system.clk_domain
1602 gic=system.realview.gic
1605 platform=system.realview
1609 pio=system.membus.master[3]
1611 [system.realview.vram]
1614 clk_domain=system.clk_domain
1615 conf_table_reported=false
1621 range=402653184:436207615
1622 port=system.iobus.master[11]
1624 [system.realview.watchdog_fake]
1627 clk_domain=system.clk_domain
1633 pio=system.iobus.master[17]
1638 intr_control=system.intrctrl
1650 [system.voltage_domain]