b2af2f1b43910e67406d4fa1f08fa9ce2e1b40a0
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
15 boot_loader=/dist/m5/system/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17 boot_release_addr=65528
19 clk_domain=system.clk_domain
20 dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
25 gic_cpu_addr=738205696
26 have_generic_timer=false
27 have_large_asid_64=false
30 have_virtualization=false
31 highest_el_is_64=false
33 kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34 kernel_addr_check=true
35 load_addr_mask=268435455
36 load_offset=2147483648
37 machine_type=VExpress_EMM
39 mem_ranges=2147483648:2415919103
40 memories=system.physmem system.realview.nvmem system.realview.vram
41 mmap_using_noreserve=false
47 readfile=/z/stever/hg/gem5/tests/halt.sh
50 work_begin_ckpt_count=0
51 work_begin_cpu_id_exit=-1
52 work_begin_exit_count=0
53 work_cpus_ckpt_count=0
57 system_port=system.membus.slave[1]
61 clk_domain=system.clk_domain
64 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
67 master=system.iobus.slave[0]
68 slave=system.membus.master[0]
76 image=system.cf0.image
81 child=system.cf0.image.child
87 [system.cf0.image.child]
90 image_file=/dist/m5/system/disks/linux-aarch32-ael.img
99 voltage_domain=system.voltage_domain
103 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
104 branchPred=system.cpu.branchPred
106 clk_domain=system.cpu_clk_domain
108 decodeCycleInput=true
109 decodeInputBufferSize=3
111 decodeToExecuteForwardDelay=1
112 do_checkpoint_insts=true
114 do_statistics_insts=true
115 dstage2_mmu=system.cpu.dstage2_mmu
119 executeAllowEarlyMemoryIssue=true
122 executeCycleInput=true
123 executeFuncUnits=system.cpu.executeFuncUnits
124 executeInputBufferSize=7
127 executeLSQMaxStoreBufferStoresPerCycle=2
128 executeLSQRequestsQueueSize=1
129 executeLSQStoreBufferSize=5
130 executeLSQTransfersQueueSize=2
131 executeMaxAccessesInMemory=2
132 executeMemoryCommitLimit=1
133 executeMemoryIssueLimit=1
135 executeSetTraceTimeOnCommit=true
136 executeSetTraceTimeOnIssue=false
138 fetch1LineSnapWidth=0
140 fetch1ToFetch2BackwardDelay=1
141 fetch1ToFetch2ForwardDelay=1
142 fetch2CycleInput=true
143 fetch2InputBufferSize=2
144 fetch2ToDecodeForwardDelay=1
146 function_trace_start=0
147 interrupts=system.cpu.interrupts
149 istage2_mmu=system.cpu.istage2_mmu
151 max_insts_all_threads=0
152 max_insts_any_thread=0
153 max_loads_all_threads=0
154 max_loads_any_thread=0
158 simpoint_start_insts=
162 tracer=system.cpu.tracer
164 dcache_port=system.cpu.dcache.cpu_side
165 icache_port=system.cpu.icache.cpu_side
167 [system.cpu.branchPred]
173 choicePredictorSize=8192
176 globalPredictorSize=8192
179 localHistoryTableSize=2048
180 localPredictorSize=2048
187 addr_ranges=0:18446744073709551615
189 clk_domain=system.cpu_clk_domain
190 demand_mshr_reserve=1
197 prefetch_on_access=false
200 sequential_access=false
203 tags=system.cpu.dcache.tags
207 cpu_side=system.cpu.dcache_port
208 mem_side=system.cpu.toL2Bus.slave[1]
210 [system.cpu.dcache.tags]
214 clk_domain=system.cpu_clk_domain
217 sequential_access=false
220 [system.cpu.dstage2_mmu]
224 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
228 [system.cpu.dstage2_mmu.stage2_tlb]
234 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
236 [system.cpu.dstage2_mmu.stage2_tlb.walker]
238 clk_domain=system.cpu_clk_domain
241 num_squash_per_cycle=2
250 walker=system.cpu.dtb.walker
252 [system.cpu.dtb.walker]
254 clk_domain=system.cpu_clk_domain
257 num_squash_per_cycle=2
259 port=system.cpu.toL2Bus.slave[3]
261 [system.cpu.executeFuncUnits]
263 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
265 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
267 [system.cpu.executeFuncUnits.funcUnits0]
269 children=opClasses timings
270 cantForwardFromFUIndices=
273 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
275 timings=system.cpu.executeFuncUnits.funcUnits0.timings
277 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
281 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
283 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
288 [system.cpu.executeFuncUnits.funcUnits0.timings]
295 extraCommitLatExpr=Null
298 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
299 srcRegsRelativeLats=2
302 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
307 [system.cpu.executeFuncUnits.funcUnits1]
309 children=opClasses timings
310 cantForwardFromFUIndices=
313 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
315 timings=system.cpu.executeFuncUnits.funcUnits1.timings
317 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
321 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
323 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
328 [system.cpu.executeFuncUnits.funcUnits1.timings]
335 extraCommitLatExpr=Null
338 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
339 srcRegsRelativeLats=2
342 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
347 [system.cpu.executeFuncUnits.funcUnits2]
349 children=opClasses timings
350 cantForwardFromFUIndices=
353 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
355 timings=system.cpu.executeFuncUnits.funcUnits2.timings
357 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
361 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
363 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
368 [system.cpu.executeFuncUnits.funcUnits2.timings]
375 extraCommitLatExpr=Null
378 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
379 srcRegsRelativeLats=0
382 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
387 [system.cpu.executeFuncUnits.funcUnits3]
390 cantForwardFromFUIndices=
393 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
397 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
401 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
403 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
408 [system.cpu.executeFuncUnits.funcUnits4]
410 children=opClasses timings
411 cantForwardFromFUIndices=
414 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
416 timings=system.cpu.executeFuncUnits.funcUnits4.timings
418 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
420 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
422 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
424 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
429 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
434 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
439 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
444 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
449 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
454 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
459 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
464 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
469 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
474 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
479 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
484 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
489 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
494 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
499 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
504 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
509 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
514 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
519 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
524 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
529 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
534 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
537 opClass=SimdFloatMisc
539 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
542 opClass=SimdFloatMult
544 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
547 opClass=SimdFloatMultAcc
549 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
552 opClass=SimdFloatSqrt
554 [system.cpu.executeFuncUnits.funcUnits4.timings]
557 description=FloatSimd
561 extraCommitLatExpr=Null
564 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
565 srcRegsRelativeLats=2
568 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
573 [system.cpu.executeFuncUnits.funcUnits5]
575 children=opClasses timings
576 cantForwardFromFUIndices=
579 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
581 timings=system.cpu.executeFuncUnits.funcUnits5.timings
583 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
585 children=opClasses0 opClasses1
587 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
589 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
594 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
599 [system.cpu.executeFuncUnits.funcUnits5.timings]
606 extraCommitLatExpr=Null
609 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
610 srcRegsRelativeLats=1
613 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
618 [system.cpu.executeFuncUnits.funcUnits6]
621 cantForwardFromFUIndices=
624 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
628 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
630 children=opClasses0 opClasses1
632 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
634 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
639 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
647 addr_ranges=0:18446744073709551615
649 clk_domain=system.cpu_clk_domain
650 demand_mshr_reserve=1
657 prefetch_on_access=false
660 sequential_access=false
663 tags=system.cpu.icache.tags
667 cpu_side=system.cpu.icache_port
668 mem_side=system.cpu.toL2Bus.slave[0]
670 [system.cpu.icache.tags]
674 clk_domain=system.cpu_clk_domain
677 sequential_access=false
680 [system.cpu.interrupts]
690 id_aa64dfr0_el1=1052678
694 id_aa64mmfr0_el1=15728642
714 [system.cpu.istage2_mmu]
718 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
722 [system.cpu.istage2_mmu.stage2_tlb]
728 walker=system.cpu.istage2_mmu.stage2_tlb.walker
730 [system.cpu.istage2_mmu.stage2_tlb.walker]
732 clk_domain=system.cpu_clk_domain
735 num_squash_per_cycle=2
744 walker=system.cpu.itb.walker
746 [system.cpu.itb.walker]
748 clk_domain=system.cpu_clk_domain
751 num_squash_per_cycle=2
753 port=system.cpu.toL2Bus.slave[2]
758 addr_ranges=0:18446744073709551615
760 clk_domain=system.cpu_clk_domain
761 demand_mshr_reserve=1
768 prefetch_on_access=false
771 sequential_access=false
774 tags=system.cpu.l2cache.tags
778 cpu_side=system.cpu.toL2Bus.master[0]
779 mem_side=system.membus.slave[2]
781 [system.cpu.l2cache.tags]
785 clk_domain=system.cpu_clk_domain
788 sequential_access=false
793 clk_domain=system.cpu_clk_domain
799 snoop_response_latency=1
801 use_default_range=false
803 master=system.cpu.l2cache.cpu_side
804 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
810 [system.cpu_clk_domain]
816 voltage_domain=system.voltage_domain
818 [system.dvfs_handler]
823 sys_clk_domain=system.clk_domain
824 transition_latency=100000000
833 clk_domain=system.clk_domain
838 use_default_range=true
840 default=system.realview.pciconfig.pio
841 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
842 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
847 addr_ranges=2147483648:2415919103
849 clk_domain=system.clk_domain
850 demand_mshr_reserve=1
857 prefetch_on_access=false
860 sequential_access=false
863 tags=system.iocache.tags
867 cpu_side=system.iobus.master[27]
868 mem_side=system.membus.slave[3]
870 [system.iocache.tags]
874 clk_domain=system.clk_domain
877 sequential_access=false
882 children=badaddr_responder
883 clk_domain=system.clk_domain
889 snoop_response_latency=4
891 use_default_range=false
893 default=system.membus.badaddr_responder.pio
894 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
895 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
897 [system.membus.badaddr_responder]
899 clk_domain=system.clk_domain
907 ret_data32=4294967295
908 ret_data64=18446744073709551615
913 pio=system.membus.default
942 addr_mapping=RoRaBaCoCh
943 bank_groups_per_rank=0
947 clk_domain=system.clk_domain
948 conf_table_reported=true
950 device_rowbuffer_size=1024
951 device_size=536870912
956 max_accesses_per_row=16
957 mem_sched_policy=frfcfs
958 min_writes_per_switch=16
960 page_policy=open_adaptive
961 range=2147483648:2415919103
964 static_backend_latency=10000
965 static_frontend_latency=10000
988 write_high_thresh_perc=85
989 write_low_thresh_perc=50
990 port=system.membus.master[5]
994 children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
996 intrctrl=system.intrctrl
997 pci_cfg_base=805306368
998 pci_cfg_gen_offsets=false
1002 [system.realview.aaci_fake]
1005 clk_domain=system.clk_domain
1011 pio=system.iobus.master[18]
1013 [system.realview.cf_ctrl]
1052 MSICAPMsgUpperAddr=0
1053 MSICAPNextCapability=0
1057 MSIXCAPNextCapability=0
1067 PMCAPNextCapability=0
1072 PXCAPDevCapabilities=0
1079 PXCAPNextCapability=0
1087 clk_domain=system.clk_domain
1088 config_latency=20000
1097 platform=system.realview
1099 config=system.iobus.master[9]
1100 dma=system.iobus.slave[2]
1101 pio=system.iobus.master[8]
1103 [system.realview.clcd]
1106 clk_domain=system.clk_domain
1109 gic=system.realview.gic
1115 vnc=system.vncserver
1116 dma=system.iobus.slave[1]
1117 pio=system.iobus.master[4]
1119 [system.realview.energy_ctrl]
1121 clk_domain=system.clk_domain
1122 dvfs_handler=system.dvfs_handler
1127 pio=system.iobus.master[22]
1129 [system.realview.ethernet]
1168 MSICAPMsgUpperAddr=0
1169 MSICAPNextCapability=0
1173 MSIXCAPNextCapability=0
1183 PMCAPNextCapability=0
1188 PXCAPDevCapabilities=0
1195 PXCAPNextCapability=0
1201 SubsystemVendorID=32902
1203 clk_domain=system.clk_domain
1204 config_latency=20000
1206 fetch_comp_delay=10000
1208 hardware_address=00:90:00:00:00:01
1215 platform=system.realview
1216 rx_desc_cache_size=64
1220 tx_desc_cache_size=64
1225 config=system.iobus.master[26]
1226 dma=system.iobus.slave[4]
1227 pio=system.iobus.master[25]
1229 [system.realview.generic_timer]
1232 gic=system.realview.gic
1236 [system.realview.gic]
1238 clk_domain=system.clk_domain
1242 dist_pio_delay=10000
1247 platform=system.realview
1249 pio=system.membus.master[2]
1251 [system.realview.hdlcd]
1254 clk_domain=system.clk_domain
1257 gic=system.realview.gic
1263 vnc=system.vncserver
1264 dma=system.membus.slave[0]
1265 pio=system.iobus.master[5]
1267 [system.realview.ide]
1306 MSICAPMsgUpperAddr=0
1307 MSICAPNextCapability=0
1311 MSIXCAPNextCapability=0
1321 PMCAPNextCapability=0
1326 PXCAPDevCapabilities=0
1333 PXCAPNextCapability=0
1341 clk_domain=system.clk_domain
1342 config_latency=20000
1351 platform=system.realview
1353 config=system.iobus.master[24]
1354 dma=system.iobus.slave[3]
1355 pio=system.iobus.master[23]
1357 [system.realview.kmi0]
1360 clk_domain=system.clk_domain
1362 gic=system.realview.gic
1369 vnc=system.vncserver
1370 pio=system.iobus.master[6]
1372 [system.realview.kmi1]
1375 clk_domain=system.clk_domain
1377 gic=system.realview.gic
1384 vnc=system.vncserver
1385 pio=system.iobus.master[7]
1387 [system.realview.l2x0_fake]
1389 clk_domain=system.clk_domain
1397 ret_data32=4294967295
1398 ret_data64=18446744073709551615
1403 pio=system.iobus.master[12]
1405 [system.realview.lan_fake]
1407 clk_domain=system.clk_domain
1415 ret_data32=4294967295
1416 ret_data64=18446744073709551615
1421 pio=system.iobus.master[19]
1423 [system.realview.local_cpu_timer]
1425 clk_domain=system.clk_domain
1427 gic=system.realview.gic
1433 pio=system.membus.master[3]
1435 [system.realview.mmc_fake]
1438 clk_domain=system.clk_domain
1444 pio=system.iobus.master[21]
1446 [system.realview.nvmem]
1449 clk_domain=system.clk_domain
1450 conf_table_reported=false
1457 port=system.membus.master[1]
1459 [system.realview.pciconfig]
1462 clk_domain=system.clk_domain
1466 platform=system.realview
1469 pio=system.iobus.default
1471 [system.realview.realview_io]
1473 clk_domain=system.clk_domain
1481 pio=system.iobus.master[1]
1483 [system.realview.rtc]
1486 clk_domain=system.clk_domain
1488 gic=system.realview.gic
1494 time=Thu Jan 1 00:00:00 2009
1495 pio=system.iobus.master[10]
1497 [system.realview.sp810_fake]
1500 clk_domain=system.clk_domain
1506 pio=system.iobus.master[16]
1508 [system.realview.timer0]
1511 clk_domain=system.clk_domain
1515 gic=system.realview.gic
1521 pio=system.iobus.master[2]
1523 [system.realview.timer1]
1526 clk_domain=system.clk_domain
1530 gic=system.realview.gic
1536 pio=system.iobus.master[3]
1538 [system.realview.uart]
1540 clk_domain=system.clk_domain
1543 gic=system.realview.gic
1548 platform=system.realview
1550 terminal=system.terminal
1551 pio=system.iobus.master[0]
1553 [system.realview.uart1_fake]
1556 clk_domain=system.clk_domain
1562 pio=system.iobus.master[13]
1564 [system.realview.uart2_fake]
1567 clk_domain=system.clk_domain
1573 pio=system.iobus.master[14]
1575 [system.realview.uart3_fake]
1578 clk_domain=system.clk_domain
1584 pio=system.iobus.master[15]
1586 [system.realview.usb_fake]
1588 clk_domain=system.clk_domain
1596 ret_data32=4294967295
1597 ret_data64=18446744073709551615
1602 pio=system.iobus.master[20]
1604 [system.realview.vgic]
1606 clk_domain=system.clk_domain
1608 gic=system.realview.gic
1611 platform=system.realview
1615 pio=system.membus.master[4]
1617 [system.realview.vram]
1620 clk_domain=system.clk_domain
1621 conf_table_reported=false
1627 range=402653184:436207615
1628 port=system.iobus.master[11]
1630 [system.realview.watchdog_fake]
1633 clk_domain=system.clk_domain
1639 pio=system.iobus.master[17]
1644 intr_control=system.intrctrl
1656 [system.voltage_domain]