tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=MinorCPU
 115 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=system.cpu.branchPred
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 decodeCycleInput=true
 121 decodeInputBufferSize=3
 122 decodeInputWidth=2
 123 decodeToExecuteForwardDelay=1
 124 default_p_state=UNDEFINED
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu.dstage2_mmu
 129 dtb=system.cpu.dtb
 130 enableIdling=true
 131 eventq_index=0
 132 executeAllowEarlyMemoryIssue=true
 133 executeBranchDelay=1
 134 executeCommitLimit=2
 135 executeCycleInput=true
 136 executeFuncUnits=system.cpu.executeFuncUnits
 137 executeInputBufferSize=7
 138 executeInputWidth=2
 139 executeIssueLimit=2
 140 executeLSQMaxStoreBufferStoresPerCycle=2
 141 executeLSQRequestsQueueSize=1
 142 executeLSQStoreBufferSize=5
 143 executeLSQTransfersQueueSize=2
 144 executeMaxAccessesInMemory=2
 145 executeMemoryCommitLimit=1
 146 executeMemoryIssueLimit=1
 147 executeMemoryWidth=0
 148 executeSetTraceTimeOnCommit=true
 149 executeSetTraceTimeOnIssue=false
 150 fetch1FetchLimit=1
 151 fetch1LineSnapWidth=0
 152 fetch1LineWidth=0
 153 fetch1ToFetch2BackwardDelay=1
 154 fetch1ToFetch2ForwardDelay=1
 155 fetch2CycleInput=true
 156 fetch2InputBufferSize=2
 157 fetch2ToDecodeForwardDelay=1
 158 function_trace=false
 159 function_trace_start=0
 160 interrupts=system.cpu.interrupts
 161 isa=system.cpu.isa
 162 istage2_mmu=system.cpu.istage2_mmu
 163 itb=system.cpu.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 numThreads=1
 169 p_state_clk_gate_bins=20
 170 p_state_clk_gate_max=1000000000000
 171 p_state_clk_gate_min=1000
 172 power_model=Null
 173 profile=0
 174 progress_interval=0
 175 simpoint_start_insts=
 176 socket_id=0
 177 switched_out=false
 178 syscallRetryLatency=10000
 179 system=system
 180 threadPolicy=RoundRobin
 181 tracer=system.cpu.tracer
 182 workload=
 183 dcache_port=system.cpu.dcache.cpu_side
 184 icache_port=system.cpu.icache.cpu_side
 185
 186 [system.cpu.branchPred]
 187 type=TournamentBP
 188 BTBEntries=4096
 189 BTBTagSize=16
 190 RASSize=16
 191 choiceCtrBits=2
 192 choicePredictorSize=8192
 193 eventq_index=0
 194 globalCtrBits=2
 195 globalPredictorSize=8192
 196 indirectHashGHR=true
 197 indirectHashTargets=true
 198 indirectPathLength=3
 199 indirectSets=256
 200 indirectTagSize=16
 201 indirectWays=2
 202 instShiftAmt=2
 203 localCtrBits=2
 204 localHistoryTableSize=2048
 205 localPredictorSize=2048
 206 numThreads=1
 207 useIndirect=true
 208
 209 [system.cpu.dcache]
 210 type=Cache
 211 children=tags
 212 addr_ranges=0:18446744073709551615:0:0:0:0
 213 assoc=4
 214 clk_domain=system.cpu_clk_domain
 215 clusivity=mostly_incl
 216 data_latency=2
 217 default_p_state=UNDEFINED
 218 demand_mshr_reserve=1
 219 eventq_index=0
 220 is_read_only=false
 221 max_miss_count=0
 222 mshrs=4
 223 p_state_clk_gate_bins=20
 224 p_state_clk_gate_max=1000000000000
 225 p_state_clk_gate_min=1000
 226 power_model=Null
 227 prefetch_on_access=false
 228 prefetcher=Null
 229 response_latency=2
 230 sequential_access=false
 231 size=32768
 232 system=system
 233 tag_latency=2
 234 tags=system.cpu.dcache.tags
 235 tgts_per_mshr=20
 236 write_buffers=8
 237 writeback_clean=false
 238 cpu_side=system.cpu.dcache_port
 239 mem_side=system.cpu.toL2Bus.slave[1]
 240
 241 [system.cpu.dcache.tags]
 242 type=LRU
 243 assoc=4
 244 block_size=64
 245 clk_domain=system.cpu_clk_domain
 246 data_latency=2
 247 default_p_state=UNDEFINED
 248 eventq_index=0
 249 p_state_clk_gate_bins=20
 250 p_state_clk_gate_max=1000000000000
 251 p_state_clk_gate_min=1000
 252 power_model=Null
 253 sequential_access=false
 254 size=32768
 255 tag_latency=2
 256
 257 [system.cpu.dstage2_mmu]
 258 type=ArmStage2MMU
 259 children=stage2_tlb
 260 eventq_index=0
 261 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 262 sys=system
 263 tlb=system.cpu.dtb
 264
 265 [system.cpu.dstage2_mmu.stage2_tlb]
 266 type=ArmTLB
 267 children=walker
 268 eventq_index=0
 269 is_stage2=true
 270 size=32
 271 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 272
 273 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 274 type=ArmTableWalker
 275 clk_domain=system.cpu_clk_domain
 276 default_p_state=UNDEFINED
 277 eventq_index=0
 278 is_stage2=true
 279 num_squash_per_cycle=2
 280 p_state_clk_gate_bins=20
 281 p_state_clk_gate_max=1000000000000
 282 p_state_clk_gate_min=1000
 283 power_model=Null
 284 sys=system
 285
 286 [system.cpu.dtb]
 287 type=ArmTLB
 288 children=walker
 289 eventq_index=0
 290 is_stage2=false
 291 size=64
 292 walker=system.cpu.dtb.walker
 293
 294 [system.cpu.dtb.walker]
 295 type=ArmTableWalker
 296 clk_domain=system.cpu_clk_domain
 297 default_p_state=UNDEFINED
 298 eventq_index=0
 299 is_stage2=false
 300 num_squash_per_cycle=2
 301 p_state_clk_gate_bins=20
 302 p_state_clk_gate_max=1000000000000
 303 p_state_clk_gate_min=1000
 304 power_model=Null
 305 sys=system
 306 port=system.cpu.toL2Bus.slave[3]
 307
 308 [system.cpu.executeFuncUnits]
 309 type=MinorFUPool
 310 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 311 eventq_index=0
 312 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 313
 314 [system.cpu.executeFuncUnits.funcUnits0]
 315 type=MinorFU
 316 children=opClasses timings
 317 cantForwardFromFUIndices=
 318 eventq_index=0
 319 issueLat=1
 320 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 321 opLat=3
 322 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 323
 324 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 325 type=MinorOpClassSet
 326 children=opClasses
 327 eventq_index=0
 328 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 329
 330 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 331 type=MinorOpClass
 332 eventq_index=0
 333 opClass=IntAlu
 334
 335 [system.cpu.executeFuncUnits.funcUnits0.timings]
 336 type=MinorFUTiming
 337 children=opClasses
 338 description=Int
 339 eventq_index=0
 340 extraAssumedLat=0
 341 extraCommitLat=0
 342 extraCommitLatExpr=Null
 343 mask=0
 344 match=0
 345 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 346 srcRegsRelativeLats=2
 347 suppress=false
 348
 349 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 350 type=MinorOpClassSet
 351 eventq_index=0
 352 opClasses=
 353
 354 [system.cpu.executeFuncUnits.funcUnits1]
 355 type=MinorFU
 356 children=opClasses timings
 357 cantForwardFromFUIndices=
 358 eventq_index=0
 359 issueLat=1
 360 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 361 opLat=3
 362 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 363
 364 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 365 type=MinorOpClassSet
 366 children=opClasses
 367 eventq_index=0
 368 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 369
 370 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 371 type=MinorOpClass
 372 eventq_index=0
 373 opClass=IntAlu
 374
 375 [system.cpu.executeFuncUnits.funcUnits1.timings]
 376 type=MinorFUTiming
 377 children=opClasses
 378 description=Int
 379 eventq_index=0
 380 extraAssumedLat=0
 381 extraCommitLat=0
 382 extraCommitLatExpr=Null
 383 mask=0
 384 match=0
 385 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 386 srcRegsRelativeLats=2
 387 suppress=false
 388
 389 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 390 type=MinorOpClassSet
 391 eventq_index=0
 392 opClasses=
 393
 394 [system.cpu.executeFuncUnits.funcUnits2]
 395 type=MinorFU
 396 children=opClasses timings
 397 cantForwardFromFUIndices=
 398 eventq_index=0
 399 issueLat=1
 400 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 401 opLat=3
 402 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 403
 404 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 405 type=MinorOpClassSet
 406 children=opClasses
 407 eventq_index=0
 408 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 409
 410 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 411 type=MinorOpClass
 412 eventq_index=0
 413 opClass=IntMult
 414
 415 [system.cpu.executeFuncUnits.funcUnits2.timings]
 416 type=MinorFUTiming
 417 children=opClasses
 418 description=Mul
 419 eventq_index=0
 420 extraAssumedLat=0
 421 extraCommitLat=0
 422 extraCommitLatExpr=Null
 423 mask=0
 424 match=0
 425 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 426 srcRegsRelativeLats=0
 427 suppress=false
 428
 429 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 430 type=MinorOpClassSet
 431 eventq_index=0
 432 opClasses=
 433
 434 [system.cpu.executeFuncUnits.funcUnits3]
 435 type=MinorFU
 436 children=opClasses
 437 cantForwardFromFUIndices=
 438 eventq_index=0
 439 issueLat=9
 440 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 441 opLat=9
 442 timings=
 443
 444 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 445 type=MinorOpClassSet
 446 children=opClasses
 447 eventq_index=0
 448 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 449
 450 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 451 type=MinorOpClass
 452 eventq_index=0
 453 opClass=IntDiv
 454
 455 [system.cpu.executeFuncUnits.funcUnits4]
 456 type=MinorFU
 457 children=opClasses timings
 458 cantForwardFromFUIndices=
 459 eventq_index=0
 460 issueLat=1
 461 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 462 opLat=6
 463 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 464
 465 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 466 type=MinorOpClassSet
 467 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
 468 eventq_index=0
 469 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
 470
 471 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 472 type=MinorOpClass
 473 eventq_index=0
 474 opClass=FloatAdd
 475
 476 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 477 type=MinorOpClass
 478 eventq_index=0
 479 opClass=FloatCmp
 480
 481 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 482 type=MinorOpClass
 483 eventq_index=0
 484 opClass=FloatCvt
 485
 486 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 487 type=MinorOpClass
 488 eventq_index=0
 489 opClass=FloatMisc
 490
 491 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 492 type=MinorOpClass
 493 eventq_index=0
 494 opClass=FloatMult
 495
 496 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 497 type=MinorOpClass
 498 eventq_index=0
 499 opClass=FloatMultAcc
 500
 501 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 502 type=MinorOpClass
 503 eventq_index=0
 504 opClass=FloatDiv
 505
 506 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 507 type=MinorOpClass
 508 eventq_index=0
 509 opClass=FloatSqrt
 510
 511 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 512 type=MinorOpClass
 513 eventq_index=0
 514 opClass=SimdAdd
 515
 516 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 517 type=MinorOpClass
 518 eventq_index=0
 519 opClass=SimdAddAcc
 520
 521 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 522 type=MinorOpClass
 523 eventq_index=0
 524 opClass=SimdAlu
 525
 526 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 527 type=MinorOpClass
 528 eventq_index=0
 529 opClass=SimdCmp
 530
 531 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 532 type=MinorOpClass
 533 eventq_index=0
 534 opClass=SimdCvt
 535
 536 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 537 type=MinorOpClass
 538 eventq_index=0
 539 opClass=SimdMisc
 540
 541 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 542 type=MinorOpClass
 543 eventq_index=0
 544 opClass=SimdMult
 545
 546 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 547 type=MinorOpClass
 548 eventq_index=0
 549 opClass=SimdMultAcc
 550
 551 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 552 type=MinorOpClass
 553 eventq_index=0
 554 opClass=SimdShift
 555
 556 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 557 type=MinorOpClass
 558 eventq_index=0
 559 opClass=SimdShiftAcc
 560
 561 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 562 type=MinorOpClass
 563 eventq_index=0
 564 opClass=SimdSqrt
 565
 566 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 567 type=MinorOpClass
 568 eventq_index=0
 569 opClass=SimdFloatAdd
 570
 571 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 572 type=MinorOpClass
 573 eventq_index=0
 574 opClass=SimdFloatAlu
 575
 576 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 577 type=MinorOpClass
 578 eventq_index=0
 579 opClass=SimdFloatCmp
 580
 581 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 582 type=MinorOpClass
 583 eventq_index=0
 584 opClass=SimdFloatCvt
 585
 586 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 587 type=MinorOpClass
 588 eventq_index=0
 589 opClass=SimdFloatDiv
 590
 591 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 592 type=MinorOpClass
 593 eventq_index=0
 594 opClass=SimdFloatMisc
 595
 596 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 597 type=MinorOpClass
 598 eventq_index=0
 599 opClass=SimdFloatMult
 600
 601 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
 602 type=MinorOpClass
 603 eventq_index=0
 604 opClass=SimdFloatMultAcc
 605
 606 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
 607 type=MinorOpClass
 608 eventq_index=0
 609 opClass=SimdFloatSqrt
 610
 611 [system.cpu.executeFuncUnits.funcUnits4.timings]
 612 type=MinorFUTiming
 613 children=opClasses
 614 description=FloatSimd
 615 eventq_index=0
 616 extraAssumedLat=0
 617 extraCommitLat=0
 618 extraCommitLatExpr=Null
 619 mask=0
 620 match=0
 621 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 622 srcRegsRelativeLats=2
 623 suppress=false
 624
 625 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 626 type=MinorOpClassSet
 627 eventq_index=0
 628 opClasses=
 629
 630 [system.cpu.executeFuncUnits.funcUnits5]
 631 type=MinorFU
 632 children=opClasses timings
 633 cantForwardFromFUIndices=
 634 eventq_index=0
 635 issueLat=1
 636 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 637 opLat=1
 638 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 639
 640 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 641 type=MinorOpClassSet
 642 children=opClasses0 opClasses1 opClasses2 opClasses3
 643 eventq_index=0
 644 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
 645
 646 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 647 type=MinorOpClass
 648 eventq_index=0
 649 opClass=MemRead
 650
 651 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 652 type=MinorOpClass
 653 eventq_index=0
 654 opClass=MemWrite
 655
 656 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
 657 type=MinorOpClass
 658 eventq_index=0
 659 opClass=FloatMemRead
 660
 661 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
 662 type=MinorOpClass
 663 eventq_index=0
 664 opClass=FloatMemWrite
 665
 666 [system.cpu.executeFuncUnits.funcUnits5.timings]
 667 type=MinorFUTiming
 668 children=opClasses
 669 description=Mem
 670 eventq_index=0
 671 extraAssumedLat=2
 672 extraCommitLat=0
 673 extraCommitLatExpr=Null
 674 mask=0
 675 match=0
 676 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 677 srcRegsRelativeLats=1
 678 suppress=false
 679
 680 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 681 type=MinorOpClassSet
 682 eventq_index=0
 683 opClasses=
 684
 685 [system.cpu.executeFuncUnits.funcUnits6]
 686 type=MinorFU
 687 children=opClasses
 688 cantForwardFromFUIndices=
 689 eventq_index=0
 690 issueLat=1
 691 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 692 opLat=1
 693 timings=
 694
 695 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 696 type=MinorOpClassSet
 697 children=opClasses0 opClasses1
 698 eventq_index=0
 699 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 700
 701 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 702 type=MinorOpClass
 703 eventq_index=0
 704 opClass=IprAccess
 705
 706 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 707 type=MinorOpClass
 708 eventq_index=0
 709 opClass=InstPrefetch
 710
 711 [system.cpu.icache]
 712 type=Cache
 713 children=tags
 714 addr_ranges=0:18446744073709551615:0:0:0:0
 715 assoc=1
 716 clk_domain=system.cpu_clk_domain
 717 clusivity=mostly_incl
 718 data_latency=2
 719 default_p_state=UNDEFINED
 720 demand_mshr_reserve=1
 721 eventq_index=0
 722 is_read_only=true
 723 max_miss_count=0
 724 mshrs=4
 725 p_state_clk_gate_bins=20
 726 p_state_clk_gate_max=1000000000000
 727 p_state_clk_gate_min=1000
 728 power_model=Null
 729 prefetch_on_access=false
 730 prefetcher=Null
 731 response_latency=2
 732 sequential_access=false
 733 size=32768
 734 system=system
 735 tag_latency=2
 736 tags=system.cpu.icache.tags
 737 tgts_per_mshr=20
 738 write_buffers=8
 739 writeback_clean=true
 740 cpu_side=system.cpu.icache_port
 741 mem_side=system.cpu.toL2Bus.slave[0]
 742
 743 [system.cpu.icache.tags]
 744 type=LRU
 745 assoc=1
 746 block_size=64
 747 clk_domain=system.cpu_clk_domain
 748 data_latency=2
 749 default_p_state=UNDEFINED
 750 eventq_index=0
 751 p_state_clk_gate_bins=20
 752 p_state_clk_gate_max=1000000000000
 753 p_state_clk_gate_min=1000
 754 power_model=Null
 755 sequential_access=false
 756 size=32768
 757 tag_latency=2
 758
 759 [system.cpu.interrupts]
 760 type=ArmInterrupts
 761 eventq_index=0
 762
 763 [system.cpu.isa]
 764 type=ArmISA
 765 decoderFlavour=Generic
 766 eventq_index=0
 767 fpsid=1090793632
 768 id_aa64afr0_el1=0
 769 id_aa64afr1_el1=0
 770 id_aa64dfr0_el1=1052678
 771 id_aa64dfr1_el1=0
 772 id_aa64isar0_el1=0
 773 id_aa64isar1_el1=0
 774 id_aa64mmfr0_el1=15728642
 775 id_aa64mmfr1_el1=0
 776 id_isar0=34607377
 777 id_isar1=34677009
 778 id_isar2=555950401
 779 id_isar3=17899825
 780 id_isar4=268501314
 781 id_isar5=0
 782 id_mmfr0=270536963
 783 id_mmfr1=0
 784 id_mmfr2=19070976
 785 id_mmfr3=34611729
 786 midr=1091551472
 787 pmu=Null
 788 system=system
 789
 790 [system.cpu.istage2_mmu]
 791 type=ArmStage2MMU
 792 children=stage2_tlb
 793 eventq_index=0
 794 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 795 sys=system
 796 tlb=system.cpu.itb
 797
 798 [system.cpu.istage2_mmu.stage2_tlb]
 799 type=ArmTLB
 800 children=walker
 801 eventq_index=0
 802 is_stage2=true
 803 size=32
 804 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 805
 806 [system.cpu.istage2_mmu.stage2_tlb.walker]
 807 type=ArmTableWalker
 808 clk_domain=system.cpu_clk_domain
 809 default_p_state=UNDEFINED
 810 eventq_index=0
 811 is_stage2=true
 812 num_squash_per_cycle=2
 813 p_state_clk_gate_bins=20
 814 p_state_clk_gate_max=1000000000000
 815 p_state_clk_gate_min=1000
 816 power_model=Null
 817 sys=system
 818
 819 [system.cpu.itb]
 820 type=ArmTLB
 821 children=walker
 822 eventq_index=0
 823 is_stage2=false
 824 size=64
 825 walker=system.cpu.itb.walker
 826
 827 [system.cpu.itb.walker]
 828 type=ArmTableWalker
 829 clk_domain=system.cpu_clk_domain
 830 default_p_state=UNDEFINED
 831 eventq_index=0
 832 is_stage2=false
 833 num_squash_per_cycle=2
 834 p_state_clk_gate_bins=20
 835 p_state_clk_gate_max=1000000000000
 836 p_state_clk_gate_min=1000
 837 power_model=Null
 838 sys=system
 839 port=system.cpu.toL2Bus.slave[2]
 840
 841 [system.cpu.l2cache]
 842 type=Cache
 843 children=tags
 844 addr_ranges=0:18446744073709551615:0:0:0:0
 845 assoc=8
 846 clk_domain=system.cpu_clk_domain
 847 clusivity=mostly_incl
 848 data_latency=20
 849 default_p_state=UNDEFINED
 850 demand_mshr_reserve=1
 851 eventq_index=0
 852 is_read_only=false
 853 max_miss_count=0
 854 mshrs=20
 855 p_state_clk_gate_bins=20
 856 p_state_clk_gate_max=1000000000000
 857 p_state_clk_gate_min=1000
 858 power_model=Null
 859 prefetch_on_access=false
 860 prefetcher=Null
 861 response_latency=20
 862 sequential_access=false
 863 size=4194304
 864 system=system
 865 tag_latency=20
 866 tags=system.cpu.l2cache.tags
 867 tgts_per_mshr=12
 868 write_buffers=8
 869 writeback_clean=false
 870 cpu_side=system.cpu.toL2Bus.master[0]
 871 mem_side=system.membus.slave[2]
 872
 873 [system.cpu.l2cache.tags]
 874 type=LRU
 875 assoc=8
 876 block_size=64
 877 clk_domain=system.cpu_clk_domain
 878 data_latency=20
 879 default_p_state=UNDEFINED
 880 eventq_index=0
 881 p_state_clk_gate_bins=20
 882 p_state_clk_gate_max=1000000000000
 883 p_state_clk_gate_min=1000
 884 power_model=Null
 885 sequential_access=false
 886 size=4194304
 887 tag_latency=20
 888
 889 [system.cpu.toL2Bus]
 890 type=CoherentXBar
 891 children=snoop_filter
 892 clk_domain=system.cpu_clk_domain
 893 default_p_state=UNDEFINED
 894 eventq_index=0
 895 forward_latency=0
 896 frontend_latency=1
 897 p_state_clk_gate_bins=20
 898 p_state_clk_gate_max=1000000000000
 899 p_state_clk_gate_min=1000
 900 point_of_coherency=false
 901 power_model=Null
 902 response_latency=1
 903 snoop_filter=system.cpu.toL2Bus.snoop_filter
 904 snoop_response_latency=1
 905 system=system
 906 use_default_range=false
 907 width=32
 908 master=system.cpu.l2cache.cpu_side
 909 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 910
 911 [system.cpu.toL2Bus.snoop_filter]
 912 type=SnoopFilter
 913 eventq_index=0
 914 lookup_latency=0
 915 max_capacity=8388608
 916 system=system
 917
 918 [system.cpu.tracer]
 919 type=ExeTracer
 920 eventq_index=0
 921
 922 [system.cpu_clk_domain]
 923 type=SrcClockDomain
 924 clock=500
 925 domain_id=-1
 926 eventq_index=0
 927 init_perf_level=0
 928 voltage_domain=system.voltage_domain
 929
 930 [system.dvfs_handler]
 931 type=DVFSHandler
 932 domains=
 933 enable=false
 934 eventq_index=0
 935 sys_clk_domain=system.clk_domain
 936 transition_latency=100000000
 937
 938 [system.intrctrl]
 939 type=IntrControl
 940 eventq_index=0
 941 sys=system
 942
 943 [system.iobus]
 944 type=NoncoherentXBar
 945 clk_domain=system.clk_domain
 946 default_p_state=UNDEFINED
 947 eventq_index=0
 948 forward_latency=1
 949 frontend_latency=2
 950 p_state_clk_gate_bins=20
 951 p_state_clk_gate_max=1000000000000
 952 p_state_clk_gate_min=1000
 953 power_model=Null
 954 response_latency=2
 955 use_default_range=false
 956 width=16
 957 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 958 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 959
 960 [system.iocache]
 961 type=Cache
 962 children=tags
 963 addr_ranges=2147483648:2415919103:0:0:0:0
 964 assoc=8
 965 clk_domain=system.clk_domain
 966 clusivity=mostly_incl
 967 data_latency=50
 968 default_p_state=UNDEFINED
 969 demand_mshr_reserve=1
 970 eventq_index=0
 971 is_read_only=false
 972 max_miss_count=0
 973 mshrs=20
 974 p_state_clk_gate_bins=20
 975 p_state_clk_gate_max=1000000000000
 976 p_state_clk_gate_min=1000
 977 power_model=Null
 978 prefetch_on_access=false
 979 prefetcher=Null
 980 response_latency=50
 981 sequential_access=false
 982 size=1024
 983 system=system
 984 tag_latency=50
 985 tags=system.iocache.tags
 986 tgts_per_mshr=12
 987 write_buffers=8
 988 writeback_clean=false
 989 cpu_side=system.iobus.master[25]
 990 mem_side=system.membus.slave[3]
 991
 992 [system.iocache.tags]
 993 type=LRU
 994 assoc=8
 995 block_size=64
 996 clk_domain=system.clk_domain
 997 data_latency=50
 998 default_p_state=UNDEFINED
 999 eventq_index=0
1000 p_state_clk_gate_bins=20
1001 p_state_clk_gate_max=1000000000000
1002 p_state_clk_gate_min=1000
1003 power_model=Null
1004 sequential_access=false
1005 size=1024
1006 tag_latency=50
1007
1008 [system.membus]
1009 type=CoherentXBar
1010 children=badaddr_responder snoop_filter
1011 clk_domain=system.clk_domain
1012 default_p_state=UNDEFINED
1013 eventq_index=0
1014 forward_latency=4
1015 frontend_latency=3
1016 p_state_clk_gate_bins=20
1017 p_state_clk_gate_max=1000000000000
1018 p_state_clk_gate_min=1000
1019 point_of_coherency=true
1020 power_model=Null
1021 response_latency=2
1022 snoop_filter=system.membus.snoop_filter
1023 snoop_response_latency=4
1024 system=system
1025 use_default_range=false
1026 width=16
1027 default=system.membus.badaddr_responder.pio
1028 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1029 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
1030
1031 [system.membus.badaddr_responder]
1032 type=IsaFake
1033 clk_domain=system.clk_domain
1034 default_p_state=UNDEFINED
1035 eventq_index=0
1036 fake_mem=false
1037 p_state_clk_gate_bins=20
1038 p_state_clk_gate_max=1000000000000
1039 p_state_clk_gate_min=1000
1040 pio_addr=0
1041 pio_latency=100000
1042 pio_size=8
1043 power_model=Null
1044 ret_bad_addr=true
1045 ret_data16=65535
1046 ret_data32=4294967295
1047 ret_data64=18446744073709551615
1048 ret_data8=255
1049 system=system
1050 update_data=false
1051 warn_access=warn
1052 pio=system.membus.default
1053
1054 [system.membus.snoop_filter]
1055 type=SnoopFilter
1056 eventq_index=0
1057 lookup_latency=1
1058 max_capacity=8388608
1059 system=system
1060
1061 [system.physmem]
1062 type=DRAMCtrl
1063 IDD0=0.055000
1064 IDD02=0.000000
1065 IDD2N=0.032000
1066 IDD2N2=0.000000
1067 IDD2P0=0.000000
1068 IDD2P02=0.000000
1069 IDD2P1=0.032000
1070 IDD2P12=0.000000
1071 IDD3N=0.038000
1072 IDD3N2=0.000000
1073 IDD3P0=0.000000
1074 IDD3P02=0.000000
1075 IDD3P1=0.038000
1076 IDD3P12=0.000000
1077 IDD4R=0.157000
1078 IDD4R2=0.000000
1079 IDD4W=0.125000
1080 IDD4W2=0.000000
1081 IDD5=0.235000
1082 IDD52=0.000000
1083 IDD6=0.020000
1084 IDD62=0.000000
1085 VDD=1.500000
1086 VDD2=0.000000
1087 activation_limit=4
1088 addr_mapping=RoRaBaCoCh
1089 bank_groups_per_rank=0
1090 banks_per_rank=8
1091 burst_length=8
1092 channels=1
1093 clk_domain=system.clk_domain
1094 conf_table_reported=true
1095 default_p_state=UNDEFINED
1096 device_bus_width=8
1097 device_rowbuffer_size=1024
1098 device_size=536870912
1099 devices_per_rank=8
1100 dll=true
1101 eventq_index=0
1102 in_addr_map=true
1103 kvm_map=true
1104 max_accesses_per_row=16
1105 mem_sched_policy=frfcfs
1106 min_writes_per_switch=16
1107 null=false
1108 p_state_clk_gate_bins=20
1109 p_state_clk_gate_max=1000000000000
1110 p_state_clk_gate_min=1000
1111 page_policy=open_adaptive
1112 power_model=Null
1113 range=2147483648:2415919103:0:0:0:0
1114 ranks_per_channel=2
1115 read_buffer_size=32
1116 static_backend_latency=10000
1117 static_frontend_latency=10000
1118 tBURST=5000
1119 tCCD_L=0
1120 tCK=1250
1121 tCL=13750
1122 tCS=2500
1123 tRAS=35000
1124 tRCD=13750
1125 tREFI=7800000
1126 tRFC=260000
1127 tRP=13750
1128 tRRD=6000
1129 tRRD_L=0
1130 tRTP=7500
1131 tRTW=2500
1132 tWR=15000
1133 tWTR=7500
1134 tXAW=30000
1135 tXP=6000
1136 tXPDLL=0
1137 tXS=270000
1138 tXSDLL=0
1139 write_buffer_size=64
1140 write_high_thresh_perc=85
1141 write_low_thresh_perc=50
1142 port=system.membus.master[5]
1143
1144 [system.realview]
1145 type=RealView
1146 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1147 eventq_index=0
1148 intrctrl=system.intrctrl
1149 system=system
1150
1151 [system.realview.aaci_fake]
1152 type=AmbaFake
1153 amba_id=0
1154 clk_domain=system.clk_domain
1155 default_p_state=UNDEFINED
1156 eventq_index=0
1157 ignore_access=false
1158 p_state_clk_gate_bins=20
1159 p_state_clk_gate_max=1000000000000
1160 p_state_clk_gate_min=1000
1161 pio_addr=470024192
1162 pio_latency=100000
1163 power_model=Null
1164 system=system
1165 pio=system.iobus.master[18]
1166
1167 [system.realview.cf_ctrl]
1168 type=IdeController
1169 BAR0=471465984
1170 BAR0LegacyIO=true
1171 BAR0Size=256
1172 BAR1=471466240
1173 BAR1LegacyIO=true
1174 BAR1Size=4096
1175 BAR2=1
1176 BAR2LegacyIO=false
1177 BAR2Size=8
1178 BAR3=1
1179 BAR3LegacyIO=false
1180 BAR3Size=4
1181 BAR4=1
1182 BAR4LegacyIO=false
1183 BAR4Size=16
1184 BAR5=1
1185 BAR5LegacyIO=false
1186 BAR5Size=0
1187 BIST=0
1188 CacheLineSize=0
1189 CapabilityPtr=0
1190 CardbusCIS=0
1191 ClassCode=1
1192 Command=1
1193 DeviceID=28945
1194 ExpansionROM=0
1195 HeaderType=0
1196 InterruptLine=31
1197 InterruptPin=1
1198 LatencyTimer=0
1199 LegacyIOBase=0
1200 MSICAPBaseOffset=0
1201 MSICAPCapId=0
1202 MSICAPMaskBits=0
1203 MSICAPMsgAddr=0
1204 MSICAPMsgCtrl=0
1205 MSICAPMsgData=0
1206 MSICAPMsgUpperAddr=0
1207 MSICAPNextCapability=0
1208 MSICAPPendingBits=0
1209 MSIXCAPBaseOffset=0
1210 MSIXCAPCapId=0
1211 MSIXCAPNextCapability=0
1212 MSIXMsgCtrl=0
1213 MSIXPbaOffset=0
1214 MSIXTableOffset=0
1215 MaximumLatency=0
1216 MinimumGrant=0
1217 PMCAPBaseOffset=0
1218 PMCAPCapId=0
1219 PMCAPCapabilities=0
1220 PMCAPCtrlStatus=0
1221 PMCAPNextCapability=0
1222 PXCAPBaseOffset=0
1223 PXCAPCapId=0
1224 PXCAPCapabilities=0
1225 PXCAPDevCap2=0
1226 PXCAPDevCapabilities=0
1227 PXCAPDevCtrl=0
1228 PXCAPDevCtrl2=0
1229 PXCAPDevStatus=0
1230 PXCAPLinkCap=0
1231 PXCAPLinkCtrl=0
1232 PXCAPLinkStatus=0
1233 PXCAPNextCapability=0
1234 ProgIF=133
1235 Revision=0
1236 Status=640
1237 SubClassCode=1
1238 SubsystemID=0
1239 SubsystemVendorID=0
1240 VendorID=32902
1241 clk_domain=system.clk_domain
1242 config_latency=20000
1243 ctrl_offset=2
1244 default_p_state=UNDEFINED
1245 disks=
1246 eventq_index=0
1247 host=system.realview.pci_host
1248 io_shift=2
1249 p_state_clk_gate_bins=20
1250 p_state_clk_gate_max=1000000000000
1251 p_state_clk_gate_min=1000
1252 pci_bus=2
1253 pci_dev=0
1254 pci_func=0
1255 pio_latency=30000
1256 power_model=Null
1257 system=system
1258 dma=system.iobus.slave[2]
1259 pio=system.iobus.master[9]
1260
1261 [system.realview.clcd]
1262 type=Pl111
1263 amba_id=1315089
1264 clk_domain=system.clk_domain
1265 default_p_state=UNDEFINED
1266 enable_capture=true
1267 eventq_index=0
1268 gic=system.realview.gic
1269 int_num=46
1270 p_state_clk_gate_bins=20
1271 p_state_clk_gate_max=1000000000000
1272 p_state_clk_gate_min=1000
1273 pio_addr=471793664
1274 pio_latency=10000
1275 pixel_clock=41667
1276 power_model=Null
1277 system=system
1278 vnc=system.vncserver
1279 dma=system.iobus.slave[1]
1280 pio=system.iobus.master[5]
1281
1282 [system.realview.dcc]
1283 type=SubSystem
1284 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1285 eventq_index=0
1286 thermal_domain=Null
1287
1288 [system.realview.dcc.osc_cpu]
1289 type=RealViewOsc
1290 dcc=0
1291 device=0
1292 eventq_index=0
1293 freq=16667
1294 parent=system.realview.realview_io
1295 position=0
1296 site=1
1297 voltage_domain=system.voltage_domain
1298
1299 [system.realview.dcc.osc_ddr]
1300 type=RealViewOsc
1301 dcc=0
1302 device=8
1303 eventq_index=0
1304 freq=25000
1305 parent=system.realview.realview_io
1306 position=0
1307 site=1
1308 voltage_domain=system.voltage_domain
1309
1310 [system.realview.dcc.osc_hsbm]
1311 type=RealViewOsc
1312 dcc=0
1313 device=4
1314 eventq_index=0
1315 freq=25000
1316 parent=system.realview.realview_io
1317 position=0
1318 site=1
1319 voltage_domain=system.voltage_domain
1320
1321 [system.realview.dcc.osc_pxl]
1322 type=RealViewOsc
1323 dcc=0
1324 device=5
1325 eventq_index=0
1326 freq=42105
1327 parent=system.realview.realview_io
1328 position=0
1329 site=1
1330 voltage_domain=system.voltage_domain
1331
1332 [system.realview.dcc.osc_smb]
1333 type=RealViewOsc
1334 dcc=0
1335 device=6
1336 eventq_index=0
1337 freq=20000
1338 parent=system.realview.realview_io
1339 position=0
1340 site=1
1341 voltage_domain=system.voltage_domain
1342
1343 [system.realview.dcc.osc_sys]
1344 type=RealViewOsc
1345 dcc=0
1346 device=7
1347 eventq_index=0
1348 freq=16667
1349 parent=system.realview.realview_io
1350 position=0
1351 site=1
1352 voltage_domain=system.voltage_domain
1353
1354 [system.realview.energy_ctrl]
1355 type=EnergyCtrl
1356 clk_domain=system.clk_domain
1357 default_p_state=UNDEFINED
1358 dvfs_handler=system.dvfs_handler
1359 eventq_index=0
1360 p_state_clk_gate_bins=20
1361 p_state_clk_gate_max=1000000000000
1362 p_state_clk_gate_min=1000
1363 pio_addr=470286336
1364 pio_latency=100000
1365 power_model=Null
1366 system=system
1367 pio=system.iobus.master[22]
1368
1369 [system.realview.ethernet]
1370 type=IGbE
1371 BAR0=0
1372 BAR0LegacyIO=false
1373 BAR0Size=131072
1374 BAR1=0
1375 BAR1LegacyIO=false
1376 BAR1Size=0
1377 BAR2=0
1378 BAR2LegacyIO=false
1379 BAR2Size=0
1380 BAR3=0
1381 BAR3LegacyIO=false
1382 BAR3Size=0
1383 BAR4=0
1384 BAR4LegacyIO=false
1385 BAR4Size=0
1386 BAR5=0
1387 BAR5LegacyIO=false
1388 BAR5Size=0
1389 BIST=0
1390 CacheLineSize=0
1391 CapabilityPtr=0
1392 CardbusCIS=0
1393 ClassCode=2
1394 Command=0
1395 DeviceID=4213
1396 ExpansionROM=0
1397 HeaderType=0
1398 InterruptLine=1
1399 InterruptPin=1
1400 LatencyTimer=0
1401 LegacyIOBase=0
1402 MSICAPBaseOffset=0
1403 MSICAPCapId=0
1404 MSICAPMaskBits=0
1405 MSICAPMsgAddr=0
1406 MSICAPMsgCtrl=0
1407 MSICAPMsgData=0
1408 MSICAPMsgUpperAddr=0
1409 MSICAPNextCapability=0
1410 MSICAPPendingBits=0
1411 MSIXCAPBaseOffset=0
1412 MSIXCAPCapId=0
1413 MSIXCAPNextCapability=0
1414 MSIXMsgCtrl=0
1415 MSIXPbaOffset=0
1416 MSIXTableOffset=0
1417 MaximumLatency=0
1418 MinimumGrant=255
1419 PMCAPBaseOffset=0
1420 PMCAPCapId=0
1421 PMCAPCapabilities=0
1422 PMCAPCtrlStatus=0
1423 PMCAPNextCapability=0
1424 PXCAPBaseOffset=0
1425 PXCAPCapId=0
1426 PXCAPCapabilities=0
1427 PXCAPDevCap2=0
1428 PXCAPDevCapabilities=0
1429 PXCAPDevCtrl=0
1430 PXCAPDevCtrl2=0
1431 PXCAPDevStatus=0
1432 PXCAPLinkCap=0
1433 PXCAPLinkCtrl=0
1434 PXCAPLinkStatus=0
1435 PXCAPNextCapability=0
1436 ProgIF=0
1437 Revision=0
1438 Status=0
1439 SubClassCode=0
1440 SubsystemID=4104
1441 SubsystemVendorID=32902
1442 VendorID=32902
1443 clk_domain=system.clk_domain
1444 config_latency=20000
1445 default_p_state=UNDEFINED
1446 eventq_index=0
1447 fetch_comp_delay=10000
1448 fetch_delay=10000
1449 hardware_address=00:90:00:00:00:01
1450 host=system.realview.pci_host
1451 p_state_clk_gate_bins=20
1452 p_state_clk_gate_max=1000000000000
1453 p_state_clk_gate_min=1000
1454 pci_bus=0
1455 pci_dev=0
1456 pci_func=0
1457 phy_epid=896
1458 phy_pid=680
1459 pio_latency=30000
1460 power_model=Null
1461 rx_desc_cache_size=64
1462 rx_fifo_size=393216
1463 rx_write_delay=0
1464 system=system
1465 tx_desc_cache_size=64
1466 tx_fifo_size=393216
1467 tx_read_delay=0
1468 wb_comp_delay=10000
1469 wb_delay=10000
1470 dma=system.iobus.slave[4]
1471 pio=system.iobus.master[24]
1472
1473 [system.realview.generic_timer]
1474 type=GenericTimer
1475 eventq_index=0
1476 gic=system.realview.gic
1477 int_phys=29
1478 int_virt=27
1479 system=system
1480
1481 [system.realview.gic]
1482 type=Pl390
1483 clk_domain=system.clk_domain
1484 cpu_addr=738205696
1485 cpu_pio_delay=10000
1486 default_p_state=UNDEFINED
1487 dist_addr=738201600
1488 dist_pio_delay=10000
1489 eventq_index=0
1490 gem5_extensions=false
1491 int_latency=10000
1492 it_lines=128
1493 p_state_clk_gate_bins=20
1494 p_state_clk_gate_max=1000000000000
1495 p_state_clk_gate_min=1000
1496 platform=system.realview
1497 power_model=Null
1498 system=system
1499 pio=system.membus.master[2]
1500
1501 [system.realview.hdlcd]
1502 type=HDLcd
1503 amba_id=1314816
1504 clk_domain=system.clk_domain
1505 default_p_state=UNDEFINED
1506 enable_capture=true
1507 eventq_index=0
1508 gic=system.realview.gic
1509 int_num=117
1510 p_state_clk_gate_bins=20
1511 p_state_clk_gate_max=1000000000000
1512 p_state_clk_gate_min=1000
1513 pio_addr=721420288
1514 pio_latency=10000
1515 pixel_buffer_size=2048
1516 pixel_chunk=32
1517 power_model=Null
1518 pxl_clk=system.realview.dcc.osc_pxl
1519 system=system
1520 vnc=system.vncserver
1521 workaround_dma_line_count=true
1522 workaround_swap_rb=true
1523 dma=system.membus.slave[0]
1524 pio=system.iobus.master[6]
1525
1526 [system.realview.ide]
1527 type=IdeController
1528 BAR0=1
1529 BAR0LegacyIO=false
1530 BAR0Size=8
1531 BAR1=1
1532 BAR1LegacyIO=false
1533 BAR1Size=4
1534 BAR2=1
1535 BAR2LegacyIO=false
1536 BAR2Size=8
1537 BAR3=1
1538 BAR3LegacyIO=false
1539 BAR3Size=4
1540 BAR4=1
1541 BAR4LegacyIO=false
1542 BAR4Size=16
1543 BAR5=1
1544 BAR5LegacyIO=false
1545 BAR5Size=0
1546 BIST=0
1547 CacheLineSize=0
1548 CapabilityPtr=0
1549 CardbusCIS=0
1550 ClassCode=1
1551 Command=0
1552 DeviceID=28945
1553 ExpansionROM=0
1554 HeaderType=0
1555 InterruptLine=2
1556 InterruptPin=2
1557 LatencyTimer=0
1558 LegacyIOBase=0
1559 MSICAPBaseOffset=0
1560 MSICAPCapId=0
1561 MSICAPMaskBits=0
1562 MSICAPMsgAddr=0
1563 MSICAPMsgCtrl=0
1564 MSICAPMsgData=0
1565 MSICAPMsgUpperAddr=0
1566 MSICAPNextCapability=0
1567 MSICAPPendingBits=0
1568 MSIXCAPBaseOffset=0
1569 MSIXCAPCapId=0
1570 MSIXCAPNextCapability=0
1571 MSIXMsgCtrl=0
1572 MSIXPbaOffset=0
1573 MSIXTableOffset=0
1574 MaximumLatency=0
1575 MinimumGrant=0
1576 PMCAPBaseOffset=0
1577 PMCAPCapId=0
1578 PMCAPCapabilities=0
1579 PMCAPCtrlStatus=0
1580 PMCAPNextCapability=0
1581 PXCAPBaseOffset=0
1582 PXCAPCapId=0
1583 PXCAPCapabilities=0
1584 PXCAPDevCap2=0
1585 PXCAPDevCapabilities=0
1586 PXCAPDevCtrl=0
1587 PXCAPDevCtrl2=0
1588 PXCAPDevStatus=0
1589 PXCAPLinkCap=0
1590 PXCAPLinkCtrl=0
1591 PXCAPLinkStatus=0
1592 PXCAPNextCapability=0
1593 ProgIF=133
1594 Revision=0
1595 Status=640
1596 SubClassCode=1
1597 SubsystemID=0
1598 SubsystemVendorID=0
1599 VendorID=32902
1600 clk_domain=system.clk_domain
1601 config_latency=20000
1602 ctrl_offset=0
1603 default_p_state=UNDEFINED
1604 disks=system.cf0
1605 eventq_index=0
1606 host=system.realview.pci_host
1607 io_shift=0
1608 p_state_clk_gate_bins=20
1609 p_state_clk_gate_max=1000000000000
1610 p_state_clk_gate_min=1000
1611 pci_bus=0
1612 pci_dev=1
1613 pci_func=0
1614 pio_latency=30000
1615 power_model=Null
1616 system=system
1617 dma=system.iobus.slave[3]
1618 pio=system.iobus.master[23]
1619
1620 [system.realview.kmi0]
1621 type=Pl050
1622 amba_id=1314896
1623 clk_domain=system.clk_domain
1624 default_p_state=UNDEFINED
1625 eventq_index=0
1626 gic=system.realview.gic
1627 int_delay=1000000
1628 int_num=44
1629 is_mouse=false
1630 p_state_clk_gate_bins=20
1631 p_state_clk_gate_max=1000000000000
1632 p_state_clk_gate_min=1000
1633 pio_addr=470155264
1634 pio_latency=100000
1635 power_model=Null
1636 system=system
1637 vnc=system.vncserver
1638 pio=system.iobus.master[7]
1639
1640 [system.realview.kmi1]
1641 type=Pl050
1642 amba_id=1314896
1643 clk_domain=system.clk_domain
1644 default_p_state=UNDEFINED
1645 eventq_index=0
1646 gic=system.realview.gic
1647 int_delay=1000000
1648 int_num=45
1649 is_mouse=true
1650 p_state_clk_gate_bins=20
1651 p_state_clk_gate_max=1000000000000
1652 p_state_clk_gate_min=1000
1653 pio_addr=470220800
1654 pio_latency=100000
1655 power_model=Null
1656 system=system
1657 vnc=system.vncserver
1658 pio=system.iobus.master[8]
1659
1660 [system.realview.l2x0_fake]
1661 type=IsaFake
1662 clk_domain=system.clk_domain
1663 default_p_state=UNDEFINED
1664 eventq_index=0
1665 fake_mem=false
1666 p_state_clk_gate_bins=20
1667 p_state_clk_gate_max=1000000000000
1668 p_state_clk_gate_min=1000
1669 pio_addr=739246080
1670 pio_latency=100000
1671 pio_size=4095
1672 power_model=Null
1673 ret_bad_addr=false
1674 ret_data16=65535
1675 ret_data32=4294967295
1676 ret_data64=18446744073709551615
1677 ret_data8=255
1678 system=system
1679 update_data=false
1680 warn_access=
1681 pio=system.iobus.master[12]
1682
1683 [system.realview.lan_fake]
1684 type=IsaFake
1685 clk_domain=system.clk_domain
1686 default_p_state=UNDEFINED
1687 eventq_index=0
1688 fake_mem=false
1689 p_state_clk_gate_bins=20
1690 p_state_clk_gate_max=1000000000000
1691 p_state_clk_gate_min=1000
1692 pio_addr=436207616
1693 pio_latency=100000
1694 pio_size=65535
1695 power_model=Null
1696 ret_bad_addr=false
1697 ret_data16=65535
1698 ret_data32=4294967295
1699 ret_data64=18446744073709551615
1700 ret_data8=255
1701 system=system
1702 update_data=false
1703 warn_access=
1704 pio=system.iobus.master[19]
1705
1706 [system.realview.local_cpu_timer]
1707 type=CpuLocalTimer
1708 clk_domain=system.clk_domain
1709 default_p_state=UNDEFINED
1710 eventq_index=0
1711 gic=system.realview.gic
1712 int_num_timer=29
1713 int_num_watchdog=30
1714 p_state_clk_gate_bins=20
1715 p_state_clk_gate_max=1000000000000
1716 p_state_clk_gate_min=1000
1717 pio_addr=738721792
1718 pio_latency=100000
1719 power_model=Null
1720 system=system
1721 pio=system.membus.master[4]
1722
1723 [system.realview.mcc]
1724 type=SubSystem
1725 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1726 eventq_index=0
1727 thermal_domain=Null
1728
1729 [system.realview.mcc.osc_clcd]
1730 type=RealViewOsc
1731 dcc=0
1732 device=1
1733 eventq_index=0
1734 freq=42105
1735 parent=system.realview.realview_io
1736 position=0
1737 site=0
1738 voltage_domain=system.voltage_domain
1739
1740 [system.realview.mcc.osc_mcc]
1741 type=RealViewOsc
1742 dcc=0
1743 device=0
1744 eventq_index=0
1745 freq=20000
1746 parent=system.realview.realview_io
1747 position=0
1748 site=0
1749 voltage_domain=system.voltage_domain
1750
1751 [system.realview.mcc.osc_peripheral]
1752 type=RealViewOsc
1753 dcc=0
1754 device=2
1755 eventq_index=0
1756 freq=41667
1757 parent=system.realview.realview_io
1758 position=0
1759 site=0
1760 voltage_domain=system.voltage_domain
1761
1762 [system.realview.mcc.osc_system_bus]
1763 type=RealViewOsc
1764 dcc=0
1765 device=4
1766 eventq_index=0
1767 freq=41667
1768 parent=system.realview.realview_io
1769 position=0
1770 site=0
1771 voltage_domain=system.voltage_domain
1772
1773 [system.realview.mcc.temp_crtl]
1774 type=RealViewTemperatureSensor
1775 dcc=0
1776 device=0
1777 eventq_index=0
1778 parent=system.realview.realview_io
1779 position=0
1780 site=0
1781 system=system
1782
1783 [system.realview.mmc_fake]
1784 type=AmbaFake
1785 amba_id=0
1786 clk_domain=system.clk_domain
1787 default_p_state=UNDEFINED
1788 eventq_index=0
1789 ignore_access=false
1790 p_state_clk_gate_bins=20
1791 p_state_clk_gate_max=1000000000000
1792 p_state_clk_gate_min=1000
1793 pio_addr=470089728
1794 pio_latency=100000
1795 power_model=Null
1796 system=system
1797 pio=system.iobus.master[21]
1798
1799 [system.realview.nvmem]
1800 type=SimpleMemory
1801 bandwidth=73.000000
1802 clk_domain=system.clk_domain
1803 conf_table_reported=false
1804 default_p_state=UNDEFINED
1805 eventq_index=0
1806 in_addr_map=true
1807 kvm_map=true
1808 latency=30000
1809 latency_var=0
1810 null=false
1811 p_state_clk_gate_bins=20
1812 p_state_clk_gate_max=1000000000000
1813 p_state_clk_gate_min=1000
1814 power_model=Null
1815 range=0:67108863:0:0:0:0
1816 port=system.membus.master[1]
1817
1818 [system.realview.pci_host]
1819 type=GenericPciHost
1820 clk_domain=system.clk_domain
1821 conf_base=805306368
1822 conf_device_bits=16
1823 conf_size=268435456
1824 default_p_state=UNDEFINED
1825 eventq_index=0
1826 p_state_clk_gate_bins=20
1827 p_state_clk_gate_max=1000000000000
1828 p_state_clk_gate_min=1000
1829 pci_dma_base=0
1830 pci_mem_base=0
1831 pci_pio_base=0
1832 platform=system.realview
1833 power_model=Null
1834 system=system
1835 pio=system.iobus.master[2]
1836
1837 [system.realview.realview_io]
1838 type=RealViewCtrl
1839 clk_domain=system.clk_domain
1840 default_p_state=UNDEFINED
1841 eventq_index=0
1842 idreg=35979264
1843 p_state_clk_gate_bins=20
1844 p_state_clk_gate_max=1000000000000
1845 p_state_clk_gate_min=1000
1846 pio_addr=469827584
1847 pio_latency=100000
1848 power_model=Null
1849 proc_id0=335544320
1850 proc_id1=335544320
1851 system=system
1852 pio=system.iobus.master[1]
1853
1854 [system.realview.rtc]
1855 type=PL031
1856 amba_id=3412017
1857 clk_domain=system.clk_domain
1858 default_p_state=UNDEFINED
1859 eventq_index=0
1860 gic=system.realview.gic
1861 int_delay=100000
1862 int_num=36
1863 p_state_clk_gate_bins=20
1864 p_state_clk_gate_max=1000000000000
1865 p_state_clk_gate_min=1000
1866 pio_addr=471269376
1867 pio_latency=100000
1868 power_model=Null
1869 system=system
1870 time=Thu Jan  1 00:00:00 2009
1871 pio=system.iobus.master[10]
1872
1873 [system.realview.sp810_fake]
1874 type=AmbaFake
1875 amba_id=0
1876 clk_domain=system.clk_domain
1877 default_p_state=UNDEFINED
1878 eventq_index=0
1879 ignore_access=true
1880 p_state_clk_gate_bins=20
1881 p_state_clk_gate_max=1000000000000
1882 p_state_clk_gate_min=1000
1883 pio_addr=469893120
1884 pio_latency=100000
1885 power_model=Null
1886 system=system
1887 pio=system.iobus.master[16]
1888
1889 [system.realview.timer0]
1890 type=Sp804
1891 amba_id=1316868
1892 clk_domain=system.clk_domain
1893 clock0=1000000
1894 clock1=1000000
1895 default_p_state=UNDEFINED
1896 eventq_index=0
1897 gic=system.realview.gic
1898 int_num0=34
1899 int_num1=34
1900 p_state_clk_gate_bins=20
1901 p_state_clk_gate_max=1000000000000
1902 p_state_clk_gate_min=1000
1903 pio_addr=470876160
1904 pio_latency=100000
1905 power_model=Null
1906 system=system
1907 pio=system.iobus.master[3]
1908
1909 [system.realview.timer1]
1910 type=Sp804
1911 amba_id=1316868
1912 clk_domain=system.clk_domain
1913 clock0=1000000
1914 clock1=1000000
1915 default_p_state=UNDEFINED
1916 eventq_index=0
1917 gic=system.realview.gic
1918 int_num0=35
1919 int_num1=35
1920 p_state_clk_gate_bins=20
1921 p_state_clk_gate_max=1000000000000
1922 p_state_clk_gate_min=1000
1923 pio_addr=470941696
1924 pio_latency=100000
1925 power_model=Null
1926 system=system
1927 pio=system.iobus.master[4]
1928
1929 [system.realview.uart]
1930 type=Pl011
1931 clk_domain=system.clk_domain
1932 default_p_state=UNDEFINED
1933 end_on_eot=false
1934 eventq_index=0
1935 gic=system.realview.gic
1936 int_delay=100000
1937 int_num=37
1938 p_state_clk_gate_bins=20
1939 p_state_clk_gate_max=1000000000000
1940 p_state_clk_gate_min=1000
1941 pio_addr=470351872
1942 pio_latency=100000
1943 platform=system.realview
1944 power_model=Null
1945 system=system
1946 terminal=system.terminal
1947 pio=system.iobus.master[0]
1948
1949 [system.realview.uart1_fake]
1950 type=AmbaFake
1951 amba_id=0
1952 clk_domain=system.clk_domain
1953 default_p_state=UNDEFINED
1954 eventq_index=0
1955 ignore_access=false
1956 p_state_clk_gate_bins=20
1957 p_state_clk_gate_max=1000000000000
1958 p_state_clk_gate_min=1000
1959 pio_addr=470417408
1960 pio_latency=100000
1961 power_model=Null
1962 system=system
1963 pio=system.iobus.master[13]
1964
1965 [system.realview.uart2_fake]
1966 type=AmbaFake
1967 amba_id=0
1968 clk_domain=system.clk_domain
1969 default_p_state=UNDEFINED
1970 eventq_index=0
1971 ignore_access=false
1972 p_state_clk_gate_bins=20
1973 p_state_clk_gate_max=1000000000000
1974 p_state_clk_gate_min=1000
1975 pio_addr=470482944
1976 pio_latency=100000
1977 power_model=Null
1978 system=system
1979 pio=system.iobus.master[14]
1980
1981 [system.realview.uart3_fake]
1982 type=AmbaFake
1983 amba_id=0
1984 clk_domain=system.clk_domain
1985 default_p_state=UNDEFINED
1986 eventq_index=0
1987 ignore_access=false
1988 p_state_clk_gate_bins=20
1989 p_state_clk_gate_max=1000000000000
1990 p_state_clk_gate_min=1000
1991 pio_addr=470548480
1992 pio_latency=100000
1993 power_model=Null
1994 system=system
1995 pio=system.iobus.master[15]
1996
1997 [system.realview.usb_fake]
1998 type=IsaFake
1999 clk_domain=system.clk_domain
2000 default_p_state=UNDEFINED
2001 eventq_index=0
2002 fake_mem=false
2003 p_state_clk_gate_bins=20
2004 p_state_clk_gate_max=1000000000000
2005 p_state_clk_gate_min=1000
2006 pio_addr=452984832
2007 pio_latency=100000
2008 pio_size=131071
2009 power_model=Null
2010 ret_bad_addr=false
2011 ret_data16=65535
2012 ret_data32=4294967295
2013 ret_data64=18446744073709551615
2014 ret_data8=255
2015 system=system
2016 update_data=false
2017 warn_access=
2018 pio=system.iobus.master[20]
2019
2020 [system.realview.vgic]
2021 type=VGic
2022 clk_domain=system.clk_domain
2023 default_p_state=UNDEFINED
2024 eventq_index=0
2025 gic=system.realview.gic
2026 hv_addr=738213888
2027 p_state_clk_gate_bins=20
2028 p_state_clk_gate_max=1000000000000
2029 p_state_clk_gate_min=1000
2030 pio_delay=10000
2031 platform=system.realview
2032 power_model=Null
2033 ppint=25
2034 system=system
2035 vcpu_addr=738222080
2036 pio=system.membus.master[3]
2037
2038 [system.realview.vram]
2039 type=SimpleMemory
2040 bandwidth=73.000000
2041 clk_domain=system.clk_domain
2042 conf_table_reported=false
2043 default_p_state=UNDEFINED
2044 eventq_index=0
2045 in_addr_map=true
2046 kvm_map=true
2047 latency=30000
2048 latency_var=0
2049 null=false
2050 p_state_clk_gate_bins=20
2051 p_state_clk_gate_max=1000000000000
2052 p_state_clk_gate_min=1000
2053 power_model=Null
2054 range=402653184:436207615:0:0:0:0
2055 port=system.iobus.master[11]
2056
2057 [system.realview.watchdog_fake]
2058 type=AmbaFake
2059 amba_id=0
2060 clk_domain=system.clk_domain
2061 default_p_state=UNDEFINED
2062 eventq_index=0
2063 ignore_access=false
2064 p_state_clk_gate_bins=20
2065 p_state_clk_gate_max=1000000000000
2066 p_state_clk_gate_min=1000
2067 pio_addr=470745088
2068 pio_latency=100000
2069 power_model=Null
2070 system=system
2071 pio=system.iobus.master[17]
2072
2073 [system.terminal]
2074 type=Terminal
2075 eventq_index=0
2076 intr_control=system.intrctrl
2077 number=0
2078 output=true
2079 port=3456
2080
2081 [system.vncserver]
2082 type=VncServer
2083 eventq_index=0
2084 frame_capture=false
2085 number=0
2086 port=5900
2087
2088 [system.voltage_domain]
2089 type=VoltageDomain
2090 eventq_index=0
2091 voltage=1.000000
2092