2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.852796 # Number of seconds simulated
4 sim_ticks 2852795541500 # Number of ticks simulated
5 final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 152327 # Simulator instruction rate (inst/s)
8 host_op_rate 184181 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3876544573 # Simulator tick rate (ticks/s)
10 host_mem_usage 573860 # Number of bytes of host memory used
11 host_seconds 735.91 # Real time elapsed on the host
12 sim_insts 112099513 # Number of instructions simulated
13 sim_ops 135541235 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory
20 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory
31 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory
34 system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 169771 # Number of read requests accepted
55 system.physmem.writeReqs 164823 # Number of write requests accepted
56 system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 10712 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 10437 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 10571 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 10533 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 13317 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 10551 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 11242 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 11054 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 10299 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 10415 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 10045 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 9308 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 10198 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 10751 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 10066 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 10147 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 8889 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 8834 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 9167 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 9119 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 8534 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 8844 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 9286 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 9148 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 9024 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 8594 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 8355 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 8781 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 8812 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 8428 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
100 system.physmem.totGap 2852795136500 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 543 # Read request sizes (log2)
104 system.physmem.readPktSize::3 14 # Read request sizes (log2)
105 system.physmem.readPktSize::4 0 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 169214 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111 system.physmem.writePktSize::3 0 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 160442 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes
231 system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads
269 system.physmem.totQLat 1681739444 # Total ticks spent queuing
270 system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM
271 system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers
272 system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst
273 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
274 system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst
275 system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
276 system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
277 system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
278 system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
279 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280 system.physmem.busUtil 0.05 # Data bus utilization in percentage
281 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
282 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
283 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
284 system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
285 system.physmem.readRowHits 140075 # Number of row buffer hits during reads
286 system.physmem.writeRowHits 109026 # Number of row buffer hits during writes
287 system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads
288 system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes
289 system.physmem.avgGap 8526139.55 # Average gap between requests
290 system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
291 system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ)
292 system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ)
293 system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ)
294 system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ)
295 system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
296 system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ)
297 system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ)
298 system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ)
299 system.physmem_0.averagePower 669.449413 # Core power per rank (mW)
300 system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states
301 system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states
302 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
303 system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states
304 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
305 system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ)
306 system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ)
307 system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ)
308 system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ)
309 system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
310 system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ)
311 system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ)
312 system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ)
313 system.physmem_1.averagePower 669.351340 # Core power per rank (mW)
314 system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states
315 system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states
316 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
317 system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states
318 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
319 system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
320 system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
321 system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
322 system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
323 system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
324 system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
325 system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s)
326 system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s)
327 system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s)
328 system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
329 system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
330 system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
331 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
332 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
333 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
334 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
335 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
336 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
337 system.cpu.branchPred.lookups 31028841 # Number of BP lookups
338 system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted
339 system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect
340 system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups
341 system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits
342 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
343 system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage
344 system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target.
345 system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions.
346 system.cpu_clk_domain.clock 500 # Clock period in ticks
347 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
354 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
355 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
356 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
357 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
358 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
359 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
360 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
361 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
362 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
363 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
364 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
365 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
366 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
367 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
368 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
374 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
375 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376 system.cpu.dtb.walker.walks 66007 # Table walker walks requested
377 system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors
378 system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate
379 system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate
380 system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency
381 system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency
382 system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency
383 system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency
384 system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency
385 system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency
386 system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency
387 system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency
388 system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency
389 system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
390 system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
391 system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
392 system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
393 system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency
394 system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
395 system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
396 system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
397 system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated
398 system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated
399 system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated
400 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst
401 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst
403 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst
404 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst
406 system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst
407 system.cpu.dtb.inst_hits 0 # ITB inst hits
408 system.cpu.dtb.inst_misses 0 # ITB inst misses
409 system.cpu.dtb.read_hits 24765986 # DTB read hits
410 system.cpu.dtb.read_misses 59321 # DTB read misses
411 system.cpu.dtb.write_hits 19441821 # DTB write hits
412 system.cpu.dtb.write_misses 6686 # DTB write misses
413 system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
414 system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
415 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
416 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
417 system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
418 system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions
419 system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch
420 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
421 system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions
422 system.cpu.dtb.read_accesses 24825307 # DTB read accesses
423 system.cpu.dtb.write_accesses 19448507 # DTB write accesses
424 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
425 system.cpu.dtb.hits 44207807 # DTB hits
426 system.cpu.dtb.misses 66007 # DTB misses
427 system.cpu.dtb.accesses 44273814 # DTB accesses
428 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
429 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
430 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
431 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
432 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
433 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
434 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
435 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
436 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
437 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
438 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
439 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
440 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
441 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
442 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
443 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
444 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
445 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
446 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
447 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
448 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
449 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
450 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
451 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
452 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
453 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
454 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
455 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
456 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
457 system.cpu.itb.walker.walks 5444 # Table walker walks requested
458 system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors
459 system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate
460 system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate
461 system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency
462 system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency
463 system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency
464 system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
465 system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency
466 system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency
467 system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency
468 system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency
469 system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency
470 system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
471 system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
472 system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
473 system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
474 system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
475 system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
476 system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
477 system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
478 system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
479 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst
481 system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst
482 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
484 system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
485 system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst
486 system.cpu.itb.inst_hits 57608448 # ITB inst hits
487 system.cpu.itb.inst_misses 5444 # ITB inst misses
488 system.cpu.itb.read_hits 0 # DTB read hits
489 system.cpu.itb.read_misses 0 # DTB read misses
490 system.cpu.itb.write_hits 0 # DTB write hits
491 system.cpu.itb.write_misses 0 # DTB write misses
492 system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
493 system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
494 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
495 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
496 system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
497 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
498 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
499 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
500 system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions
501 system.cpu.itb.read_accesses 0 # DTB read accesses
502 system.cpu.itb.write_accesses 0 # DTB write accesses
503 system.cpu.itb.inst_accesses 57613892 # ITB inst accesses
504 system.cpu.itb.hits 57608448 # DTB hits
505 system.cpu.itb.misses 5444 # DTB misses
506 system.cpu.itb.accesses 57613892 # DTB accesses
507 system.cpu.numCycles 315454477 # number of cpu cycles simulated
508 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
509 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
510 system.cpu.committedInsts 112099513 # Number of instructions committed
511 system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed
512 system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit
513 system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
514 system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
515 system.cpu.cpi 2.814058 # CPI: cycles per instruction
516 system.cpu.ipc 0.355359 # IPC: instructions per cycle
517 system.cpu.kern.inst.arm 0 # number of arm instructions executed
518 system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
519 system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked
520 system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped
521 system.cpu.dcache.tags.replacements 842088 # number of replacements
522 system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use
523 system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks.
524 system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks.
525 system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks.
526 system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
527 system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor
528 system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
529 system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
530 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
531 system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
532 system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
533 system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
534 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
535 system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses
536 system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses
537 system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits
538 system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits
539 system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits
540 system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits
541 system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits
542 system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits
543 system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits
544 system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits
545 system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits
546 system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits
547 system.cpu.dcache.demand_hits::cpu.data 41360470 # number of demand (read+write) hits
548 system.cpu.dcache.demand_hits::total 41360470 # number of demand (read+write) hits
549 system.cpu.dcache.overall_hits::cpu.data 41717116 # number of overall hits
550 system.cpu.dcache.overall_hits::total 41717116 # number of overall hits
551 system.cpu.dcache.ReadReq_misses::cpu.data 491782 # number of ReadReq misses
552 system.cpu.dcache.ReadReq_misses::total 491782 # number of ReadReq misses
553 system.cpu.dcache.WriteReq_misses::cpu.data 547820 # number of WriteReq misses
554 system.cpu.dcache.WriteReq_misses::total 547820 # number of WriteReq misses
555 system.cpu.dcache.SoftPFReq_misses::cpu.data 169860 # number of SoftPFReq misses
556 system.cpu.dcache.SoftPFReq_misses::total 169860 # number of SoftPFReq misses
557 system.cpu.dcache.LoadLockedReq_misses::cpu.data 22518 # number of LoadLockedReq misses
558 system.cpu.dcache.LoadLockedReq_misses::total 22518 # number of LoadLockedReq misses
559 system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
560 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
561 system.cpu.dcache.demand_misses::cpu.data 1039602 # number of demand (read+write) misses
562 system.cpu.dcache.demand_misses::total 1039602 # number of demand (read+write) misses
563 system.cpu.dcache.overall_misses::cpu.data 1209462 # number of overall misses
564 system.cpu.dcache.overall_misses::total 1209462 # number of overall misses
565 system.cpu.dcache.ReadReq_miss_latency::cpu.data 7264308005 # number of ReadReq miss cycles
566 system.cpu.dcache.ReadReq_miss_latency::total 7264308005 # number of ReadReq miss cycles
567 system.cpu.dcache.WriteReq_miss_latency::cpu.data 23337097788 # number of WriteReq miss cycles
568 system.cpu.dcache.WriteReq_miss_latency::total 23337097788 # number of WriteReq miss cycles
569 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285724000 # number of LoadLockedReq miss cycles
570 system.cpu.dcache.LoadLockedReq_miss_latency::total 285724000 # number of LoadLockedReq miss cycles
571 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
572 system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
573 system.cpu.dcache.demand_miss_latency::cpu.data 30601405793 # number of demand (read+write) miss cycles
574 system.cpu.dcache.demand_miss_latency::total 30601405793 # number of demand (read+write) miss cycles
575 system.cpu.dcache.overall_miss_latency::cpu.data 30601405793 # number of overall miss cycles
576 system.cpu.dcache.overall_miss_latency::total 30601405793 # number of overall miss cycles
577 system.cpu.dcache.ReadReq_accesses::cpu.data 23566505 # number of ReadReq accesses(hits+misses)
578 system.cpu.dcache.ReadReq_accesses::total 23566505 # number of ReadReq accesses(hits+misses)
579 system.cpu.dcache.WriteReq_accesses::cpu.data 18833567 # number of WriteReq accesses(hits+misses)
580 system.cpu.dcache.WriteReq_accesses::total 18833567 # number of WriteReq accesses(hits+misses)
581 system.cpu.dcache.SoftPFReq_accesses::cpu.data 526506 # number of SoftPFReq accesses(hits+misses)
582 system.cpu.dcache.SoftPFReq_accesses::total 526506 # number of SoftPFReq accesses(hits+misses)
583 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466021 # number of LoadLockedReq accesses(hits+misses)
584 system.cpu.dcache.LoadLockedReq_accesses::total 466021 # number of LoadLockedReq accesses(hits+misses)
585 system.cpu.dcache.StoreCondReq_accesses::cpu.data 460200 # number of StoreCondReq accesses(hits+misses)
586 system.cpu.dcache.StoreCondReq_accesses::total 460200 # number of StoreCondReq accesses(hits+misses)
587 system.cpu.dcache.demand_accesses::cpu.data 42400072 # number of demand (read+write) accesses
588 system.cpu.dcache.demand_accesses::total 42400072 # number of demand (read+write) accesses
589 system.cpu.dcache.overall_accesses::cpu.data 42926578 # number of overall (read+write) accesses
590 system.cpu.dcache.overall_accesses::total 42926578 # number of overall (read+write) accesses
591 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020868 # miss rate for ReadReq accesses
592 system.cpu.dcache.ReadReq_miss_rate::total 0.020868 # miss rate for ReadReq accesses
593 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029087 # miss rate for WriteReq accesses
594 system.cpu.dcache.WriteReq_miss_rate::total 0.029087 # miss rate for WriteReq accesses
595 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322617 # miss rate for SoftPFReq accesses
596 system.cpu.dcache.SoftPFReq_miss_rate::total 0.322617 # miss rate for SoftPFReq accesses
597 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048320 # miss rate for LoadLockedReq accesses
598 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048320 # miss rate for LoadLockedReq accesses
599 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
600 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
601 system.cpu.dcache.demand_miss_rate::cpu.data 0.024519 # miss rate for demand accesses
602 system.cpu.dcache.demand_miss_rate::total 0.024519 # miss rate for demand accesses
603 system.cpu.dcache.overall_miss_rate::cpu.data 0.028175 # miss rate for overall accesses
604 system.cpu.dcache.overall_miss_rate::total 0.028175 # miss rate for overall accesses
605 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14771.398719 # average ReadReq miss latency
606 system.cpu.dcache.ReadReq_avg_miss_latency::total 14771.398719 # average ReadReq miss latency
607 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42599.937549 # average WriteReq miss latency
608 system.cpu.dcache.WriteReq_avg_miss_latency::total 42599.937549 # average WriteReq miss latency
609 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12688.693490 # average LoadLockedReq miss latency
610 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12688.693490 # average LoadLockedReq miss latency
611 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
612 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
613 system.cpu.dcache.demand_avg_miss_latency::cpu.data 29435.693461 # average overall miss latency
614 system.cpu.dcache.demand_avg_miss_latency::total 29435.693461 # average overall miss latency
615 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25301.667843 # average overall miss latency
616 system.cpu.dcache.overall_avg_miss_latency::total 25301.667843 # average overall miss latency
617 system.cpu.dcache.blocked_cycles::no_mshrs 252 # number of cycles access was blocked
618 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
619 system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
620 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
621 system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
622 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
623 system.cpu.dcache.fast_writes 0 # number of fast writes performed
624 system.cpu.dcache.cache_copies 0 # number of cache copies performed
625 system.cpu.dcache.writebacks::writebacks 697883 # number of writebacks
626 system.cpu.dcache.writebacks::total 697883 # number of writebacks
627 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74969 # number of ReadReq MSHR hits
628 system.cpu.dcache.ReadReq_mshr_hits::total 74969 # number of ReadReq MSHR hits
629 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits
630 system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits
631 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14294 # number of LoadLockedReq MSHR hits
632 system.cpu.dcache.LoadLockedReq_mshr_hits::total 14294 # number of LoadLockedReq MSHR hits
633 system.cpu.dcache.demand_mshr_hits::cpu.data 324010 # number of demand (read+write) MSHR hits
634 system.cpu.dcache.demand_mshr_hits::total 324010 # number of demand (read+write) MSHR hits
635 system.cpu.dcache.overall_mshr_hits::cpu.data 324010 # number of overall MSHR hits
636 system.cpu.dcache.overall_mshr_hits::total 324010 # number of overall MSHR hits
637 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416813 # number of ReadReq MSHR misses
638 system.cpu.dcache.ReadReq_mshr_misses::total 416813 # number of ReadReq MSHR misses
639 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298779 # number of WriteReq MSHR misses
640 system.cpu.dcache.WriteReq_mshr_misses::total 298779 # number of WriteReq MSHR misses
641 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121645 # number of SoftPFReq MSHR misses
642 system.cpu.dcache.SoftPFReq_mshr_misses::total 121645 # number of SoftPFReq MSHR misses
643 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8224 # number of LoadLockedReq MSHR misses
644 system.cpu.dcache.LoadLockedReq_mshr_misses::total 8224 # number of LoadLockedReq MSHR misses
645 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
646 system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
647 system.cpu.dcache.demand_mshr_misses::cpu.data 715592 # number of demand (read+write) MSHR misses
648 system.cpu.dcache.demand_mshr_misses::total 715592 # number of demand (read+write) MSHR misses
649 system.cpu.dcache.overall_mshr_misses::cpu.data 837237 # number of overall MSHR misses
650 system.cpu.dcache.overall_mshr_misses::total 837237 # number of overall MSHR misses
651 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable
652 system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable
653 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable
654 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable
655 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
656 system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
657 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5688327646 # number of ReadReq MSHR miss cycles
658 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5688327646 # number of ReadReq MSHR miss cycles
659 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12278776156 # number of WriteReq MSHR miss cycles
660 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12278776156 # number of WriteReq MSHR miss cycles
661 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1560607790 # number of SoftPFReq MSHR miss cycles
662 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1560607790 # number of SoftPFReq MSHR miss cycles
663 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106146500 # number of LoadLockedReq MSHR miss cycles
664 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106146500 # number of LoadLockedReq MSHR miss cycles
665 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
666 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
667 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17967103802 # number of demand (read+write) MSHR miss cycles
668 system.cpu.dcache.demand_mshr_miss_latency::total 17967103802 # number of demand (read+write) MSHR miss cycles
669 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19527711592 # number of overall MSHR miss cycles
670 system.cpu.dcache.overall_mshr_miss_latency::total 19527711592 # number of overall MSHR miss cycles
671 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837082750 # number of ReadReq MSHR uncacheable cycles
672 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837082750 # number of ReadReq MSHR uncacheable cycles
673 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510053000 # number of WriteReq MSHR uncacheable cycles
674 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510053000 # number of WriteReq MSHR uncacheable cycles
675 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10347135750 # number of overall MSHR uncacheable cycles
676 system.cpu.dcache.overall_mshr_uncacheable_latency::total 10347135750 # number of overall MSHR uncacheable cycles
677 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017687 # mshr miss rate for ReadReq accesses
678 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017687 # mshr miss rate for ReadReq accesses
679 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses
680 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses
681 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231042 # mshr miss rate for SoftPFReq accesses
682 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231042 # mshr miss rate for SoftPFReq accesses
683 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017647 # mshr miss rate for LoadLockedReq accesses
684 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017647 # mshr miss rate for LoadLockedReq accesses
685 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
686 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
687 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses
688 system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses
689 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses
690 system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses
691 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency
692 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency
693 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency
694 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency
695 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency
696 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency
697 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency
698 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency
699 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
700 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
701 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # average overall mshr miss latency
702 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25108.027762 # average overall mshr miss latency
703 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23323.994988 # average overall mshr miss latency
704 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23323.994988 # average overall mshr miss latency
705 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187518.721087 # average ReadReq mshr uncacheable latency
706 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187518.721087 # average ReadReq mshr uncacheable latency
707 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163508.429105 # average WriteReq mshr uncacheable latency
708 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163508.429105 # average WriteReq mshr uncacheable latency
709 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176238.451909 # average overall mshr uncacheable latency
710 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency
711 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
712 system.cpu.icache.tags.replacements 2896868 # number of replacements
713 system.cpu.icache.tags.tagsinuse 511.399912 # Cycle average of tags in use
714 system.cpu.icache.tags.total_refs 54702268 # Total number of references to valid blocks.
715 system.cpu.icache.tags.sampled_refs 2897380 # Sample count of references to valid blocks.
716 system.cpu.icache.tags.avg_refs 18.879908 # Average number of references to valid blocks.
717 system.cpu.icache.tags.warmup_cycle 15532248250 # Cycle when the warmup percentage was hit.
718 system.cpu.icache.tags.occ_blocks::cpu.inst 511.399912 # Average occupied blocks per requestor
719 system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy
720 system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy
721 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
722 system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
723 system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
724 system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
725 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
726 system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses
727 system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses
728 system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits
729 system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits
730 system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits
731 system.cpu.icache.demand_hits::total 54702268 # number of demand (read+write) hits
732 system.cpu.icache.overall_hits::cpu.inst 54702268 # number of overall hits
733 system.cpu.icache.overall_hits::total 54702268 # number of overall hits
734 system.cpu.icache.ReadReq_misses::cpu.inst 2897392 # number of ReadReq misses
735 system.cpu.icache.ReadReq_misses::total 2897392 # number of ReadReq misses
736 system.cpu.icache.demand_misses::cpu.inst 2897392 # number of demand (read+write) misses
737 system.cpu.icache.demand_misses::total 2897392 # number of demand (read+write) misses
738 system.cpu.icache.overall_misses::cpu.inst 2897392 # number of overall misses
739 system.cpu.icache.overall_misses::total 2897392 # number of overall misses
740 system.cpu.icache.ReadReq_miss_latency::cpu.inst 39291591662 # number of ReadReq miss cycles
741 system.cpu.icache.ReadReq_miss_latency::total 39291591662 # number of ReadReq miss cycles
742 system.cpu.icache.demand_miss_latency::cpu.inst 39291591662 # number of demand (read+write) miss cycles
743 system.cpu.icache.demand_miss_latency::total 39291591662 # number of demand (read+write) miss cycles
744 system.cpu.icache.overall_miss_latency::cpu.inst 39291591662 # number of overall miss cycles
745 system.cpu.icache.overall_miss_latency::total 39291591662 # number of overall miss cycles
746 system.cpu.icache.ReadReq_accesses::cpu.inst 57599660 # number of ReadReq accesses(hits+misses)
747 system.cpu.icache.ReadReq_accesses::total 57599660 # number of ReadReq accesses(hits+misses)
748 system.cpu.icache.demand_accesses::cpu.inst 57599660 # number of demand (read+write) accesses
749 system.cpu.icache.demand_accesses::total 57599660 # number of demand (read+write) accesses
750 system.cpu.icache.overall_accesses::cpu.inst 57599660 # number of overall (read+write) accesses
751 system.cpu.icache.overall_accesses::total 57599660 # number of overall (read+write) accesses
752 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050302 # miss rate for ReadReq accesses
753 system.cpu.icache.ReadReq_miss_rate::total 0.050302 # miss rate for ReadReq accesses
754 system.cpu.icache.demand_miss_rate::cpu.inst 0.050302 # miss rate for demand accesses
755 system.cpu.icache.demand_miss_rate::total 0.050302 # miss rate for demand accesses
756 system.cpu.icache.overall_miss_rate::cpu.inst 0.050302 # miss rate for overall accesses
757 system.cpu.icache.overall_miss_rate::total 0.050302 # miss rate for overall accesses
758 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13561.020277 # average ReadReq miss latency
759 system.cpu.icache.ReadReq_avg_miss_latency::total 13561.020277 # average ReadReq miss latency
760 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
761 system.cpu.icache.demand_avg_miss_latency::total 13561.020277 # average overall miss latency
762 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
763 system.cpu.icache.overall_avg_miss_latency::total 13561.020277 # average overall miss latency
764 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
765 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
766 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
767 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
768 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
769 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
770 system.cpu.icache.fast_writes 0 # number of fast writes performed
771 system.cpu.icache.cache_copies 0 # number of cache copies performed
772 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897392 # number of ReadReq MSHR misses
773 system.cpu.icache.ReadReq_mshr_misses::total 2897392 # number of ReadReq MSHR misses
774 system.cpu.icache.demand_mshr_misses::cpu.inst 2897392 # number of demand (read+write) MSHR misses
775 system.cpu.icache.demand_mshr_misses::total 2897392 # number of demand (read+write) MSHR misses
776 system.cpu.icache.overall_mshr_misses::cpu.inst 2897392 # number of overall MSHR misses
777 system.cpu.icache.overall_mshr_misses::total 2897392 # number of overall MSHR misses
778 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable
779 system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable
780 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses
781 system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses
782 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34935956838 # number of ReadReq MSHR miss cycles
783 system.cpu.icache.ReadReq_mshr_miss_latency::total 34935956838 # number of ReadReq MSHR miss cycles
784 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34935956838 # number of demand (read+write) MSHR miss cycles
785 system.cpu.icache.demand_mshr_miss_latency::total 34935956838 # number of demand (read+write) MSHR miss cycles
786 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34935956838 # number of overall MSHR miss cycles
787 system.cpu.icache.overall_mshr_miss_latency::total 34935956838 # number of overall MSHR miss cycles
788 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles
789 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles
790 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles
791 system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles
792 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for ReadReq accesses
793 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050302 # mshr miss rate for ReadReq accesses
794 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for demand accesses
795 system.cpu.icache.demand_mshr_miss_rate::total 0.050302 # mshr miss rate for demand accesses
796 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for overall accesses
797 system.cpu.icache.overall_mshr_miss_rate::total 0.050302 # mshr miss rate for overall accesses
798 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.725305 # average ReadReq mshr miss latency
799 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.725305 # average ReadReq mshr miss latency
800 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
801 system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
802 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
803 system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
804 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency
805 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency
806 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency
807 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency
808 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
809 system.cpu.l2cache.tags.replacements 96519 # number of replacements
810 system.cpu.l2cache.tags.tagsinuse 65064.584640 # Cycle average of tags in use
811 system.cpu.l2cache.tags.total_refs 4043303 # Total number of references to valid blocks.
812 system.cpu.l2cache.tags.sampled_refs 161770 # Sample count of references to valid blocks.
813 system.cpu.l2cache.tags.avg_refs 24.994146 # Average number of references to valid blocks.
814 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
815 system.cpu.l2cache.tags.occ_blocks::writebacks 47432.807159 # Average occupied blocks per requestor
816 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.814603 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
818 system.cpu.l2cache.tags.occ_blocks::cpu.inst 12239.354143 # Average occupied blocks per requestor
819 system.cpu.l2cache.tags.occ_blocks::cpu.data 5328.608352 # Average occupied blocks per requestor
820 system.cpu.l2cache.tags.occ_percent::writebacks 0.723767 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000974 # Average percentage of cache occupancy
822 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
823 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186758 # Average percentage of cache occupancy
824 system.cpu.l2cache.tags.occ_percent::cpu.data 0.081308 # Average percentage of cache occupancy
825 system.cpu.l2cache.tags.occ_percent::total 0.992807 # Average percentage of cache occupancy
826 system.cpu.l2cache.tags.occ_task_id_blocks::1023 39 # Occupied blocks per task id
827 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65212 # Occupied blocks per task id
828 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 39 # Occupied blocks per task id
829 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
830 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
831 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2301 # Occupied blocks per task id
832 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6950 # Occupied blocks per task id
833 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55839 # Occupied blocks per task id
834 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000595 # Percentage of cache occupancy per task id
835 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995056 # Percentage of cache occupancy per task id
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837 system.cpu.l2cache.tags.data_accesses 36587667 # Number of data accesses
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846 system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits
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848 system.cpu.l2cache.ReadExReq_hits::total 165019 # number of ReadExReq hits
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919 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70474 # number of overall (read+write) accesses
920 system.cpu.l2cache.overall_accesses::cpu.itb.walker 4501 # number of overall (read+write) accesses
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924 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001660 # miss rate for ReadReq accesses
925 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000222 # miss rate for ReadReq accesses
926 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007935 # miss rate for ReadReq accesses
927 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026085 # miss rate for ReadReq accesses
928 system.cpu.l2cache.ReadReq_miss_rate::total 0.010619 # miss rate for ReadReq accesses
929 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982004 # miss rate for UpgradeReq accesses
930 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982004 # miss rate for UpgradeReq accesses
931 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
932 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
933 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442409 # miss rate for ReadExReq accesses
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935 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001660 # miss rate for demand accesses
936 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000222 # miss rate for demand accesses
937 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007935 # miss rate for demand accesses
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941 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000222 # miss rate for overall accesses
942 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007935 # miss rate for overall accesses
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946 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
947 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80182.590257 # average ReadReq miss latency
948 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83580.735624 # average ReadReq miss latency
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951 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 404.406755 # average UpgradeReq miss latency
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1051 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1052 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442409 # mshr miss rate for ReadExReq accesses
1053 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442409 # mshr miss rate for ReadExReq accesses
1054 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for demand accesses
1055 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for demand accesses
1056 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses
1057 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses
1058 system.cpu.l2cache.demand_mshr_miss_rate::total 0.044072 # mshr miss rate for demand accesses
1059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for overall accesses
1060 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for overall accesses
1061 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses
1062 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses
1063 system.cpu.l2cache.overall_mshr_miss_rate::total 0.044072 # mshr miss rate for overall accesses
1064 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average ReadReq mshr miss latency
1065 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
1066 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67689.004746 # average ReadReq mshr miss latency
1067 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71214.411931 # average ReadReq mshr miss latency
1068 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69055.756834 # average ReadReq mshr miss latency
1069 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17774.445922 # average UpgradeReq mshr miss latency
1070 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17774.445922 # average UpgradeReq mshr miss latency
1071 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
1072 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
1073 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65003.775370 # average ReadExReq mshr miss latency
1074 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65003.775370 # average ReadExReq mshr miss latency
1075 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency
1076 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
1077 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency
1078 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency
1079 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency
1080 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency
1081 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
1082 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency
1083 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency
1084 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency
1085 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency
1086 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173502.602159 # average ReadReq mshr uncacheable latency
1087 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163047.193878 # average ReadReq mshr uncacheable latency
1088 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150503.734184 # average WriteReq mshr uncacheable latency
1089 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150503.734184 # average WriteReq mshr uncacheable latency
1090 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency
1091 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency
1092 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency
1093 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1094 system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution
1095 system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution
1096 system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
1097 system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
1098 system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution
1099 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
1100 system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution
1101 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1102 system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution
1103 system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution
1104 system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution
1105 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes)
1106 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes)
1107 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes)
1108 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes)
1109 system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes)
1110 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes)
1111 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes)
1112 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes)
1113 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes)
1114 system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes)
1115 system.cpu.toL2Bus.snoops 60910 # Total snoops (count)
1116 system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram
1117 system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram
1118 system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram
1119 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1120 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1121 system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram
1122 system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram
1123 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1124 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1125 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1126 system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram
1127 system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks)
1128 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1129 system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks)
1130 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1131 system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks)
1132 system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1133 system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks)
1134 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1135 system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks)
1136 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1137 system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks)
1138 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1139 system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1140 system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1141 system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1142 system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1143 system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1144 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1145 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1146 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1147 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1148 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1149 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1150 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1151 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1152 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1153 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1154 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1155 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1156 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1157 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1158 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1159 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1160 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1161 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1162 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1163 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1164 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1165 system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1166 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
1167 system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
1168 system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
1169 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1170 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1171 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1172 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1173 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1174 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1175 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1176 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1177 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1178 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1179 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1180 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1181 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1182 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1183 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1184 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1185 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1186 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1187 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1188 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
1189 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1190 system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1191 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
1192 system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
1193 system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
1194 system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1195 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1196 system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
1197 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1198 system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
1199 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1200 system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
1201 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1202 system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
1203 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1204 system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
1205 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1206 system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
1207 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1208 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1209 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1210 system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1211 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1212 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1213 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1214 system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
1215 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1216 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1217 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1218 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
1219 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1220 system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1221 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1222 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1223 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1224 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1225 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1226 system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1227 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1228 system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1229 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1230 system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1231 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1232 system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1233 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1234 system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks)
1235 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1236 system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1237 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1238 system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1239 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1240 system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks)
1241 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1242 system.iocache.tags.replacements 36424 # number of replacements
1243 system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use
1244 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1245 system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1246 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1247 system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit.
1248 system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor
1249 system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy
1250 system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy
1251 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1252 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1253 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1254 system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1255 system.iocache.tags.data_accesses 328122 # Number of data accesses
1256 system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1257 system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1258 system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
1259 system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
1260 system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
1261 system.iocache.demand_misses::total 234 # number of demand (read+write) misses
1262 system.iocache.overall_misses::realview.ide 234 # number of overall misses
1263 system.iocache.overall_misses::total 234 # number of overall misses
1264 system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles
1265 system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles
1266 system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles
1267 system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles
1268 system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles
1269 system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles
1270 system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles
1271 system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles
1272 system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1273 system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1274 system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
1275 system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1276 system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
1277 system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
1278 system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
1279 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
1280 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1281 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1282 system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1283 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1284 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1285 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1286 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1287 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1288 system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency
1289 system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency
1290 system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency
1291 system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency
1292 system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
1293 system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency
1294 system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
1295 system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency
1296 system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked
1297 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1298 system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked
1299 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1300 system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked
1301 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1302 system.iocache.fast_writes 0 # number of fast writes performed
1303 system.iocache.cache_copies 0 # number of cache copies performed
1304 system.iocache.writebacks::writebacks 36190 # number of writebacks
1305 system.iocache.writebacks::total 36190 # number of writebacks
1306 system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1307 system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1308 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
1309 system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
1310 system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
1311 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
1312 system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
1313 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
1314 system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles
1315 system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles
1316 system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles
1317 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles
1318 system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles
1319 system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles
1320 system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles
1321 system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles
1322 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1323 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1324 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1325 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1326 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1327 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1328 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1329 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1330 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency
1331 system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency
1332 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency
1333 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency
1334 system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
1335 system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
1336 system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
1337 system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
1338 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1339 system.membus.trans_dist::ReadReq 71735 # Transaction distribution
1340 system.membus.trans_dist::ReadResp 71735 # Transaction distribution
1341 system.membus.trans_dist::WriteReq 27583 # Transaction distribution
1342 system.membus.trans_dist::WriteResp 27583 # Transaction distribution
1343 system.membus.trans_dist::Writeback 124218 # Transaction distribution
1344 system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
1345 system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1346 system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
1347 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1348 system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution
1349 system.membus.trans_dist::ReadExReq 129118 # Transaction distribution
1350 system.membus.trans_dist::ReadExResp 129118 # Transaction distribution
1351 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1352 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
1353 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
1354 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes)
1355 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes)
1356 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
1357 system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
1358 system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes)
1359 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1360 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
1361 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
1362 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes)
1363 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes)
1364 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
1365 system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
1366 system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes)
1367 system.membus.snoops 506 # Total snoops (count)
1368 system.membus.snoop_fanout::samples 393527 # Request fanout histogram
1369 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1370 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1371 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1372 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1373 system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram
1374 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1375 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1376 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1377 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1378 system.membus.snoop_fanout::total 393527 # Request fanout histogram
1379 system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks)
1380 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1381 system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1382 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1383 system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks)
1384 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1385 system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks)
1386 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1387 system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks)
1388 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1389 system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks)
1390 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1391 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1392 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1393 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1394 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1395 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1396 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1397 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1398 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1399 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1400 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1401 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1402 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1403 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1404 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1405 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1406 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1407 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1408 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1409 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1410 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1411 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1412 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1413 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1414 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1415 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1416 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1417 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1418 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1419 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1420 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1421 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1423 ---------- End Simulation Statistics ----------
projects / gem5.git / blob