2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.854926 # Number of seconds simulated
4 sim_ticks 2854925996500 # Number of ticks simulated
5 final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 115917 # Simulator instruction rate (inst/s)
8 host_op_rate 140154 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2954234125 # Simulator tick rate (ticks/s)
10 host_mem_usage 584856 # Number of bytes of host memory used
11 host_seconds 966.38 # Real time elapsed on the host
12 sim_insts 112020669 # Number of instructions simulated
13 sim_ops 135443008 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.dtb.walker 7040 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 1667200 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 9190572 # Number of bytes read from this memory
21 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 10865900 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu.inst 1667200 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::total 1667200 # Number of instructions bytes read from this memory
25 system.physmem.bytes_written::writebacks 7979712 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
27 system.physmem.bytes_written::total 7997236 # Number of bytes written to this memory
28 system.physmem.num_reads::cpu.dtb.walker 110 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.inst 26050 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu.data 144124 # Number of read requests responded to by this memory
32 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
33 system.physmem.num_reads::total 170301 # Number of read requests responded to by this memory
34 system.physmem.num_writes::writebacks 124683 # Number of write requests responded to by this memory
35 system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
36 system.physmem.num_writes::total 129064 # Number of write requests responded to by this memory
37 system.physmem.bw_read::cpu.dtb.walker 2466 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.inst 583973 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu.data 3219198 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::total 3806018 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::cpu.inst 583973 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_inst_read::total 583973 # Instruction read bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::writebacks 2795068 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_write::total 2801206 # Write bandwidth from this memory (bytes/s)
48 system.physmem.bw_total::writebacks 2795068 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.dtb.walker 2466 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.inst 583973 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu.data 3225336 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::total 6607224 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.readReqs 170301 # Number of read requests accepted
56 system.physmem.writeReqs 129064 # Number of write requests accepted
57 system.physmem.readBursts 170301 # Number of DRAM read bursts, including those serviced by the write queue
58 system.physmem.writeBursts 129064 # Number of DRAM write bursts, including those merged in the write queue
59 system.physmem.bytesReadDRAM 10890496 # Total number of bytes read from DRAM
60 system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
61 system.physmem.bytesWritten 8010048 # Total number of bytes written to DRAM
62 system.physmem.bytesReadSys 10865900 # Total read bytes from the system interface side
63 system.physmem.bytesWrittenSys 7997236 # Total written bytes from the system interface side
64 system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
65 system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
66 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67 system.physmem.perBankRdBursts::0 10638 # Per bank write bursts
68 system.physmem.perBankRdBursts::1 10529 # Per bank write bursts
69 system.physmem.perBankRdBursts::2 10665 # Per bank write bursts
70 system.physmem.perBankRdBursts::3 10242 # Per bank write bursts
71 system.physmem.perBankRdBursts::4 13390 # Per bank write bursts
72 system.physmem.perBankRdBursts::5 10196 # Per bank write bursts
73 system.physmem.perBankRdBursts::6 10392 # Per bank write bursts
74 system.physmem.perBankRdBursts::7 10920 # Per bank write bursts
75 system.physmem.perBankRdBursts::8 10199 # Per bank write bursts
76 system.physmem.perBankRdBursts::9 10416 # Per bank write bursts
77 system.physmem.perBankRdBursts::10 10277 # Per bank write bursts
78 system.physmem.perBankRdBursts::11 9652 # Per bank write bursts
79 system.physmem.perBankRdBursts::12 10777 # Per bank write bursts
80 system.physmem.perBankRdBursts::13 11476 # Per bank write bursts
81 system.physmem.perBankRdBursts::14 10256 # Per bank write bursts
82 system.physmem.perBankRdBursts::15 10139 # Per bank write bursts
83 system.physmem.perBankWrBursts::0 7926 # Per bank write bursts
84 system.physmem.perBankWrBursts::1 7916 # Per bank write bursts
85 system.physmem.perBankWrBursts::2 8341 # Per bank write bursts
86 system.physmem.perBankWrBursts::3 7830 # Per bank write bursts
87 system.physmem.perBankWrBursts::4 7635 # Per bank write bursts
88 system.physmem.perBankWrBursts::5 7427 # Per bank write bursts
89 system.physmem.perBankWrBursts::6 7524 # Per bank write bursts
90 system.physmem.perBankWrBursts::7 8090 # Per bank write bursts
91 system.physmem.perBankWrBursts::8 7812 # Per bank write bursts
92 system.physmem.perBankWrBursts::9 7846 # Per bank write bursts
93 system.physmem.perBankWrBursts::10 7622 # Per bank write bursts
94 system.physmem.perBankWrBursts::11 7450 # Per bank write bursts
95 system.physmem.perBankWrBursts::12 8154 # Per bank write bursts
96 system.physmem.perBankWrBursts::13 8593 # Per bank write bursts
97 system.physmem.perBankWrBursts::14 7575 # Per bank write bursts
98 system.physmem.perBankWrBursts::15 7416 # Per bank write bursts
99 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100 system.physmem.numWrRetry 56 # Number of times write queue was full causing retry
101 system.physmem.totGap 2854925546000 # Total gap between requests
102 system.physmem.readPktSize::0 0 # Read request sizes (log2)
103 system.physmem.readPktSize::1 0 # Read request sizes (log2)
104 system.physmem.readPktSize::2 543 # Read request sizes (log2)
105 system.physmem.readPktSize::3 14 # Read request sizes (log2)
106 system.physmem.readPktSize::4 0 # Read request sizes (log2)
107 system.physmem.readPktSize::5 0 # Read request sizes (log2)
108 system.physmem.readPktSize::6 169744 # Read request sizes (log2)
109 system.physmem.writePktSize::0 0 # Write request sizes (log2)
110 system.physmem.writePktSize::1 0 # Write request sizes (log2)
111 system.physmem.writePktSize::2 4381 # Write request sizes (log2)
112 system.physmem.writePktSize::3 0 # Write request sizes (log2)
113 system.physmem.writePktSize::4 0 # Write request sizes (log2)
114 system.physmem.writePktSize::5 0 # Write request sizes (log2)
115 system.physmem.writePktSize::6 124683 # Write request sizes (log2)
116 system.physmem.rdQLenPdf::0 160221 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::1 9636 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
148 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::15 1833 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::16 2641 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::17 5947 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::18 6248 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::19 6539 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::20 6191 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::21 6635 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::22 6984 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::23 7561 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::24 7557 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::25 8594 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::26 9006 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::27 7531 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::30 6851 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::31 6591 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::32 6684 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::34 463 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::35 366 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::44 270 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::45 254 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::46 268 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::47 280 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::48 200 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::54 188 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::56 231 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::60 246 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::61 160 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::63 138 # What write queue length does an incoming req see
212 system.physmem.bytesPerActivate::samples 60414 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::mean 312.849340 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::gmean 185.889118 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::stdev 328.883375 # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::0-127 21657 35.85% 35.85% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::128-255 14616 24.19% 60.04% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::256-383 6864 11.36% 71.40% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::384-511 3516 5.82% 77.22% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::512-639 2636 4.36% 81.59% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::640-767 1611 2.67% 84.25% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::768-895 1067 1.77% 86.02% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::896-1023 953 1.58% 87.60% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::1024-1151 7494 12.40% 100.00% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::total 60414 # Bytes accessed per row activation
226 system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::mean 27.463041 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::stdev 582.417033 # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::0-2047 6195 99.98% 99.98% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes
232 system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::mean 20.199645 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::gmean 18.300177 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::stdev 15.412164 # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::16-19 5485 88.52% 88.52% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::20-23 67 1.08% 89.61% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::24-27 43 0.69% 90.30% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::28-31 35 0.56% 90.87% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::32-35 272 4.39% 95.26% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::36-39 29 0.47% 95.72% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::40-43 8 0.13% 95.85% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::44-47 11 0.18% 96.03% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::48-51 11 0.18% 96.21% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::52-55 3 0.05% 96.26% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::56-59 4 0.06% 96.32% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::60-63 7 0.11% 96.43% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::64-67 138 2.23% 98.66% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::68-71 3 0.05% 98.71% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::72-75 2 0.03% 98.74% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::76-79 7 0.11% 98.85% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::80-83 6 0.10% 98.95% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::88-91 1 0.02% 98.97% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::100-103 1 0.02% 98.98% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::104-107 1 0.02% 99.00% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::108-111 13 0.21% 99.21% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::120-123 2 0.03% 99.24% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::124-127 3 0.05% 99.29% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::128-131 12 0.19% 99.48% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::140-143 3 0.05% 99.69% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::144-147 2 0.03% 99.73% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::148-151 1 0.02% 99.74% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::156-159 1 0.02% 99.76% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::172-175 3 0.05% 99.82% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::180-183 1 0.02% 99.84% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::184-187 1 0.02% 99.85% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::188-191 4 0.06% 99.92% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads
274 system.physmem.totQLat 4595967000 # Total ticks spent queuing
275 system.physmem.totMemAccLat 7786542000 # Total ticks spent from burst creation until serviced by the DRAM
276 system.physmem.totBusLat 850820000 # Total ticks spent in databus transfers
277 system.physmem.avgQLat 27009.04 # Average queueing delay per DRAM burst
278 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
279 system.physmem.avgMemAccLat 45759.04 # Average memory access latency per DRAM burst
280 system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
281 system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
282 system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
283 system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s
284 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
285 system.physmem.busUtil 0.05 # Data bus utilization in percentage
286 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
287 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
288 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
289 system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing
290 system.physmem.readRowHits 140583 # Number of row buffer hits during reads
291 system.physmem.writeRowHits 94323 # Number of row buffer hits during writes
292 system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads
293 system.physmem.writeRowHitRate 75.35 # Row buffer hit rate for writes
294 system.physmem.avgGap 9536604.30 # Average gap between requests
295 system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
296 system.physmem_0.actEnergy 218405460 # Energy for activate commands per rank (pJ)
297 system.physmem_0.preEnergy 116085255 # Energy for precharge commands per rank (pJ)
298 system.physmem_0.readEnergy 620980080 # Energy for read commands per rank (pJ)
299 system.physmem_0.writeEnergy 327236580 # Energy for write commands per rank (pJ)
300 system.physmem_0.refreshEnergy 6016710960.000001 # Energy for refresh commands per rank (pJ)
301 system.physmem_0.actBackEnergy 4587085260 # Energy for active background per rank (pJ)
302 system.physmem_0.preBackEnergy 376629120 # Energy for precharge background per rank (pJ)
303 system.physmem_0.actPowerDownEnergy 12457025670 # Energy for active power-down per rank (pJ)
304 system.physmem_0.prePowerDownEnergy 8414413920 # Energy for precharge power-down per rank (pJ)
305 system.physmem_0.selfRefreshEnergy 671932680540 # Energy for self refresh per rank (pJ)
306 system.physmem_0.totalEnergy 705069857835 # Total energy per rank (pJ)
307 system.physmem_0.averagePower 246.966071 # Core power per rank (mW)
308 system.physmem_0.totalIdleTime 2843548486750 # Total Idle time Per DRAM Rank
309 system.physmem_0.memoryStateTime::IDLE 708499000 # Time in different power states
310 system.physmem_0.memoryStateTime::REF 2558586000 # Time in different power states
311 system.physmem_0.memoryStateTime::SREF 2794649429000 # Time in different power states
312 system.physmem_0.memoryStateTime::PRE_PDN 21912527500 # Time in different power states
313 system.physmem_0.memoryStateTime::ACT 7778804250 # Time in different power states
314 system.physmem_0.memoryStateTime::ACT_PDN 27318150750 # Time in different power states
315 system.physmem_1.actEnergy 212957640 # Energy for activate commands per rank (pJ)
316 system.physmem_1.preEnergy 113185875 # Energy for precharge commands per rank (pJ)
317 system.physmem_1.readEnergy 593990880 # Energy for read commands per rank (pJ)
318 system.physmem_1.writeEnergy 326082960 # Energy for write commands per rank (pJ)
319 system.physmem_1.refreshEnergy 6113824080.000001 # Energy for refresh commands per rank (pJ)
320 system.physmem_1.actBackEnergy 4455367380 # Energy for active background per rank (pJ)
321 system.physmem_1.preBackEnergy 374460480 # Energy for precharge background per rank (pJ)
322 system.physmem_1.actPowerDownEnergy 12365716800 # Energy for active power-down per rank (pJ)
323 system.physmem_1.prePowerDownEnergy 8661645120 # Energy for precharge power-down per rank (pJ)
324 system.physmem_1.selfRefreshEnergy 671979444945 # Energy for self refresh per rank (pJ)
325 system.physmem_1.totalEnergy 705199696980 # Total energy per rank (pJ)
326 system.physmem_1.averagePower 247.011550 # Core power per rank (mW)
327 system.physmem_1.totalIdleTime 2844173514000 # Total Idle time Per DRAM Rank
328 system.physmem_1.memoryStateTime::IDLE 705782750 # Time in different power states
329 system.physmem_1.memoryStateTime::REF 2600572000 # Time in different power states
330 system.physmem_1.memoryStateTime::SREF 2794499397250 # Time in different power states
331 system.physmem_1.memoryStateTime::PRE_PDN 22556418250 # Time in different power states
332 system.physmem_1.memoryStateTime::ACT 7446062750 # Time in different power states
333 system.physmem_1.memoryStateTime::ACT_PDN 27117763500 # Time in different power states
334 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
335 system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
336 system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
337 system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
338 system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
339 system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
340 system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
341 system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s)
342 system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s)
343 system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s)
344 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
345 system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
346 system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
347 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
348 system.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
349 system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
350 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
351 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
352 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
353 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
354 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
355 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
356 system.cpu.branchPred.lookups 31074836 # Number of BP lookups
357 system.cpu.branchPred.condPredicted 16867509 # Number of conditional branches predicted
358 system.cpu.branchPred.condIncorrect 2481345 # Number of conditional branches incorrect
359 system.cpu.branchPred.BTBLookups 18655029 # Number of BTB lookups
360 system.cpu.branchPred.BTBHits 10408802 # Number of BTB hits
361 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
362 system.cpu.branchPred.BTBHitPct 55.796225 # BTB Hit Percentage
363 system.cpu.branchPred.usedRAS 7856601 # Number of times the RAS was used to get a target.
364 system.cpu.branchPred.RASInCorrect 1514233 # Number of incorrect RAS predictions.
365 system.cpu.branchPred.indirectLookups 3068747 # Number of indirect predictor lookups.
366 system.cpu.branchPred.indirectHits 2872226 # Number of indirect target hits.
367 system.cpu.branchPred.indirectMisses 196521 # Number of indirect misses.
368 system.cpu.branchPredindirectMispredicted 109392 # Number of mispredicted indirect branches.
369 system.cpu_clk_domain.clock 500 # Clock period in ticks
370 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
371 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
372 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
373 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
374 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
375 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
376 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
377 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
378 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
379 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
380 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
381 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
382 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
383 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
384 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
385 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
386 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
387 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
388 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
389 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
390 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
391 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
392 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
393 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
394 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
395 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
396 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
397 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
398 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
399 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
400 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
401 system.cpu.dtb.walker.walks 68070 # Table walker walks requested
402 system.cpu.dtb.walker.walksShort 68070 # Table walker walks initiated with short descriptors
403 system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44787 # Level at which table walker walks with short descriptors terminate
404 system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23283 # Level at which table walker walks with short descriptors terminate
405 system.cpu.dtb.walker.walkWaitTime::samples 68070 # Table walker wait (enqueue to first request) latency
406 system.cpu.dtb.walker.walkWaitTime::0 68070 100.00% 100.00% # Table walker wait (enqueue to first request) latency
407 system.cpu.dtb.walker.walkWaitTime::total 68070 # Table walker wait (enqueue to first request) latency
408 system.cpu.dtb.walker.walkCompletionTime::samples 7877 # Table walker service (enqueue to completion) latency
409 system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571 # Table walker service (enqueue to completion) latency
410 system.cpu.dtb.walker.walkCompletionTime::gmean 8445.879455 # Table walker service (enqueue to completion) latency
411 system.cpu.dtb.walker.walkCompletionTime::stdev 9567.630419 # Table walker service (enqueue to completion) latency
412 system.cpu.dtb.walker.walkCompletionTime::0-65535 7869 99.90% 99.90% # Table walker service (enqueue to completion) latency
413 system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.97% # Table walker service (enqueue to completion) latency
414 system.cpu.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
415 system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
416 system.cpu.dtb.walker.walkCompletionTime::total 7877 # Table walker service (enqueue to completion) latency
417 system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution
418 system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution
419 system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution
420 system.cpu.dtb.walker.walkPageSizes::4K 6513 82.68% 82.68% # Table walker page sizes translated
421 system.cpu.dtb.walker.walkPageSizes::1M 1364 17.32% 100.00% # Table walker page sizes translated
422 system.cpu.dtb.walker.walkPageSizes::total 7877 # Table walker page sizes translated
423 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68070 # Table walker requests started/completed, data/inst
424 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
425 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68070 # Table walker requests started/completed, data/inst
426 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7877 # Table walker requests started/completed, data/inst
427 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
428 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7877 # Table walker requests started/completed, data/inst
429 system.cpu.dtb.walker.walkRequestOrigin::total 75947 # Table walker requests started/completed, data/inst
430 system.cpu.dtb.inst_hits 0 # ITB inst hits
431 system.cpu.dtb.inst_misses 0 # ITB inst misses
432 system.cpu.dtb.read_hits 24743648 # DTB read hits
433 system.cpu.dtb.read_misses 61017 # DTB read misses
434 system.cpu.dtb.write_hits 19435570 # DTB write hits
435 system.cpu.dtb.write_misses 7053 # DTB write misses
436 system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
437 system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
438 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
439 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
440 system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB
441 system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions
442 system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch
443 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
444 system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions
445 system.cpu.dtb.read_accesses 24804665 # DTB read accesses
446 system.cpu.dtb.write_accesses 19442623 # DTB write accesses
447 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
448 system.cpu.dtb.hits 44179218 # DTB hits
449 system.cpu.dtb.misses 68070 # DTB misses
450 system.cpu.dtb.accesses 44247288 # DTB accesses
451 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
452 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
453 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
454 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
455 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
456 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
457 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
458 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
459 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
460 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
461 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
462 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
463 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
464 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
465 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
466 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
467 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
468 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
469 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
470 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
471 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
472 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
473 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
474 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
475 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
476 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
477 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
478 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
479 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
480 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
481 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
482 system.cpu.itb.walker.walks 5855 # Table walker walks requested
483 system.cpu.itb.walker.walksShort 5855 # Table walker walks initiated with short descriptors
484 system.cpu.itb.walker.walksShortTerminationLevel::Level1 322 # Level at which table walker walks with short descriptors terminate
485 system.cpu.itb.walker.walksShortTerminationLevel::Level2 5533 # Level at which table walker walks with short descriptors terminate
486 system.cpu.itb.walker.walkWaitTime::samples 5855 # Table walker wait (enqueue to first request) latency
487 system.cpu.itb.walker.walkWaitTime::0 5855 100.00% 100.00% # Table walker wait (enqueue to first request) latency
488 system.cpu.itb.walker.walkWaitTime::total 5855 # Table walker wait (enqueue to first request) latency
489 system.cpu.itb.walker.walkCompletionTime::samples 3194 # Table walker service (enqueue to completion) latency
490 system.cpu.itb.walker.walkCompletionTime::mean 10424.389480 # Table walker service (enqueue to completion) latency
491 system.cpu.itb.walker.walkCompletionTime::gmean 8603.860466 # Table walker service (enqueue to completion) latency
492 system.cpu.itb.walker.walkCompletionTime::stdev 6932.586443 # Table walker service (enqueue to completion) latency
493 system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.80% 57.80% # Table walker service (enqueue to completion) latency
494 system.cpu.itb.walker.walkCompletionTime::8192-16383 798 24.98% 82.78% # Table walker service (enqueue to completion) latency
495 system.cpu.itb.walker.walkCompletionTime::16384-24575 544 17.03% 99.81% # Table walker service (enqueue to completion) latency
496 system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency
497 system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
498 system.cpu.itb.walker.walkCompletionTime::total 3194 # Table walker service (enqueue to completion) latency
499 system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution
500 system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution
501 system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution
502 system.cpu.itb.walker.walkPageSizes::4K 2884 90.29% 90.29% # Table walker page sizes translated
503 system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated
504 system.cpu.itb.walker.walkPageSizes::total 3194 # Table walker page sizes translated
505 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
506 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5855 # Table walker requests started/completed, data/inst
507 system.cpu.itb.walker.walkRequestOrigin_Requested::total 5855 # Table walker requests started/completed, data/inst
508 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
509 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3194 # Table walker requests started/completed, data/inst
510 system.cpu.itb.walker.walkRequestOrigin_Completed::total 3194 # Table walker requests started/completed, data/inst
511 system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst
512 system.cpu.itb.inst_hits 57481594 # ITB inst hits
513 system.cpu.itb.inst_misses 5855 # ITB inst misses
514 system.cpu.itb.read_hits 0 # DTB read hits
515 system.cpu.itb.read_misses 0 # DTB read misses
516 system.cpu.itb.write_hits 0 # DTB write hits
517 system.cpu.itb.write_misses 0 # DTB write misses
518 system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
519 system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
520 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
521 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
522 system.cpu.itb.flush_entries 2915 # Number of entries that have been flushed from TLB
523 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
524 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
525 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
526 system.cpu.itb.perms_faults 8308 # Number of TLB faults due to permissions restrictions
527 system.cpu.itb.read_accesses 0 # DTB read accesses
528 system.cpu.itb.write_accesses 0 # DTB write accesses
529 system.cpu.itb.inst_accesses 57487449 # ITB inst accesses
530 system.cpu.itb.hits 57481594 # DTB hits
531 system.cpu.itb.misses 5855 # DTB misses
532 system.cpu.itb.accesses 57487449 # DTB accesses
533 system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
534 system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
535 system.cpu.pwrStateClkGateDist::mean 887934091.386746 # Distribution of time spent in the clock gated state
536 system.cpu.pwrStateClkGateDist::stdev 17437787888.707882 # Distribution of time spent in the clock gated state
537 system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state
538 system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state
539 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
540 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
541 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
542 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
543 system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
544 system.cpu.pwrStateClkGateDist::max_value 499966196768 # Distribution of time spent in the clock gated state
545 system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
546 system.cpu.pwrStateResidencyTicks::ON 161821897324 # Cumulative time (in ticks) in various power states
547 system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176 # Cumulative time (in ticks) in various power states
548 system.cpu.numCycles 323646748 # number of cpu cycles simulated
549 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
550 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
551 system.cpu.committedInsts 112020669 # Number of instructions committed
552 system.cpu.committedOps 135443008 # Number of ops (including micro ops) committed
553 system.cpu.discardedOps 7814596 # Number of ops (including micro ops) which were discarded before commit
554 system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
555 system.cpu.quiesceCycles 5386269471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
556 system.cpu.cpi 2.889170 # CPI: cycles per instruction
557 system.cpu.ipc 0.346120 # IPC: instructions per cycle
558 system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction
559 system.cpu.op_class_0::IntAlu 90804901 67.04% 67.04% # Class of committed instruction
560 system.cpu.op_class_0::IntMult 113201 0.08% 67.13% # Class of committed instruction
561 system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction
562 system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction
563 system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction
564 system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction
565 system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction
566 system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction
567 system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction
568 system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction
569 system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction
570 system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction
571 system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction
572 system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction
573 system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction
574 system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction
575 system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction
576 system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction
577 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction
578 system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction
579 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction
580 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction
581 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction
582 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction
583 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction
584 system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Class of committed instruction
585 system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction
586 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction
587 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction
588 system.cpu.op_class_0::MemRead 24250620 17.90% 85.04% # Class of committed instruction
589 system.cpu.op_class_0::MemWrite 20263468 14.96% 100.00% # Class of committed instruction
590 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
591 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
592 system.cpu.op_class_0::total 135443008 # Class of committed instruction
593 system.cpu.kern.inst.arm 0 # number of arm instructions executed
594 system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
595 system.cpu.tickCycles 217947056 # Number of cycles that the object actually ticked
596 system.cpu.idleCycles 105699692 # Total number of cycles that the object has spent stopped
597 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
598 system.cpu.dcache.tags.replacements 844723 # number of replacements
599 system.cpu.dcache.tags.tagsinuse 511.945160 # Cycle average of tags in use
600 system.cpu.dcache.tags.total_refs 42637807 # Total number of references to valid blocks.
601 system.cpu.dcache.tags.sampled_refs 845235 # Sample count of references to valid blocks.
602 system.cpu.dcache.tags.avg_refs 50.444914 # Average number of references to valid blocks.
603 system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit.
604 system.cpu.dcache.tags.occ_blocks::cpu.data 511.945160 # Average occupied blocks per requestor
605 system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy
606 system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy
607 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
608 system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
609 system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
610 system.cpu.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
611 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
612 system.cpu.dcache.tags.tag_accesses 176206878 # Number of tag accesses
613 system.cpu.dcache.tags.data_accesses 176206878 # Number of data accesses
614 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
615 system.cpu.dcache.ReadReq_hits::cpu.data 23101260 # number of ReadReq hits
616 system.cpu.dcache.ReadReq_hits::total 23101260 # number of ReadReq hits
617 system.cpu.dcache.WriteReq_hits::cpu.data 18273431 # number of WriteReq hits
618 system.cpu.dcache.WriteReq_hits::total 18273431 # number of WriteReq hits
619 system.cpu.dcache.SoftPFReq_hits::cpu.data 356861 # number of SoftPFReq hits
620 system.cpu.dcache.SoftPFReq_hits::total 356861 # number of SoftPFReq hits
621 system.cpu.dcache.LoadLockedReq_hits::cpu.data 443340 # number of LoadLockedReq hits
622 system.cpu.dcache.LoadLockedReq_hits::total 443340 # number of LoadLockedReq hits
623 system.cpu.dcache.StoreCondReq_hits::cpu.data 460050 # number of StoreCondReq hits
624 system.cpu.dcache.StoreCondReq_hits::total 460050 # number of StoreCondReq hits
625 system.cpu.dcache.demand_hits::cpu.data 41374691 # number of demand (read+write) hits
626 system.cpu.dcache.demand_hits::total 41374691 # number of demand (read+write) hits
627 system.cpu.dcache.overall_hits::cpu.data 41731552 # number of overall hits
628 system.cpu.dcache.overall_hits::total 41731552 # number of overall hits
629 system.cpu.dcache.ReadReq_misses::cpu.data 465078 # number of ReadReq misses
630 system.cpu.dcache.ReadReq_misses::total 465078 # number of ReadReq misses
631 system.cpu.dcache.WriteReq_misses::cpu.data 548776 # number of WriteReq misses
632 system.cpu.dcache.WriteReq_misses::total 548776 # number of WriteReq misses
633 system.cpu.dcache.SoftPFReq_misses::cpu.data 169103 # number of SoftPFReq misses
634 system.cpu.dcache.SoftPFReq_misses::total 169103 # number of SoftPFReq misses
635 system.cpu.dcache.LoadLockedReq_misses::cpu.data 22503 # number of LoadLockedReq misses
636 system.cpu.dcache.LoadLockedReq_misses::total 22503 # number of LoadLockedReq misses
637 system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
638 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
639 system.cpu.dcache.demand_misses::cpu.data 1013854 # number of demand (read+write) misses
640 system.cpu.dcache.demand_misses::total 1013854 # number of demand (read+write) misses
641 system.cpu.dcache.overall_misses::cpu.data 1182957 # number of overall misses
642 system.cpu.dcache.overall_misses::total 1182957 # number of overall misses
643 system.cpu.dcache.ReadReq_miss_latency::cpu.data 7334484000 # number of ReadReq miss cycles
644 system.cpu.dcache.ReadReq_miss_latency::total 7334484000 # number of ReadReq miss cycles
645 system.cpu.dcache.WriteReq_miss_latency::cpu.data 26875060480 # number of WriteReq miss cycles
646 system.cpu.dcache.WriteReq_miss_latency::total 26875060480 # number of WriteReq miss cycles
647 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306737000 # number of LoadLockedReq miss cycles
648 system.cpu.dcache.LoadLockedReq_miss_latency::total 306737000 # number of LoadLockedReq miss cycles
649 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles
650 system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles
651 system.cpu.dcache.demand_miss_latency::cpu.data 34209544480 # number of demand (read+write) miss cycles
652 system.cpu.dcache.demand_miss_latency::total 34209544480 # number of demand (read+write) miss cycles
653 system.cpu.dcache.overall_miss_latency::cpu.data 34209544480 # number of overall miss cycles
654 system.cpu.dcache.overall_miss_latency::total 34209544480 # number of overall miss cycles
655 system.cpu.dcache.ReadReq_accesses::cpu.data 23566338 # number of ReadReq accesses(hits+misses)
656 system.cpu.dcache.ReadReq_accesses::total 23566338 # number of ReadReq accesses(hits+misses)
657 system.cpu.dcache.WriteReq_accesses::cpu.data 18822207 # number of WriteReq accesses(hits+misses)
658 system.cpu.dcache.WriteReq_accesses::total 18822207 # number of WriteReq accesses(hits+misses)
659 system.cpu.dcache.SoftPFReq_accesses::cpu.data 525964 # number of SoftPFReq accesses(hits+misses)
660 system.cpu.dcache.SoftPFReq_accesses::total 525964 # number of SoftPFReq accesses(hits+misses)
661 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465843 # number of LoadLockedReq accesses(hits+misses)
662 system.cpu.dcache.LoadLockedReq_accesses::total 465843 # number of LoadLockedReq accesses(hits+misses)
663 system.cpu.dcache.StoreCondReq_accesses::cpu.data 460052 # number of StoreCondReq accesses(hits+misses)
664 system.cpu.dcache.StoreCondReq_accesses::total 460052 # number of StoreCondReq accesses(hits+misses)
665 system.cpu.dcache.demand_accesses::cpu.data 42388545 # number of demand (read+write) accesses
666 system.cpu.dcache.demand_accesses::total 42388545 # number of demand (read+write) accesses
667 system.cpu.dcache.overall_accesses::cpu.data 42914509 # number of overall (read+write) accesses
668 system.cpu.dcache.overall_accesses::total 42914509 # number of overall (read+write) accesses
669 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019735 # miss rate for ReadReq accesses
670 system.cpu.dcache.ReadReq_miss_rate::total 0.019735 # miss rate for ReadReq accesses
671 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029156 # miss rate for WriteReq accesses
672 system.cpu.dcache.WriteReq_miss_rate::total 0.029156 # miss rate for WriteReq accesses
673 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321511 # miss rate for SoftPFReq accesses
674 system.cpu.dcache.SoftPFReq_miss_rate::total 0.321511 # miss rate for SoftPFReq accesses
675 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048306 # miss rate for LoadLockedReq accesses
676 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048306 # miss rate for LoadLockedReq accesses
677 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
678 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
679 system.cpu.dcache.demand_miss_rate::cpu.data 0.023918 # miss rate for demand accesses
680 system.cpu.dcache.demand_miss_rate::total 0.023918 # miss rate for demand accesses
681 system.cpu.dcache.overall_miss_rate::cpu.data 0.027565 # miss rate for overall accesses
682 system.cpu.dcache.overall_miss_rate::total 0.027565 # miss rate for overall accesses
683 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507 # average ReadReq miss latency
684 system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507 # average ReadReq miss latency
685 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918 # average WriteReq miss latency
686 system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918 # average WriteReq miss latency
687 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097 # average LoadLockedReq miss latency
688 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097 # average LoadLockedReq miss latency
689 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency
690 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency
691 system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680 # average overall miss latency
692 system.cpu.dcache.demand_avg_miss_latency::total 33742.081680 # average overall miss latency
693 system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160 # average overall miss latency
694 system.cpu.dcache.overall_avg_miss_latency::total 28918.671160 # average overall miss latency
695 system.cpu.dcache.blocked_cycles::no_mshrs 224 # number of cycles access was blocked
696 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
697 system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
698 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
699 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked
700 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
701 system.cpu.dcache.writebacks::writebacks 702249 # number of writebacks
702 system.cpu.dcache.writebacks::total 702249 # number of writebacks
703 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45641 # number of ReadReq MSHR hits
704 system.cpu.dcache.ReadReq_mshr_hits::total 45641 # number of ReadReq MSHR hits
705 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249535 # number of WriteReq MSHR hits
706 system.cpu.dcache.WriteReq_mshr_hits::total 249535 # number of WriteReq MSHR hits
707 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits
708 system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits
709 system.cpu.dcache.demand_mshr_hits::cpu.data 295176 # number of demand (read+write) MSHR hits
710 system.cpu.dcache.demand_mshr_hits::total 295176 # number of demand (read+write) MSHR hits
711 system.cpu.dcache.overall_mshr_hits::cpu.data 295176 # number of overall MSHR hits
712 system.cpu.dcache.overall_mshr_hits::total 295176 # number of overall MSHR hits
713 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419437 # number of ReadReq MSHR misses
714 system.cpu.dcache.ReadReq_mshr_misses::total 419437 # number of ReadReq MSHR misses
715 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299241 # number of WriteReq MSHR misses
716 system.cpu.dcache.WriteReq_mshr_misses::total 299241 # number of WriteReq MSHR misses
717 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121149 # number of SoftPFReq MSHR misses
718 system.cpu.dcache.SoftPFReq_mshr_misses::total 121149 # number of SoftPFReq MSHR misses
719 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8225 # number of LoadLockedReq MSHR misses
720 system.cpu.dcache.LoadLockedReq_mshr_misses::total 8225 # number of LoadLockedReq MSHR misses
721 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
722 system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
723 system.cpu.dcache.demand_mshr_misses::cpu.data 718678 # number of demand (read+write) MSHR misses
724 system.cpu.dcache.demand_mshr_misses::total 718678 # number of demand (read+write) MSHR misses
725 system.cpu.dcache.overall_mshr_misses::cpu.data 839827 # number of overall MSHR misses
726 system.cpu.dcache.overall_mshr_misses::total 839827 # number of overall MSHR misses
727 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
728 system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable
729 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
730 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
731 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
732 system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
733 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447841000 # number of ReadReq MSHR miss cycles
734 system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447841000 # number of ReadReq MSHR miss cycles
735 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14303453000 # number of WriteReq MSHR miss cycles
736 system.cpu.dcache.WriteReq_mshr_miss_latency::total 14303453000 # number of WriteReq MSHR miss cycles
737 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1653166500 # number of SoftPFReq MSHR miss cycles
738 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1653166500 # number of SoftPFReq MSHR miss cycles
739 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 121747500 # number of LoadLockedReq MSHR miss cycles
740 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121747500 # number of LoadLockedReq MSHR miss cycles
741 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles
742 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles
743 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20751294000 # number of demand (read+write) MSHR miss cycles
744 system.cpu.dcache.demand_mshr_miss_latency::total 20751294000 # number of demand (read+write) MSHR miss cycles
745 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22404460500 # number of overall MSHR miss cycles
746 system.cpu.dcache.overall_mshr_miss_latency::total 22404460500 # number of overall MSHR miss cycles
747 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305636000 # number of ReadReq MSHR uncacheable cycles
748 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305636000 # number of ReadReq MSHR uncacheable cycles
749 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305636000 # number of overall MSHR uncacheable cycles
750 system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305636000 # number of overall MSHR uncacheable cycles
751 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017798 # mshr miss rate for ReadReq accesses
752 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017798 # mshr miss rate for ReadReq accesses
753 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses
754 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses
755 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230337 # mshr miss rate for SoftPFReq accesses
756 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230337 # mshr miss rate for SoftPFReq accesses
757 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses
758 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses
759 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
760 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
761 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016955 # mshr miss rate for demand accesses
762 system.cpu.dcache.demand_mshr_miss_rate::total 0.016955 # mshr miss rate for demand accesses
763 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019570 # mshr miss rate for overall accesses
764 system.cpu.dcache.overall_mshr_miss_rate::total 0.019570 # mshr miss rate for overall accesses
765 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997 # average ReadReq mshr miss latency
766 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997 # average ReadReq mshr miss latency
767 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411 # average WriteReq mshr miss latency
768 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411 # average WriteReq mshr miss latency
769 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639 # average SoftPFReq mshr miss latency
770 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639 # average SoftPFReq mshr miss latency
771 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660 # average LoadLockedReq mshr miss latency
772 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660 # average LoadLockedReq mshr miss latency
773 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency
774 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency
775 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013 # average overall mshr miss latency
776 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013 # average overall mshr miss latency
777 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074 # average overall mshr miss latency
778 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074 # average overall mshr miss latency
779 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394 # average ReadReq mshr uncacheable latency
780 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394 # average ReadReq mshr uncacheable latency
781 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948 # average overall mshr uncacheable latency
782 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948 # average overall mshr uncacheable latency
783 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
784 system.cpu.icache.tags.replacements 2891615 # number of replacements
785 system.cpu.icache.tags.tagsinuse 511.370867 # Cycle average of tags in use
786 system.cpu.icache.tags.total_refs 54580851 # Total number of references to valid blocks.
787 system.cpu.icache.tags.sampled_refs 2892127 # Sample count of references to valid blocks.
788 system.cpu.icache.tags.avg_refs 18.872218 # Average number of references to valid blocks.
789 system.cpu.icache.tags.warmup_cycle 16116545500 # Cycle when the warmup percentage was hit.
790 system.cpu.icache.tags.occ_blocks::cpu.inst 511.370867 # Average occupied blocks per requestor
791 system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy
792 system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy
793 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
794 system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
795 system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
796 system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
797 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
798 system.cpu.icache.tags.tag_accesses 60365128 # Number of tag accesses
799 system.cpu.icache.tags.data_accesses 60365128 # Number of data accesses
800 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
801 system.cpu.icache.ReadReq_hits::cpu.inst 54580851 # number of ReadReq hits
802 system.cpu.icache.ReadReq_hits::total 54580851 # number of ReadReq hits
803 system.cpu.icache.demand_hits::cpu.inst 54580851 # number of demand (read+write) hits
804 system.cpu.icache.demand_hits::total 54580851 # number of demand (read+write) hits
805 system.cpu.icache.overall_hits::cpu.inst 54580851 # number of overall hits
806 system.cpu.icache.overall_hits::total 54580851 # number of overall hits
807 system.cpu.icache.ReadReq_misses::cpu.inst 2892139 # number of ReadReq misses
808 system.cpu.icache.ReadReq_misses::total 2892139 # number of ReadReq misses
809 system.cpu.icache.demand_misses::cpu.inst 2892139 # number of demand (read+write) misses
810 system.cpu.icache.demand_misses::total 2892139 # number of demand (read+write) misses
811 system.cpu.icache.overall_misses::cpu.inst 2892139 # number of overall misses
812 system.cpu.icache.overall_misses::total 2892139 # number of overall misses
813 system.cpu.icache.ReadReq_miss_latency::cpu.inst 39804335500 # number of ReadReq miss cycles
814 system.cpu.icache.ReadReq_miss_latency::total 39804335500 # number of ReadReq miss cycles
815 system.cpu.icache.demand_miss_latency::cpu.inst 39804335500 # number of demand (read+write) miss cycles
816 system.cpu.icache.demand_miss_latency::total 39804335500 # number of demand (read+write) miss cycles
817 system.cpu.icache.overall_miss_latency::cpu.inst 39804335500 # number of overall miss cycles
818 system.cpu.icache.overall_miss_latency::total 39804335500 # number of overall miss cycles
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820 system.cpu.icache.ReadReq_accesses::total 57472990 # number of ReadReq accesses(hits+misses)
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822 system.cpu.icache.demand_accesses::total 57472990 # number of demand (read+write) accesses
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824 system.cpu.icache.overall_accesses::total 57472990 # number of overall (read+write) accesses
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826 system.cpu.icache.ReadReq_miss_rate::total 0.050322 # miss rate for ReadReq accesses
827 system.cpu.icache.demand_miss_rate::cpu.inst 0.050322 # miss rate for demand accesses
828 system.cpu.icache.demand_miss_rate::total 0.050322 # miss rate for demand accesses
829 system.cpu.icache.overall_miss_rate::cpu.inst 0.050322 # miss rate for overall accesses
830 system.cpu.icache.overall_miss_rate::total 0.050322 # miss rate for overall accesses
831 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990 # average ReadReq miss latency
832 system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990 # average ReadReq miss latency
833 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency
834 system.cpu.icache.demand_avg_miss_latency::total 13762.939990 # average overall miss latency
835 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency
836 system.cpu.icache.overall_avg_miss_latency::total 13762.939990 # average overall miss latency
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838 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
840 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
841 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
842 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843 system.cpu.icache.writebacks::writebacks 2891615 # number of writebacks
844 system.cpu.icache.writebacks::total 2891615 # number of writebacks
845 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2892139 # number of ReadReq MSHR misses
846 system.cpu.icache.ReadReq_mshr_misses::total 2892139 # number of ReadReq MSHR misses
847 system.cpu.icache.demand_mshr_misses::cpu.inst 2892139 # number of demand (read+write) MSHR misses
848 system.cpu.icache.demand_mshr_misses::total 2892139 # number of demand (read+write) MSHR misses
849 system.cpu.icache.overall_mshr_misses::cpu.inst 2892139 # number of overall MSHR misses
850 system.cpu.icache.overall_mshr_misses::total 2892139 # number of overall MSHR misses
851 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
852 system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable
853 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
854 system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses
855 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36912197500 # number of ReadReq MSHR miss cycles
856 system.cpu.icache.ReadReq_mshr_miss_latency::total 36912197500 # number of ReadReq MSHR miss cycles
857 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36912197500 # number of demand (read+write) MSHR miss cycles
858 system.cpu.icache.demand_mshr_miss_latency::total 36912197500 # number of demand (read+write) MSHR miss cycles
859 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36912197500 # number of overall MSHR miss cycles
860 system.cpu.icache.overall_mshr_miss_latency::total 36912197500 # number of overall MSHR miss cycles
861 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles
862 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles
863 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles
864 system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles
865 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for ReadReq accesses
866 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050322 # mshr miss rate for ReadReq accesses
867 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for demand accesses
868 system.cpu.icache.demand_mshr_miss_rate::total 0.050322 # mshr miss rate for demand accesses
869 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for overall accesses
870 system.cpu.icache.overall_mshr_miss_rate::total 0.050322 # mshr miss rate for overall accesses
871 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336 # average ReadReq mshr miss latency
872 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336 # average ReadReq mshr miss latency
873 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency
874 system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency
875 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency
876 system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency
877 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency
878 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency
879 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency
880 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency
881 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
882 system.cpu.l2cache.tags.replacements 97098 # number of replacements
883 system.cpu.l2cache.tags.tagsinuse 65145.315179 # Cycle average of tags in use
884 system.cpu.l2cache.tags.total_refs 7321379 # Total number of references to valid blocks.
885 system.cpu.l2cache.tags.sampled_refs 162490 # Sample count of references to valid blocks.
886 system.cpu.l2cache.tags.avg_refs 45.057413 # Average number of references to valid blocks.
887 system.cpu.l2cache.tags.warmup_cycle 271905816000 # Cycle when the warmup percentage was hit.
888 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 69.248317 # Average occupied blocks per requestor
889 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032949 # Average occupied blocks per requestor
890 system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979 # Average occupied blocks per requestor
891 system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933 # Average occupied blocks per requestor
892 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001057 # Average percentage of cache occupancy
893 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
894 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184912 # Average percentage of cache occupancy
895 system.cpu.l2cache.tags.occ_percent::cpu.data 0.808069 # Average percentage of cache occupancy
896 system.cpu.l2cache.tags.occ_percent::total 0.994039 # Average percentage of cache occupancy
897 system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
898 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65342 # Occupied blocks per task id
899 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id
900 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
901 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
902 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4586 # Occupied blocks per task id
903 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60692 # Occupied blocks per task id
904 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id
905 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997040 # Percentage of cache occupancy per task id
906 system.cpu.l2cache.tags.tag_accesses 60089878 # Number of tag accesses
907 system.cpu.l2cache.tags.data_accesses 60089878 # Number of data accesses
908 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
909 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68391 # number of ReadReq hits
910 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3372 # number of ReadReq hits
911 system.cpu.l2cache.ReadReq_hits::total 71763 # number of ReadReq hits
912 system.cpu.l2cache.WritebackDirty_hits::writebacks 702249 # number of WritebackDirty hits
913 system.cpu.l2cache.WritebackDirty_hits::total 702249 # number of WritebackDirty hits
914 system.cpu.l2cache.WritebackClean_hits::writebacks 2840964 # number of WritebackClean hits
915 system.cpu.l2cache.WritebackClean_hits::total 2840964 # number of WritebackClean hits
916 system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784 # number of UpgradeReq hits
917 system.cpu.l2cache.UpgradeReq_hits::total 2784 # number of UpgradeReq hits
918 system.cpu.l2cache.ReadExReq_hits::cpu.data 166689 # number of ReadExReq hits
919 system.cpu.l2cache.ReadExReq_hits::total 166689 # number of ReadExReq hits
920 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2869145 # number of ReadCleanReq hits
921 system.cpu.l2cache.ReadCleanReq_hits::total 2869145 # number of ReadCleanReq hits
922 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534458 # number of ReadSharedReq hits
923 system.cpu.l2cache.ReadSharedReq_hits::total 534458 # number of ReadSharedReq hits
924 system.cpu.l2cache.demand_hits::cpu.dtb.walker 68391 # number of demand (read+write) hits
925 system.cpu.l2cache.demand_hits::cpu.itb.walker 3372 # number of demand (read+write) hits
926 system.cpu.l2cache.demand_hits::cpu.inst 2869145 # number of demand (read+write) hits
927 system.cpu.l2cache.demand_hits::cpu.data 701147 # number of demand (read+write) hits
928 system.cpu.l2cache.demand_hits::total 3642055 # number of demand (read+write) hits
929 system.cpu.l2cache.overall_hits::cpu.dtb.walker 68391 # number of overall hits
930 system.cpu.l2cache.overall_hits::cpu.itb.walker 3372 # number of overall hits
931 system.cpu.l2cache.overall_hits::cpu.inst 2869145 # number of overall hits
932 system.cpu.l2cache.overall_hits::cpu.data 701147 # number of overall hits
933 system.cpu.l2cache.overall_hits::total 3642055 # number of overall hits
934 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 110 # number of ReadReq misses
935 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
936 system.cpu.l2cache.ReadReq_misses::total 112 # number of ReadReq misses
937 system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
938 system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
939 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
940 system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
941 system.cpu.l2cache.ReadExReq_misses::cpu.data 129768 # number of ReadExReq misses
942 system.cpu.l2cache.ReadExReq_misses::total 129768 # number of ReadExReq misses
943 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22956 # number of ReadCleanReq misses
944 system.cpu.l2cache.ReadCleanReq_misses::total 22956 # number of ReadCleanReq misses
945 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14347 # number of ReadSharedReq misses
946 system.cpu.l2cache.ReadSharedReq_misses::total 14347 # number of ReadSharedReq misses
947 system.cpu.l2cache.demand_misses::cpu.dtb.walker 110 # number of demand (read+write) misses
948 system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
949 system.cpu.l2cache.demand_misses::cpu.inst 22956 # number of demand (read+write) misses
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952 system.cpu.l2cache.overall_misses::cpu.dtb.walker 110 # number of overall misses
953 system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
954 system.cpu.l2cache.overall_misses::cpu.inst 22956 # number of overall misses
955 system.cpu.l2cache.overall_misses::cpu.data 144115 # number of overall misses
956 system.cpu.l2cache.overall_misses::total 167183 # number of overall misses
957 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35753500 # number of ReadReq miss cycles
958 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000 # number of ReadReq miss cycles
959 system.cpu.l2cache.ReadReq_miss_latency::total 35946500 # number of ReadReq miss cycles
960 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000 # number of UpgradeReq miss cycles
961 system.cpu.l2cache.UpgradeReq_miss_latency::total 174000 # number of UpgradeReq miss cycles
962 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000 # number of SCUpgradeReq miss cycles
963 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000 # number of SCUpgradeReq miss cycles
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965 system.cpu.l2cache.ReadExReq_miss_latency::total 12066822500 # number of ReadExReq miss cycles
966 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2380927500 # number of ReadCleanReq miss cycles
967 system.cpu.l2cache.ReadCleanReq_miss_latency::total 2380927500 # number of ReadCleanReq miss cycles
968 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1746972000 # number of ReadSharedReq miss cycles
969 system.cpu.l2cache.ReadSharedReq_miss_latency::total 1746972000 # number of ReadSharedReq miss cycles
970 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35753500 # number of demand (read+write) miss cycles
971 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000 # number of demand (read+write) miss cycles
972 system.cpu.l2cache.demand_miss_latency::cpu.inst 2380927500 # number of demand (read+write) miss cycles
973 system.cpu.l2cache.demand_miss_latency::cpu.data 13813794500 # number of demand (read+write) miss cycles
974 system.cpu.l2cache.demand_miss_latency::total 16230668500 # number of demand (read+write) miss cycles
975 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35753500 # number of overall miss cycles
976 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000 # number of overall miss cycles
977 system.cpu.l2cache.overall_miss_latency::cpu.inst 2380927500 # number of overall miss cycles
978 system.cpu.l2cache.overall_miss_latency::cpu.data 13813794500 # number of overall miss cycles
979 system.cpu.l2cache.overall_miss_latency::total 16230668500 # number of overall miss cycles
980 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68501 # number of ReadReq accesses(hits+misses)
981 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3374 # number of ReadReq accesses(hits+misses)
982 system.cpu.l2cache.ReadReq_accesses::total 71875 # number of ReadReq accesses(hits+misses)
983 system.cpu.l2cache.WritebackDirty_accesses::writebacks 702249 # number of WritebackDirty accesses(hits+misses)
984 system.cpu.l2cache.WritebackDirty_accesses::total 702249 # number of WritebackDirty accesses(hits+misses)
985 system.cpu.l2cache.WritebackClean_accesses::writebacks 2840964 # number of WritebackClean accesses(hits+misses)
986 system.cpu.l2cache.WritebackClean_accesses::total 2840964 # number of WritebackClean accesses(hits+misses)
987 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790 # number of UpgradeReq accesses(hits+misses)
988 system.cpu.l2cache.UpgradeReq_accesses::total 2790 # number of UpgradeReq accesses(hits+misses)
989 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
990 system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
991 system.cpu.l2cache.ReadExReq_accesses::cpu.data 296457 # number of ReadExReq accesses(hits+misses)
992 system.cpu.l2cache.ReadExReq_accesses::total 296457 # number of ReadExReq accesses(hits+misses)
993 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2892101 # number of ReadCleanReq accesses(hits+misses)
994 system.cpu.l2cache.ReadCleanReq_accesses::total 2892101 # number of ReadCleanReq accesses(hits+misses)
995 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses)
996 system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses)
997 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68501 # number of demand (read+write) accesses
998 system.cpu.l2cache.demand_accesses::cpu.itb.walker 3374 # number of demand (read+write) accesses
999 system.cpu.l2cache.demand_accesses::cpu.inst 2892101 # number of demand (read+write) accesses
1000 system.cpu.l2cache.demand_accesses::cpu.data 845262 # number of demand (read+write) accesses
1001 system.cpu.l2cache.demand_accesses::total 3809238 # number of demand (read+write) accesses
1002 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68501 # number of overall (read+write) accesses
1003 system.cpu.l2cache.overall_accesses::cpu.itb.walker 3374 # number of overall (read+write) accesses
1004 system.cpu.l2cache.overall_accesses::cpu.inst 2892101 # number of overall (read+write) accesses
1005 system.cpu.l2cache.overall_accesses::cpu.data 845262 # number of overall (read+write) accesses
1006 system.cpu.l2cache.overall_accesses::total 3809238 # number of overall (read+write) accesses
1007 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001606 # miss rate for ReadReq accesses
1008 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000593 # miss rate for ReadReq accesses
1009 system.cpu.l2cache.ReadReq_miss_rate::total 0.001558 # miss rate for ReadReq accesses
1010 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151 # miss rate for UpgradeReq accesses
1011 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151 # miss rate for UpgradeReq accesses
1012 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1013 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1014 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437730 # miss rate for ReadExReq accesses
1015 system.cpu.l2cache.ReadExReq_miss_rate::total 0.437730 # miss rate for ReadExReq accesses
1016 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937 # miss rate for ReadCleanReq accesses
1017 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937 # miss rate for ReadCleanReq accesses
1018 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026142 # miss rate for ReadSharedReq accesses
1019 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026142 # miss rate for ReadSharedReq accesses
1020 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001606 # miss rate for demand accesses
1021 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000593 # miss rate for demand accesses
1022 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937 # miss rate for demand accesses
1023 system.cpu.l2cache.demand_miss_rate::cpu.data 0.170497 # miss rate for demand accesses
1024 system.cpu.l2cache.demand_miss_rate::total 0.043889 # miss rate for demand accesses
1025 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001606 # miss rate for overall accesses
1026 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000593 # miss rate for overall accesses
1027 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937 # miss rate for overall accesses
1028 system.cpu.l2cache.overall_miss_rate::cpu.data 0.170497 # miss rate for overall accesses
1029 system.cpu.l2cache.overall_miss_rate::total 0.043889 # miss rate for overall accesses
1030 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182 # average ReadReq miss latency
1031 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500 # average ReadReq miss latency
1032 system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857 # average ReadReq miss latency
1033 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000 # average UpgradeReq miss latency
1034 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000 # average UpgradeReq miss latency
1035 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000 # average SCUpgradeReq miss latency
1036 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000 # average SCUpgradeReq miss latency
1037 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745 # average ReadExReq miss latency
1038 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745 # average ReadExReq miss latency
1039 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091 # average ReadCleanReq miss latency
1040 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091 # average ReadCleanReq miss latency
1041 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296 # average ReadSharedReq miss latency
1042 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296 # average ReadSharedReq miss latency
1043 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency
1044 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency
1045 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency
1046 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency
1047 system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100 # average overall miss latency
1048 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency
1049 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency
1050 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency
1051 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency
1052 system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100 # average overall miss latency
1053 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1054 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1055 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1056 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1057 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1058 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1059 system.cpu.l2cache.writebacks::writebacks 88493 # number of writebacks
1060 system.cpu.l2cache.writebacks::total 88493 # number of writebacks
1061 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 14 # number of ReadCleanReq MSHR hits
1062 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits
1063 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 145 # number of ReadSharedReq MSHR hits
1064 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 145 # number of ReadSharedReq MSHR hits
1065 system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
1066 system.cpu.l2cache.demand_mshr_hits::cpu.data 145 # number of demand (read+write) MSHR hits
1067 system.cpu.l2cache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits
1068 system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
1069 system.cpu.l2cache.overall_mshr_hits::cpu.data 145 # number of overall MSHR hits
1070 system.cpu.l2cache.overall_mshr_hits::total 159 # number of overall MSHR hits
1071 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 110 # number of ReadReq MSHR misses
1072 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1073 system.cpu.l2cache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses
1074 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
1075 system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
1076 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1077 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1078 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129768 # number of ReadExReq MSHR misses
1079 system.cpu.l2cache.ReadExReq_mshr_misses::total 129768 # number of ReadExReq MSHR misses
1080 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22942 # number of ReadCleanReq MSHR misses
1081 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22942 # number of ReadCleanReq MSHR misses
1082 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14202 # number of ReadSharedReq MSHR misses
1083 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14202 # number of ReadSharedReq MSHR misses
1084 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 110 # number of demand (read+write) MSHR misses
1085 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1086 system.cpu.l2cache.demand_mshr_misses::cpu.inst 22942 # number of demand (read+write) MSHR misses
1087 system.cpu.l2cache.demand_mshr_misses::cpu.data 143970 # number of demand (read+write) MSHR misses
1088 system.cpu.l2cache.demand_mshr_misses::total 167024 # number of demand (read+write) MSHR misses
1089 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 110 # number of overall MSHR misses
1090 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1091 system.cpu.l2cache.overall_mshr_misses::cpu.inst 22942 # number of overall MSHR misses
1092 system.cpu.l2cache.overall_mshr_misses::cpu.data 143970 # number of overall MSHR misses
1093 system.cpu.l2cache.overall_mshr_misses::total 167024 # number of overall MSHR misses
1094 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
1095 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
1096 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable
1097 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
1098 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
1099 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
1100 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
1101 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses
1102 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34653500 # number of ReadReq MSHR miss cycles
1103 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000 # number of ReadReq MSHR miss cycles
1104 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34826500 # number of ReadReq MSHR miss cycles
1105 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000 # number of UpgradeReq MSHR miss cycles
1106 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000 # number of UpgradeReq MSHR miss cycles
1107 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000 # number of SCUpgradeReq MSHR miss cycles
1108 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles
1109 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10769142500 # number of ReadExReq MSHR miss cycles
1110 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10769142500 # number of ReadExReq MSHR miss cycles
1111 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2149471500 # number of ReadCleanReq MSHR miss cycles
1112 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2149471500 # number of ReadCleanReq MSHR miss cycles
1113 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1592398000 # number of ReadSharedReq MSHR miss cycles
1114 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1592398000 # number of ReadSharedReq MSHR miss cycles
1115 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34653500 # number of demand (read+write) MSHR miss cycles
1116 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000 # number of demand (read+write) MSHR miss cycles
1117 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2149471500 # number of demand (read+write) MSHR miss cycles
1118 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12361540500 # number of demand (read+write) MSHR miss cycles
1119 system.cpu.l2cache.demand_mshr_miss_latency::total 14545838500 # number of demand (read+write) MSHR miss cycles
1120 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34653500 # number of overall MSHR miss cycles
1121 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000 # number of overall MSHR miss cycles
1122 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2149471500 # number of overall MSHR miss cycles
1123 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12361540500 # number of overall MSHR miss cycles
1124 system.cpu.l2cache.overall_mshr_miss_latency::total 14545838500 # number of overall MSHR miss cycles
1125 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles
1126 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916431500 # number of ReadReq MSHR uncacheable cycles
1127 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133251000 # number of ReadReq MSHR uncacheable cycles
1128 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles
1129 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916431500 # number of overall MSHR uncacheable cycles
1130 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133251000 # number of overall MSHR uncacheable cycles
1131 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for ReadReq accesses
1132 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for ReadReq accesses
1133 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001558 # mshr miss rate for ReadReq accesses
1134 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for UpgradeReq accesses
1135 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151 # mshr miss rate for UpgradeReq accesses
1136 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1137 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1138 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437730 # mshr miss rate for ReadExReq accesses
1139 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437730 # mshr miss rate for ReadExReq accesses
1140 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for ReadCleanReq accesses
1141 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007933 # mshr miss rate for ReadCleanReq accesses
1142 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025878 # mshr miss rate for ReadSharedReq accesses
1143 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025878 # mshr miss rate for ReadSharedReq accesses
1144 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for demand accesses
1145 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for demand accesses
1146 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for demand accesses
1147 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for demand accesses
1148 system.cpu.l2cache.demand_mshr_miss_rate::total 0.043847 # mshr miss rate for demand accesses
1149 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for overall accesses
1150 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for overall accesses
1151 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for overall accesses
1152 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for overall accesses
1153 system.cpu.l2cache.overall_mshr_miss_rate::total 0.043847 # mshr miss rate for overall accesses
1154 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average ReadReq mshr miss latency
1155 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500 # average ReadReq mshr miss latency
1156 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857 # average ReadReq mshr miss latency
1157 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency
1158 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency
1159 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency
1160 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency
1161 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745 # average ReadExReq mshr miss latency
1162 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745 # average ReadExReq mshr miss latency
1163 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252 # average ReadCleanReq mshr miss latency
1164 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252 # average ReadCleanReq mshr miss latency
1165 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984 # average ReadSharedReq mshr miss latency
1166 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984 # average ReadSharedReq mshr miss latency
1167 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency
1168 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency
1169 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency
1170 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency
1171 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency
1172 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency
1173 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency
1174 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency
1175 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency
1176 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency
1177 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency
1178 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587 # average ReadReq mshr uncacheable latency
1179 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460 # average ReadReq mshr uncacheable latency
1180 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency
1181 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586 # average overall mshr uncacheable latency
1182 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847 # average overall mshr uncacheable latency
1183 system.cpu.toL2Bus.snoop_filter.tot_requests 7507397 # Total number of requests made to the snoop filter.
1184 system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770030 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1185 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58003 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1186 system.cpu.toL2Bus.snoop_filter.tot_snoops 175 # Total number of snoops made to the snoop filter.
1187 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 175 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1188 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1189 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1190 system.cpu.toL2Bus.trans_dist::ReadReq 136990 # Transaction distribution
1191 system.cpu.toL2Bus.trans_dist::ReadResp 3578080 # Transaction distribution
1192 system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
1193 system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
1194 system.cpu.toL2Bus.trans_dist::WritebackDirty 790742 # Transaction distribution
1195 system.cpu.toL2Bus.trans_dist::WritebackClean 2891615 # Transaction distribution
1196 system.cpu.toL2Bus.trans_dist::CleanEvict 151079 # Transaction distribution
1197 system.cpu.toL2Bus.trans_dist::UpgradeReq 2790 # Transaction distribution
1198 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1199 system.cpu.toL2Bus.trans_dist::UpgradeResp 2792 # Transaction distribution
1200 system.cpu.toL2Bus.trans_dist::ReadExReq 296457 # Transaction distribution
1201 system.cpu.toL2Bus.trans_dist::ReadExResp 296457 # Transaction distribution
1202 system.cpu.toL2Bus.trans_dist::ReadCleanReq 2892139 # Transaction distribution
1203 system.cpu.toL2Bus.trans_dist::ReadSharedReq 549026 # Transaction distribution
1204 system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution
1205 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8682092 # Packet count per connected master and slave (bytes)
1206 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658406 # Packet count per connected master and slave (bytes)
1207 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14762 # Packet count per connected master and slave (bytes)
1208 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159854 # Packet count per connected master and slave (bytes)
1209 system.cpu.toL2Bus.pkt_count::total 11515114 # Packet count per connected master and slave (bytes)
1210 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370357376 # Cumulative packet size per connected master and slave (bytes)
1211 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99233193 # Cumulative packet size per connected master and slave (bytes)
1212 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13496 # Cumulative packet size per connected master and slave (bytes)
1213 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 274004 # Cumulative packet size per connected master and slave (bytes)
1214 system.cpu.toL2Bus.pkt_size::total 469878069 # Cumulative packet size per connected master and slave (bytes)
1215 system.cpu.toL2Bus.snoops 132782 # Total snoops (count)
1216 system.cpu.toL2Bus.snoopTraffic 5798856 # Total snoop traffic (bytes)
1217 system.cpu.toL2Bus.snoop_fanout::samples 4006498 # Request fanout histogram
1218 system.cpu.toL2Bus.snoop_fanout::mean 0.022233 # Request fanout histogram
1219 system.cpu.toL2Bus.snoop_fanout::stdev 0.147442 # Request fanout histogram
1220 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1221 system.cpu.toL2Bus.snoop_fanout::0 3917420 97.78% 97.78% # Request fanout histogram
1222 system.cpu.toL2Bus.snoop_fanout::1 89078 2.22% 100.00% # Request fanout histogram
1223 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1224 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1225 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1226 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1227 system.cpu.toL2Bus.snoop_fanout::total 4006498 # Request fanout histogram
1228 system.cpu.toL2Bus.reqLayer0.occupancy 7428208500 # Layer occupancy (ticks)
1229 system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
1230 system.cpu.toL2Bus.snoopLayer0.occupancy 281377 # Layer occupancy (ticks)
1231 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1232 system.cpu.toL2Bus.respLayer0.occupancy 4343459350 # Layer occupancy (ticks)
1233 system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1234 system.cpu.toL2Bus.respLayer1.occupancy 1314433554 # Layer occupancy (ticks)
1235 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1236 system.cpu.toL2Bus.respLayer2.occupancy 11390994 # Layer occupancy (ticks)
1237 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1238 system.cpu.toL2Bus.respLayer3.occupancy 91384437 # Layer occupancy (ticks)
1239 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1240 system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1241 system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1242 system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1243 system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1244 system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1245 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1246 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1247 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1248 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1249 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1250 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1251 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1252 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1253 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1254 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1255 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1256 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1257 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1258 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1259 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1260 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1261 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1262 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1263 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1264 system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1265 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
1266 system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
1267 system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
1268 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1269 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1270 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
1271 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1272 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1273 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1274 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1275 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1276 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1277 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1278 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1279 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1280 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1281 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1282 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1283 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1284 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1285 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1286 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1287 system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1288 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
1289 system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
1290 system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
1291 system.iobus.reqLayer0.occupancy 46308000 # Layer occupancy (ticks)
1292 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1293 system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
1294 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1295 system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
1296 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1297 system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
1298 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1299 system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
1300 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1301 system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks)
1302 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1303 system.iobus.reqLayer8.occupancy 618500 # Layer occupancy (ticks)
1304 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1305 system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks)
1306 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1307 system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
1308 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1309 system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
1310 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1311 system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
1312 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1313 system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
1314 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1315 system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
1316 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1317 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1318 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1319 system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
1320 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1321 system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks)
1322 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1323 system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks)
1324 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1325 system.iobus.reqLayer23.occupancy 6088500 # Layer occupancy (ticks)
1326 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1327 system.iobus.reqLayer24.occupancy 39091500 # Layer occupancy (ticks)
1328 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1329 system.iobus.reqLayer25.occupancy 187755828 # Layer occupancy (ticks)
1330 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1331 system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1332 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1333 system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
1334 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1335 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1336 system.iocache.tags.replacements 36424 # number of replacements
1337 system.iocache.tags.tagsinuse 1.033906 # Cycle average of tags in use
1338 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1339 system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1340 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1341 system.iocache.tags.warmup_cycle 272036495000 # Cycle when the warmup percentage was hit.
1342 system.iocache.tags.occ_blocks::realview.ide 1.033906 # Average occupied blocks per requestor
1343 system.iocache.tags.occ_percent::realview.ide 0.064619 # Average percentage of cache occupancy
1344 system.iocache.tags.occ_percent::total 0.064619 # Average percentage of cache occupancy
1345 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1346 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1347 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1348 system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1349 system.iocache.tags.data_accesses 328122 # Number of data accesses
1350 system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1351 system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1352 system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1353 system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1354 system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1355 system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
1356 system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
1357 system.iocache.overall_misses::realview.ide 36458 # number of overall misses
1358 system.iocache.overall_misses::total 36458 # number of overall misses
1359 system.iocache.ReadReq_miss_latency::realview.ide 37411877 # number of ReadReq miss cycles
1360 system.iocache.ReadReq_miss_latency::total 37411877 # number of ReadReq miss cycles
1361 system.iocache.WriteLineReq_miss_latency::realview.ide 4363182951 # number of WriteLineReq miss cycles
1362 system.iocache.WriteLineReq_miss_latency::total 4363182951 # number of WriteLineReq miss cycles
1363 system.iocache.demand_miss_latency::realview.ide 4400594828 # number of demand (read+write) miss cycles
1364 system.iocache.demand_miss_latency::total 4400594828 # number of demand (read+write) miss cycles
1365 system.iocache.overall_miss_latency::realview.ide 4400594828 # number of overall miss cycles
1366 system.iocache.overall_miss_latency::total 4400594828 # number of overall miss cycles
1367 system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1368 system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1369 system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1370 system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1371 system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
1372 system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
1373 system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
1374 system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
1375 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1376 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1377 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1378 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1379 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1380 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1381 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1382 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1383 system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239 # average ReadReq miss latency
1384 system.iocache.ReadReq_avg_miss_latency::total 159879.816239 # average ReadReq miss latency
1385 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381 # average WriteLineReq miss latency
1386 system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381 # average WriteLineReq miss latency
1387 system.iocache.demand_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency
1388 system.iocache.demand_avg_miss_latency::total 120703.133140 # average overall miss latency
1389 system.iocache.overall_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency
1390 system.iocache.overall_avg_miss_latency::total 120703.133140 # average overall miss latency
1391 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1392 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1393 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1394 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1395 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1396 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1397 system.iocache.writebacks::writebacks 36190 # number of writebacks
1398 system.iocache.writebacks::total 36190 # number of writebacks
1399 system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1400 system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1401 system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1402 system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1403 system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
1404 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
1405 system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
1406 system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
1407 system.iocache.ReadReq_mshr_miss_latency::realview.ide 25711877 # number of ReadReq MSHR miss cycles
1408 system.iocache.ReadReq_mshr_miss_latency::total 25711877 # number of ReadReq MSHR miss cycles
1409 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549871160 # number of WriteLineReq MSHR miss cycles
1410 system.iocache.WriteLineReq_mshr_miss_latency::total 2549871160 # number of WriteLineReq MSHR miss cycles
1411 system.iocache.demand_mshr_miss_latency::realview.ide 2575583037 # number of demand (read+write) MSHR miss cycles
1412 system.iocache.demand_mshr_miss_latency::total 2575583037 # number of demand (read+write) MSHR miss cycles
1413 system.iocache.overall_mshr_miss_latency::realview.ide 2575583037 # number of overall MSHR miss cycles
1414 system.iocache.overall_mshr_miss_latency::total 2575583037 # number of overall MSHR miss cycles
1415 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1416 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1417 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1418 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1419 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1420 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1421 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1422 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1423 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239 # average ReadReq mshr miss latency
1424 system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239 # average ReadReq mshr miss latency
1425 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263 # average WriteLineReq mshr miss latency
1426 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263 # average WriteLineReq mshr miss latency
1427 system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency
1428 system.iocache.demand_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency
1429 system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency
1430 system.iocache.overall_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency
1431 system.membus.snoop_filter.tot_requests 337068 # Total number of requests made to the snoop filter.
1432 system.membus.snoop_filter.hit_single_requests 138136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1433 system.membus.snoop_filter.hit_multi_requests 489 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1434 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1435 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1436 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1437 system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1438 system.membus.trans_dist::ReadReq 34249 # Transaction distribution
1439 system.membus.trans_dist::ReadResp 71739 # Transaction distribution
1440 system.membus.trans_dist::WriteReq 27584 # Transaction distribution
1441 system.membus.trans_dist::WriteResp 27584 # Transaction distribution
1442 system.membus.trans_dist::WritebackDirty 124683 # Transaction distribution
1443 system.membus.trans_dist::CleanEvict 8839 # Transaction distribution
1444 system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
1445 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1446 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1447 system.membus.trans_dist::ReadExReq 129646 # Transaction distribution
1448 system.membus.trans_dist::ReadExResp 129646 # Transaction distribution
1449 system.membus.trans_dist::ReadSharedReq 37490 # Transaction distribution
1450 system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1451 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1452 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
1453 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes)
1454 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446846 # Packet count per connected master and slave (bytes)
1455 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554414 # Packet count per connected master and slave (bytes)
1456 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
1457 system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
1458 system.membus.pkt_count::total 627311 # Packet count per connected master and slave (bytes)
1459 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1460 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
1461 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes)
1462 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16546016 # Cumulative packet size per connected master and slave (bytes)
1463 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16709801 # Cumulative packet size per connected master and slave (bytes)
1464 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1465 system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1466 system.membus.pkt_size::total 19026921 # Cumulative packet size per connected master and slave (bytes)
1467 system.membus.snoops 505 # Total snoops (count)
1468 system.membus.snoopTraffic 32192 # Total snoop traffic (bytes)
1469 system.membus.snoop_fanout::samples 265323 # Request fanout histogram
1470 system.membus.snoop_fanout::mean 0.018540 # Request fanout histogram
1471 system.membus.snoop_fanout::stdev 0.134893 # Request fanout histogram
1472 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1473 system.membus.snoop_fanout::0 260404 98.15% 98.15% # Request fanout histogram
1474 system.membus.snoop_fanout::1 4919 1.85% 100.00% # Request fanout histogram
1475 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1476 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1477 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1478 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1479 system.membus.snoop_fanout::total 265323 # Request fanout histogram
1480 system.membus.reqLayer0.occupancy 92820000 # Layer occupancy (ticks)
1481 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1482 system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks)
1483 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1484 system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks)
1485 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1486 system.membus.reqLayer5.occupancy 905922529 # Layer occupancy (ticks)
1487 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1488 system.membus.respLayer2.occupancy 989794500 # Layer occupancy (ticks)
1489 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1490 system.membus.respLayer3.occupancy 1230123 # Layer occupancy (ticks)
1491 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1492 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1493 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1494 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1495 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1496 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1497 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1498 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1499 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1500 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1501 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1502 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1503 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1504 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1505 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1506 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1507 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1508 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1509 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1510 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1511 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1512 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1513 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1514 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1515 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1516 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1517 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1518 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1519 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1520 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1521 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1522 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1523 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1524 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1525 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1526 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1527 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1528 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1529 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1530 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1531 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1532 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1533 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1534 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1535 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1536 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1537 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1538 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1539 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1540 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1541 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1542 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1543 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1544 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1545 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1546 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1547 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1548 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1549 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1550 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1551 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1552 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1553 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1554 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1555 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1556 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1557 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1558 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1559 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1560 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
1562 ---------- End Simulation Statistics ----------
projects / gem5.git / blob