tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/arm/projectscratch/pd/sysrandd/dist/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 load_addr_mask=268435455
  35 load_offset=0
  36 machine_type=RealView_PBX
  37 mem_mode=timing
  38 mem_ranges=0:134217727
  39 memories=system.physmem system.realview.nvmem
  40 multi_proc=true
  41 num_work_ids=16
  42 panic_on_oops=true
  43 panic_on_panic=true
  44 phys_addr_range_64=40
  45 readfile=tests/halt.sh
  46 reset_addr_64=0
  47 symbolfile=
  48 work_begin_ckpt_count=0
  49 work_begin_cpu_id_exit=-1
  50 work_begin_exit_count=0
  51 work_cpus_ckpt_count=0
  52 work_end_ckpt_count=0
  53 work_end_exit_count=0
  54 work_item_id=-1
  55 system_port=system.membus.slave[0]
  56
  57 [system.bridge]
  58 type=Bridge
  59 clk_domain=system.clk_domain
  60 delay=50000
  61 eventq_index=0
  62 ranges=268435456:520093695 1073741824:1610612735
  63 req_size=16
  64 resp_size=16
  65 master=system.iobus.slave[0]
  66 slave=system.membus.master[0]
  67
  68 [system.cf0]
  69 type=IdeDisk
  70 children=image
  71 delay=1000000
  72 driveID=master
  73 eventq_index=0
  74 image=system.cf0.image
  75
  76 [system.cf0.image]
  77 type=CowDiskImage
  78 children=child
  79 child=system.cf0.image.child
  80 eventq_index=0
  81 image_file=
  82 read_only=false
  83 table_size=65536
  84
  85 [system.cf0.image.child]
  86 type=RawDiskImage
  87 eventq_index=0
  88 image_file=/arm/projectscratch/pd/sysrandd/dist/disks/linux-arm-ael.img
  89 read_only=true
  90
  91 [system.clk_domain]
  92 type=SrcClockDomain
  93 clock=1000
  94 eventq_index=0
  95 voltage_domain=system.voltage_domain
  96
  97 [system.cpu0]
  98 type=MinorCPU
  99 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
 100 branchPred=system.cpu0.branchPred
 101 checker=Null
 102 clk_domain=system.cpu_clk_domain
 103 cpu_id=0
 104 decodeCycleInput=true
 105 decodeInputBufferSize=3
 106 decodeInputWidth=2
 107 decodeToExecuteForwardDelay=1
 108 do_checkpoint_insts=true
 109 do_quiesce=true
 110 do_statistics_insts=true
 111 dstage2_mmu=system.cpu0.dstage2_mmu
 112 dtb=system.cpu0.dtb
 113 enableIdling=true
 114 eventq_index=0
 115 executeAllowEarlyMemoryIssue=true
 116 executeBranchDelay=1
 117 executeCommitLimit=2
 118 executeCycleInput=true
 119 executeFuncUnits=system.cpu0.executeFuncUnits
 120 executeInputBufferSize=7
 121 executeInputWidth=2
 122 executeIssueLimit=2
 123 executeLSQMaxStoreBufferStoresPerCycle=2
 124 executeLSQRequestsQueueSize=1
 125 executeLSQStoreBufferSize=5
 126 executeLSQTransfersQueueSize=2
 127 executeMaxAccessesInMemory=2
 128 executeMemoryCommitLimit=1
 129 executeMemoryIssueLimit=1
 130 executeMemoryWidth=0
 131 executeSetTraceTimeOnCommit=true
 132 executeSetTraceTimeOnIssue=false
 133 fetch1FetchLimit=1
 134 fetch1LineSnapWidth=0
 135 fetch1LineWidth=0
 136 fetch1ToFetch2BackwardDelay=1
 137 fetch1ToFetch2ForwardDelay=1
 138 fetch2CycleInput=true
 139 fetch2InputBufferSize=2
 140 fetch2ToDecodeForwardDelay=1
 141 function_trace=false
 142 function_trace_start=0
 143 interrupts=system.cpu0.interrupts
 144 isa=system.cpu0.isa
 145 istage2_mmu=system.cpu0.istage2_mmu
 146 itb=system.cpu0.itb
 147 max_insts_all_threads=0
 148 max_insts_any_thread=0
 149 max_loads_all_threads=0
 150 max_loads_any_thread=0
 151 numThreads=1
 152 profile=0
 153 progress_interval=0
 154 simpoint_start_insts=
 155 switched_out=false
 156 system=system
 157 tracer=system.cpu0.tracer
 158 workload=
 159 dcache_port=system.cpu0.dcache.cpu_side
 160 icache_port=system.cpu0.icache.cpu_side
 161
 162 [system.cpu0.branchPred]
 163 type=BranchPredictor
 164 BTBEntries=4096
 165 BTBTagSize=16
 166 RASSize=16
 167 choiceCtrBits=2
 168 choicePredictorSize=8192
 169 eventq_index=0
 170 globalCtrBits=2
 171 globalPredictorSize=8192
 172 instShiftAmt=2
 173 localCtrBits=2
 174 localHistoryTableSize=2048
 175 localPredictorSize=2048
 176 numThreads=1
 177 predType=tournament
 178
 179 [system.cpu0.dcache]
 180 type=BaseCache
 181 children=tags
 182 addr_ranges=0:18446744073709551615
 183 assoc=4
 184 clk_domain=system.cpu_clk_domain
 185 eventq_index=0
 186 forward_snoops=true
 187 hit_latency=2
 188 is_top_level=true
 189 max_miss_count=0
 190 mshrs=4
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=2
 194 sequential_access=false
 195 size=32768
 196 system=system
 197 tags=system.cpu0.dcache.tags
 198 tgts_per_mshr=20
 199 two_queue=false
 200 write_buffers=8
 201 cpu_side=system.cpu0.dcache_port
 202 mem_side=system.toL2Bus.slave[1]
 203
 204 [system.cpu0.dcache.tags]
 205 type=LRU
 206 assoc=4
 207 block_size=64
 208 clk_domain=system.cpu_clk_domain
 209 eventq_index=0
 210 hit_latency=2
 211 sequential_access=false
 212 size=32768
 213
 214 [system.cpu0.dstage2_mmu]
 215 type=ArmStage2MMU
 216 children=stage2_tlb
 217 eventq_index=0
 218 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 219 tlb=system.cpu0.dtb
 220
 221 [system.cpu0.dstage2_mmu.stage2_tlb]
 222 type=ArmTLB
 223 children=walker
 224 eventq_index=0
 225 is_stage2=true
 226 size=32
 227 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 228
 229 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 230 type=ArmTableWalker
 231 clk_domain=system.cpu_clk_domain
 232 eventq_index=0
 233 is_stage2=true
 234 num_squash_per_cycle=2
 235 sys=system
 236 port=system.toL2Bus.slave[5]
 237
 238 [system.cpu0.dtb]
 239 type=ArmTLB
 240 children=walker
 241 eventq_index=0
 242 is_stage2=false
 243 size=64
 244 walker=system.cpu0.dtb.walker
 245
 246 [system.cpu0.dtb.walker]
 247 type=ArmTableWalker
 248 clk_domain=system.cpu_clk_domain
 249 eventq_index=0
 250 is_stage2=false
 251 num_squash_per_cycle=2
 252 sys=system
 253 port=system.toL2Bus.slave[3]
 254
 255 [system.cpu0.executeFuncUnits]
 256 type=MinorFUPool
 257 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 258 eventq_index=0
 259 funcUnits=system.cpu0.executeFuncUnits.funcUnits0 system.cpu0.executeFuncUnits.funcUnits1 system.cpu0.executeFuncUnits.funcUnits2 system.cpu0.executeFuncUnits.funcUnits3 system.cpu0.executeFuncUnits.funcUnits4 system.cpu0.executeFuncUnits.funcUnits5 system.cpu0.executeFuncUnits.funcUnits6
 260
 261 [system.cpu0.executeFuncUnits.funcUnits0]
 262 type=MinorFU
 263 children=opClasses timings
 264 eventq_index=0
 265 issueLat=1
 266 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses
 267 opLat=3
 268 timings=system.cpu0.executeFuncUnits.funcUnits0.timings
 269
 270 [system.cpu0.executeFuncUnits.funcUnits0.opClasses]
 271 type=MinorOpClassSet
 272 children=opClasses
 273 eventq_index=0
 274 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses
 275
 276 [system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses]
 277 type=MinorOpClass
 278 eventq_index=0
 279 opClass=IntAlu
 280
 281 [system.cpu0.executeFuncUnits.funcUnits0.timings]
 282 type=MinorFUTiming
 283 children=opClasses
 284 description=Int
 285 eventq_index=0
 286 extraAssumedLat=0
 287 extraCommitLat=0
 288 extraCommitLatExpr=Null
 289 mask=0
 290 match=0
 291 opClasses=system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses
 292 srcRegsRelativeLats=2
 293 suppress=false
 294
 295 [system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses]
 296 type=MinorOpClassSet
 297 eventq_index=0
 298 opClasses=
 299
 300 [system.cpu0.executeFuncUnits.funcUnits1]
 301 type=MinorFU
 302 children=opClasses timings
 303 eventq_index=0
 304 issueLat=1
 305 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses
 306 opLat=3
 307 timings=system.cpu0.executeFuncUnits.funcUnits1.timings
 308
 309 [system.cpu0.executeFuncUnits.funcUnits1.opClasses]
 310 type=MinorOpClassSet
 311 children=opClasses
 312 eventq_index=0
 313 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses
 314
 315 [system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses]
 316 type=MinorOpClass
 317 eventq_index=0
 318 opClass=IntAlu
 319
 320 [system.cpu0.executeFuncUnits.funcUnits1.timings]
 321 type=MinorFUTiming
 322 children=opClasses
 323 description=Int
 324 eventq_index=0
 325 extraAssumedLat=0
 326 extraCommitLat=0
 327 extraCommitLatExpr=Null
 328 mask=0
 329 match=0
 330 opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses
 331 srcRegsRelativeLats=2
 332 suppress=false
 333
 334 [system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses]
 335 type=MinorOpClassSet
 336 eventq_index=0
 337 opClasses=
 338
 339 [system.cpu0.executeFuncUnits.funcUnits2]
 340 type=MinorFU
 341 children=opClasses timings
 342 eventq_index=0
 343 issueLat=1
 344 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses
 345 opLat=3
 346 timings=system.cpu0.executeFuncUnits.funcUnits2.timings
 347
 348 [system.cpu0.executeFuncUnits.funcUnits2.opClasses]
 349 type=MinorOpClassSet
 350 children=opClasses
 351 eventq_index=0
 352 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses
 353
 354 [system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses]
 355 type=MinorOpClass
 356 eventq_index=0
 357 opClass=IntMult
 358
 359 [system.cpu0.executeFuncUnits.funcUnits2.timings]
 360 type=MinorFUTiming
 361 children=opClasses
 362 description=Mul
 363 eventq_index=0
 364 extraAssumedLat=0
 365 extraCommitLat=0
 366 extraCommitLatExpr=Null
 367 mask=0
 368 match=0
 369 opClasses=system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses
 370 srcRegsRelativeLats=0
 371 suppress=false
 372
 373 [system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses]
 374 type=MinorOpClassSet
 375 eventq_index=0
 376 opClasses=
 377
 378 [system.cpu0.executeFuncUnits.funcUnits3]
 379 type=MinorFU
 380 children=opClasses
 381 eventq_index=0
 382 issueLat=9
 383 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses
 384 opLat=9
 385 timings=
 386
 387 [system.cpu0.executeFuncUnits.funcUnits3.opClasses]
 388 type=MinorOpClassSet
 389 children=opClasses
 390 eventq_index=0
 391 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses
 392
 393 [system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses]
 394 type=MinorOpClass
 395 eventq_index=0
 396 opClass=IntDiv
 397
 398 [system.cpu0.executeFuncUnits.funcUnits4]
 399 type=MinorFU
 400 children=opClasses timings
 401 eventq_index=0
 402 issueLat=1
 403 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses
 404 opLat=6
 405 timings=system.cpu0.executeFuncUnits.funcUnits4.timings
 406
 407 [system.cpu0.executeFuncUnits.funcUnits4.opClasses]
 408 type=MinorOpClassSet
 409 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 410 eventq_index=0
 411 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25
 412
 413 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 414 type=MinorOpClass
 415 eventq_index=0
 416 opClass=FloatAdd
 417
 418 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 419 type=MinorOpClass
 420 eventq_index=0
 421 opClass=FloatCmp
 422
 423 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 424 type=MinorOpClass
 425 eventq_index=0
 426 opClass=FloatCvt
 427
 428 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 429 type=MinorOpClass
 430 eventq_index=0
 431 opClass=FloatMult
 432
 433 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 434 type=MinorOpClass
 435 eventq_index=0
 436 opClass=FloatDiv
 437
 438 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 439 type=MinorOpClass
 440 eventq_index=0
 441 opClass=FloatSqrt
 442
 443 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 444 type=MinorOpClass
 445 eventq_index=0
 446 opClass=SimdAdd
 447
 448 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 449 type=MinorOpClass
 450 eventq_index=0
 451 opClass=SimdAddAcc
 452
 453 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 454 type=MinorOpClass
 455 eventq_index=0
 456 opClass=SimdAlu
 457
 458 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 459 type=MinorOpClass
 460 eventq_index=0
 461 opClass=SimdCmp
 462
 463 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 464 type=MinorOpClass
 465 eventq_index=0
 466 opClass=SimdCvt
 467
 468 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 469 type=MinorOpClass
 470 eventq_index=0
 471 opClass=SimdMisc
 472
 473 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 474 type=MinorOpClass
 475 eventq_index=0
 476 opClass=SimdMult
 477
 478 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 479 type=MinorOpClass
 480 eventq_index=0
 481 opClass=SimdMultAcc
 482
 483 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 484 type=MinorOpClass
 485 eventq_index=0
 486 opClass=SimdShift
 487
 488 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 489 type=MinorOpClass
 490 eventq_index=0
 491 opClass=SimdShiftAcc
 492
 493 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 494 type=MinorOpClass
 495 eventq_index=0
 496 opClass=SimdSqrt
 497
 498 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 499 type=MinorOpClass
 500 eventq_index=0
 501 opClass=SimdFloatAdd
 502
 503 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 504 type=MinorOpClass
 505 eventq_index=0
 506 opClass=SimdFloatAlu
 507
 508 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 509 type=MinorOpClass
 510 eventq_index=0
 511 opClass=SimdFloatCmp
 512
 513 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 514 type=MinorOpClass
 515 eventq_index=0
 516 opClass=SimdFloatCvt
 517
 518 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 519 type=MinorOpClass
 520 eventq_index=0
 521 opClass=SimdFloatDiv
 522
 523 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 524 type=MinorOpClass
 525 eventq_index=0
 526 opClass=SimdFloatMisc
 527
 528 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 529 type=MinorOpClass
 530 eventq_index=0
 531 opClass=SimdFloatMult
 532
 533 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 534 type=MinorOpClass
 535 eventq_index=0
 536 opClass=SimdFloatMultAcc
 537
 538 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 539 type=MinorOpClass
 540 eventq_index=0
 541 opClass=SimdFloatSqrt
 542
 543 [system.cpu0.executeFuncUnits.funcUnits4.timings]
 544 type=MinorFUTiming
 545 children=opClasses
 546 description=FloatSimd
 547 eventq_index=0
 548 extraAssumedLat=0
 549 extraCommitLat=0
 550 extraCommitLatExpr=Null
 551 mask=0
 552 match=0
 553 opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses
 554 srcRegsRelativeLats=2
 555 suppress=false
 556
 557 [system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses]
 558 type=MinorOpClassSet
 559 eventq_index=0
 560 opClasses=
 561
 562 [system.cpu0.executeFuncUnits.funcUnits5]
 563 type=MinorFU
 564 children=opClasses timings
 565 eventq_index=0
 566 issueLat=1
 567 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses
 568 opLat=1
 569 timings=system.cpu0.executeFuncUnits.funcUnits5.timings
 570
 571 [system.cpu0.executeFuncUnits.funcUnits5.opClasses]
 572 type=MinorOpClassSet
 573 children=opClasses0 opClasses1
 574 eventq_index=0
 575 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1
 576
 577 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 578 type=MinorOpClass
 579 eventq_index=0
 580 opClass=MemRead
 581
 582 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 583 type=MinorOpClass
 584 eventq_index=0
 585 opClass=MemWrite
 586
 587 [system.cpu0.executeFuncUnits.funcUnits5.timings]
 588 type=MinorFUTiming
 589 children=opClasses
 590 description=Mem
 591 eventq_index=0
 592 extraAssumedLat=2
 593 extraCommitLat=0
 594 extraCommitLatExpr=Null
 595 mask=0
 596 match=0
 597 opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses
 598 srcRegsRelativeLats=1
 599 suppress=false
 600
 601 [system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses]
 602 type=MinorOpClassSet
 603 eventq_index=0
 604 opClasses=
 605
 606 [system.cpu0.executeFuncUnits.funcUnits6]
 607 type=MinorFU
 608 children=opClasses
 609 eventq_index=0
 610 issueLat=1
 611 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses
 612 opLat=1
 613 timings=
 614
 615 [system.cpu0.executeFuncUnits.funcUnits6.opClasses]
 616 type=MinorOpClassSet
 617 children=opClasses0 opClasses1
 618 eventq_index=0
 619 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1
 620
 621 [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 622 type=MinorOpClass
 623 eventq_index=0
 624 opClass=IprAccess
 625
 626 [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 627 type=MinorOpClass
 628 eventq_index=0
 629 opClass=InstPrefetch
 630
 631 [system.cpu0.icache]
 632 type=BaseCache
 633 children=tags
 634 addr_ranges=0:18446744073709551615
 635 assoc=1
 636 clk_domain=system.cpu_clk_domain
 637 eventq_index=0
 638 forward_snoops=true
 639 hit_latency=2
 640 is_top_level=true
 641 max_miss_count=0
 642 mshrs=4
 643 prefetch_on_access=false
 644 prefetcher=Null
 645 response_latency=2
 646 sequential_access=false
 647 size=32768
 648 system=system
 649 tags=system.cpu0.icache.tags
 650 tgts_per_mshr=20
 651 two_queue=false
 652 write_buffers=8
 653 cpu_side=system.cpu0.icache_port
 654 mem_side=system.toL2Bus.slave[0]
 655
 656 [system.cpu0.icache.tags]
 657 type=LRU
 658 assoc=1
 659 block_size=64
 660 clk_domain=system.cpu_clk_domain
 661 eventq_index=0
 662 hit_latency=2
 663 sequential_access=false
 664 size=32768
 665
 666 [system.cpu0.interrupts]
 667 type=ArmInterrupts
 668 eventq_index=0
 669
 670 [system.cpu0.isa]
 671 type=ArmISA
 672 eventq_index=0
 673 fpsid=1090793632
 674 id_aa64afr0_el1=0
 675 id_aa64afr1_el1=0
 676 id_aa64dfr0_el1=1052678
 677 id_aa64dfr1_el1=0
 678 id_aa64isar0_el1=0
 679 id_aa64isar1_el1=0
 680 id_aa64mmfr0_el1=15728642
 681 id_aa64mmfr1_el1=0
 682 id_aa64pfr0_el1=17
 683 id_aa64pfr1_el1=0
 684 id_isar0=34607377
 685 id_isar1=34677009
 686 id_isar2=555950401
 687 id_isar3=17899825
 688 id_isar4=268501314
 689 id_isar5=0
 690 id_mmfr0=270536963
 691 id_mmfr1=0
 692 id_mmfr2=19070976
 693 id_mmfr3=34611729
 694 id_pfr0=49
 695 id_pfr1=4113
 696 midr=1091551472
 697 system=system
 698
 699 [system.cpu0.istage2_mmu]
 700 type=ArmStage2MMU
 701 children=stage2_tlb
 702 eventq_index=0
 703 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 704 tlb=system.cpu0.itb
 705
 706 [system.cpu0.istage2_mmu.stage2_tlb]
 707 type=ArmTLB
 708 children=walker
 709 eventq_index=0
 710 is_stage2=true
 711 size=32
 712 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 713
 714 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 715 type=ArmTableWalker
 716 clk_domain=system.cpu_clk_domain
 717 eventq_index=0
 718 is_stage2=true
 719 num_squash_per_cycle=2
 720 sys=system
 721 port=system.toL2Bus.slave[4]
 722
 723 [system.cpu0.itb]
 724 type=ArmTLB
 725 children=walker
 726 eventq_index=0
 727 is_stage2=false
 728 size=64
 729 walker=system.cpu0.itb.walker
 730
 731 [system.cpu0.itb.walker]
 732 type=ArmTableWalker
 733 clk_domain=system.cpu_clk_domain
 734 eventq_index=0
 735 is_stage2=false
 736 num_squash_per_cycle=2
 737 sys=system
 738 port=system.toL2Bus.slave[2]
 739
 740 [system.cpu0.tracer]
 741 type=ExeTracer
 742 eventq_index=0
 743
 744 [system.cpu1]
 745 type=MinorCPU
 746 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
 747 branchPred=system.cpu1.branchPred
 748 checker=Null
 749 clk_domain=system.cpu_clk_domain
 750 cpu_id=1
 751 decodeCycleInput=true
 752 decodeInputBufferSize=3
 753 decodeInputWidth=2
 754 decodeToExecuteForwardDelay=1
 755 do_checkpoint_insts=true
 756 do_quiesce=true
 757 do_statistics_insts=true
 758 dstage2_mmu=system.cpu1.dstage2_mmu
 759 dtb=system.cpu1.dtb
 760 enableIdling=true
 761 eventq_index=0
 762 executeAllowEarlyMemoryIssue=true
 763 executeBranchDelay=1
 764 executeCommitLimit=2
 765 executeCycleInput=true
 766 executeFuncUnits=system.cpu1.executeFuncUnits
 767 executeInputBufferSize=7
 768 executeInputWidth=2
 769 executeIssueLimit=2
 770 executeLSQMaxStoreBufferStoresPerCycle=2
 771 executeLSQRequestsQueueSize=1
 772 executeLSQStoreBufferSize=5
 773 executeLSQTransfersQueueSize=2
 774 executeMaxAccessesInMemory=2
 775 executeMemoryCommitLimit=1
 776 executeMemoryIssueLimit=1
 777 executeMemoryWidth=0
 778 executeSetTraceTimeOnCommit=true
 779 executeSetTraceTimeOnIssue=false
 780 fetch1FetchLimit=1
 781 fetch1LineSnapWidth=0
 782 fetch1LineWidth=0
 783 fetch1ToFetch2BackwardDelay=1
 784 fetch1ToFetch2ForwardDelay=1
 785 fetch2CycleInput=true
 786 fetch2InputBufferSize=2
 787 fetch2ToDecodeForwardDelay=1
 788 function_trace=false
 789 function_trace_start=0
 790 interrupts=system.cpu1.interrupts
 791 isa=system.cpu1.isa
 792 istage2_mmu=system.cpu1.istage2_mmu
 793 itb=system.cpu1.itb
 794 max_insts_all_threads=0
 795 max_insts_any_thread=0
 796 max_loads_all_threads=0
 797 max_loads_any_thread=0
 798 numThreads=1
 799 profile=0
 800 progress_interval=0
 801 simpoint_start_insts=
 802 switched_out=false
 803 system=system
 804 tracer=system.cpu1.tracer
 805 workload=
 806 dcache_port=system.cpu1.dcache.cpu_side
 807 icache_port=system.cpu1.icache.cpu_side
 808
 809 [system.cpu1.branchPred]
 810 type=BranchPredictor
 811 BTBEntries=4096
 812 BTBTagSize=16
 813 RASSize=16
 814 choiceCtrBits=2
 815 choicePredictorSize=8192
 816 eventq_index=0
 817 globalCtrBits=2
 818 globalPredictorSize=8192
 819 instShiftAmt=2
 820 localCtrBits=2
 821 localHistoryTableSize=2048
 822 localPredictorSize=2048
 823 numThreads=1
 824 predType=tournament
 825
 826 [system.cpu1.dcache]
 827 type=BaseCache
 828 children=tags
 829 addr_ranges=0:18446744073709551615
 830 assoc=4
 831 clk_domain=system.cpu_clk_domain
 832 eventq_index=0
 833 forward_snoops=true
 834 hit_latency=2
 835 is_top_level=true
 836 max_miss_count=0
 837 mshrs=4
 838 prefetch_on_access=false
 839 prefetcher=Null
 840 response_latency=2
 841 sequential_access=false
 842 size=32768
 843 system=system
 844 tags=system.cpu1.dcache.tags
 845 tgts_per_mshr=20
 846 two_queue=false
 847 write_buffers=8
 848 cpu_side=system.cpu1.dcache_port
 849 mem_side=system.toL2Bus.slave[7]
 850
 851 [system.cpu1.dcache.tags]
 852 type=LRU
 853 assoc=4
 854 block_size=64
 855 clk_domain=system.cpu_clk_domain
 856 eventq_index=0
 857 hit_latency=2
 858 sequential_access=false
 859 size=32768
 860
 861 [system.cpu1.dstage2_mmu]
 862 type=ArmStage2MMU
 863 children=stage2_tlb
 864 eventq_index=0
 865 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 866 tlb=system.cpu1.dtb
 867
 868 [system.cpu1.dstage2_mmu.stage2_tlb]
 869 type=ArmTLB
 870 children=walker
 871 eventq_index=0
 872 is_stage2=true
 873 size=32
 874 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 875
 876 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 877 type=ArmTableWalker
 878 clk_domain=system.cpu_clk_domain
 879 eventq_index=0
 880 is_stage2=true
 881 num_squash_per_cycle=2
 882 sys=system
 883 port=system.toL2Bus.slave[11]
 884
 885 [system.cpu1.dtb]
 886 type=ArmTLB
 887 children=walker
 888 eventq_index=0
 889 is_stage2=false
 890 size=64
 891 walker=system.cpu1.dtb.walker
 892
 893 [system.cpu1.dtb.walker]
 894 type=ArmTableWalker
 895 clk_domain=system.cpu_clk_domain
 896 eventq_index=0
 897 is_stage2=false
 898 num_squash_per_cycle=2
 899 sys=system
 900 port=system.toL2Bus.slave[9]
 901
 902 [system.cpu1.executeFuncUnits]
 903 type=MinorFUPool
 904 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 905 eventq_index=0
 906 funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6
 907
 908 [system.cpu1.executeFuncUnits.funcUnits0]
 909 type=MinorFU
 910 children=opClasses timings
 911 eventq_index=0
 912 issueLat=1
 913 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses
 914 opLat=3
 915 timings=system.cpu1.executeFuncUnits.funcUnits0.timings
 916
 917 [system.cpu1.executeFuncUnits.funcUnits0.opClasses]
 918 type=MinorOpClassSet
 919 children=opClasses
 920 eventq_index=0
 921 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses
 922
 923 [system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses]
 924 type=MinorOpClass
 925 eventq_index=0
 926 opClass=IntAlu
 927
 928 [system.cpu1.executeFuncUnits.funcUnits0.timings]
 929 type=MinorFUTiming
 930 children=opClasses
 931 description=Int
 932 eventq_index=0
 933 extraAssumedLat=0
 934 extraCommitLat=0
 935 extraCommitLatExpr=Null
 936 mask=0
 937 match=0
 938 opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses
 939 srcRegsRelativeLats=2
 940 suppress=false
 941
 942 [system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses]
 943 type=MinorOpClassSet
 944 eventq_index=0
 945 opClasses=
 946
 947 [system.cpu1.executeFuncUnits.funcUnits1]
 948 type=MinorFU
 949 children=opClasses timings
 950 eventq_index=0
 951 issueLat=1
 952 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses
 953 opLat=3
 954 timings=system.cpu1.executeFuncUnits.funcUnits1.timings
 955
 956 [system.cpu1.executeFuncUnits.funcUnits1.opClasses]
 957 type=MinorOpClassSet
 958 children=opClasses
 959 eventq_index=0
 960 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses
 961
 962 [system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses]
 963 type=MinorOpClass
 964 eventq_index=0
 965 opClass=IntAlu
 966
 967 [system.cpu1.executeFuncUnits.funcUnits1.timings]
 968 type=MinorFUTiming
 969 children=opClasses
 970 description=Int
 971 eventq_index=0
 972 extraAssumedLat=0
 973 extraCommitLat=0
 974 extraCommitLatExpr=Null
 975 mask=0
 976 match=0
 977 opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses
 978 srcRegsRelativeLats=2
 979 suppress=false
 980
 981 [system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses]
 982 type=MinorOpClassSet
 983 eventq_index=0
 984 opClasses=
 985
 986 [system.cpu1.executeFuncUnits.funcUnits2]
 987 type=MinorFU
 988 children=opClasses timings
 989 eventq_index=0
 990 issueLat=1
 991 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses
 992 opLat=3
 993 timings=system.cpu1.executeFuncUnits.funcUnits2.timings
 994
 995 [system.cpu1.executeFuncUnits.funcUnits2.opClasses]
 996 type=MinorOpClassSet
 997 children=opClasses
 998 eventq_index=0
 999 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses
1000
1001 [system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses]
1002 type=MinorOpClass
1003 eventq_index=0
1004 opClass=IntMult
1005
1006 [system.cpu1.executeFuncUnits.funcUnits2.timings]
1007 type=MinorFUTiming
1008 children=opClasses
1009 description=Mul
1010 eventq_index=0
1011 extraAssumedLat=0
1012 extraCommitLat=0
1013 extraCommitLatExpr=Null
1014 mask=0
1015 match=0
1016 opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses
1017 srcRegsRelativeLats=0
1018 suppress=false
1019
1020 [system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses]
1021 type=MinorOpClassSet
1022 eventq_index=0
1023 opClasses=
1024
1025 [system.cpu1.executeFuncUnits.funcUnits3]
1026 type=MinorFU
1027 children=opClasses
1028 eventq_index=0
1029 issueLat=9
1030 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses
1031 opLat=9
1032 timings=
1033
1034 [system.cpu1.executeFuncUnits.funcUnits3.opClasses]
1035 type=MinorOpClassSet
1036 children=opClasses
1037 eventq_index=0
1038 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses
1039
1040 [system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses]
1041 type=MinorOpClass
1042 eventq_index=0
1043 opClass=IntDiv
1044
1045 [system.cpu1.executeFuncUnits.funcUnits4]
1046 type=MinorFU
1047 children=opClasses timings
1048 eventq_index=0
1049 issueLat=1
1050 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses
1051 opLat=6
1052 timings=system.cpu1.executeFuncUnits.funcUnits4.timings
1053
1054 [system.cpu1.executeFuncUnits.funcUnits4.opClasses]
1055 type=MinorOpClassSet
1056 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
1057 eventq_index=0
1058 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25
1059
1060 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
1061 type=MinorOpClass
1062 eventq_index=0
1063 opClass=FloatAdd
1064
1065 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01]
1066 type=MinorOpClass
1067 eventq_index=0
1068 opClass=FloatCmp
1069
1070 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02]
1071 type=MinorOpClass
1072 eventq_index=0
1073 opClass=FloatCvt
1074
1075 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
1076 type=MinorOpClass
1077 eventq_index=0
1078 opClass=FloatMult
1079
1080 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
1081 type=MinorOpClass
1082 eventq_index=0
1083 opClass=FloatDiv
1084
1085 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
1086 type=MinorOpClass
1087 eventq_index=0
1088 opClass=FloatSqrt
1089
1090 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
1091 type=MinorOpClass
1092 eventq_index=0
1093 opClass=SimdAdd
1094
1095 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
1096 type=MinorOpClass
1097 eventq_index=0
1098 opClass=SimdAddAcc
1099
1100 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
1101 type=MinorOpClass
1102 eventq_index=0
1103 opClass=SimdAlu
1104
1105 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
1106 type=MinorOpClass
1107 eventq_index=0
1108 opClass=SimdCmp
1109
1110 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
1111 type=MinorOpClass
1112 eventq_index=0
1113 opClass=SimdCvt
1114
1115 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
1116 type=MinorOpClass
1117 eventq_index=0
1118 opClass=SimdMisc
1119
1120 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
1121 type=MinorOpClass
1122 eventq_index=0
1123 opClass=SimdMult
1124
1125 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
1126 type=MinorOpClass
1127 eventq_index=0
1128 opClass=SimdMultAcc
1129
1130 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
1131 type=MinorOpClass
1132 eventq_index=0
1133 opClass=SimdShift
1134
1135 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
1136 type=MinorOpClass
1137 eventq_index=0
1138 opClass=SimdShiftAcc
1139
1140 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
1141 type=MinorOpClass
1142 eventq_index=0
1143 opClass=SimdSqrt
1144
1145 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
1146 type=MinorOpClass
1147 eventq_index=0
1148 opClass=SimdFloatAdd
1149
1150 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
1151 type=MinorOpClass
1152 eventq_index=0
1153 opClass=SimdFloatAlu
1154
1155 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
1156 type=MinorOpClass
1157 eventq_index=0
1158 opClass=SimdFloatCmp
1159
1160 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
1161 type=MinorOpClass
1162 eventq_index=0
1163 opClass=SimdFloatCvt
1164
1165 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
1166 type=MinorOpClass
1167 eventq_index=0
1168 opClass=SimdFloatDiv
1169
1170 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
1171 type=MinorOpClass
1172 eventq_index=0
1173 opClass=SimdFloatMisc
1174
1175 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
1176 type=MinorOpClass
1177 eventq_index=0
1178 opClass=SimdFloatMult
1179
1180 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
1181 type=MinorOpClass
1182 eventq_index=0
1183 opClass=SimdFloatMultAcc
1184
1185 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
1186 type=MinorOpClass
1187 eventq_index=0
1188 opClass=SimdFloatSqrt
1189
1190 [system.cpu1.executeFuncUnits.funcUnits4.timings]
1191 type=MinorFUTiming
1192 children=opClasses
1193 description=FloatSimd
1194 eventq_index=0
1195 extraAssumedLat=0
1196 extraCommitLat=0
1197 extraCommitLatExpr=Null
1198 mask=0
1199 match=0
1200 opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses
1201 srcRegsRelativeLats=2
1202 suppress=false
1203
1204 [system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses]
1205 type=MinorOpClassSet
1206 eventq_index=0
1207 opClasses=
1208
1209 [system.cpu1.executeFuncUnits.funcUnits5]
1210 type=MinorFU
1211 children=opClasses timings
1212 eventq_index=0
1213 issueLat=1
1214 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses
1215 opLat=1
1216 timings=system.cpu1.executeFuncUnits.funcUnits5.timings
1217
1218 [system.cpu1.executeFuncUnits.funcUnits5.opClasses]
1219 type=MinorOpClassSet
1220 children=opClasses0 opClasses1
1221 eventq_index=0
1222 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1
1223
1224 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
1225 type=MinorOpClass
1226 eventq_index=0
1227 opClass=MemRead
1228
1229 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1]
1230 type=MinorOpClass
1231 eventq_index=0
1232 opClass=MemWrite
1233
1234 [system.cpu1.executeFuncUnits.funcUnits5.timings]
1235 type=MinorFUTiming
1236 children=opClasses
1237 description=Mem
1238 eventq_index=0
1239 extraAssumedLat=2
1240 extraCommitLat=0
1241 extraCommitLatExpr=Null
1242 mask=0
1243 match=0
1244 opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses
1245 srcRegsRelativeLats=1
1246 suppress=false
1247
1248 [system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses]
1249 type=MinorOpClassSet
1250 eventq_index=0
1251 opClasses=
1252
1253 [system.cpu1.executeFuncUnits.funcUnits6]
1254 type=MinorFU
1255 children=opClasses
1256 eventq_index=0
1257 issueLat=1
1258 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses
1259 opLat=1
1260 timings=
1261
1262 [system.cpu1.executeFuncUnits.funcUnits6.opClasses]
1263 type=MinorOpClassSet
1264 children=opClasses0 opClasses1
1265 eventq_index=0
1266 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1
1267
1268 [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0]
1269 type=MinorOpClass
1270 eventq_index=0
1271 opClass=IprAccess
1272
1273 [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1]
1274 type=MinorOpClass
1275 eventq_index=0
1276 opClass=InstPrefetch
1277
1278 [system.cpu1.icache]
1279 type=BaseCache
1280 children=tags
1281 addr_ranges=0:18446744073709551615
1282 assoc=1
1283 clk_domain=system.cpu_clk_domain
1284 eventq_index=0
1285 forward_snoops=true
1286 hit_latency=2
1287 is_top_level=true
1288 max_miss_count=0
1289 mshrs=4
1290 prefetch_on_access=false
1291 prefetcher=Null
1292 response_latency=2
1293 sequential_access=false
1294 size=32768
1295 system=system
1296 tags=system.cpu1.icache.tags
1297 tgts_per_mshr=20
1298 two_queue=false
1299 write_buffers=8
1300 cpu_side=system.cpu1.icache_port
1301 mem_side=system.toL2Bus.slave[6]
1302
1303 [system.cpu1.icache.tags]
1304 type=LRU
1305 assoc=1
1306 block_size=64
1307 clk_domain=system.cpu_clk_domain
1308 eventq_index=0
1309 hit_latency=2
1310 sequential_access=false
1311 size=32768
1312
1313 [system.cpu1.interrupts]
1314 type=ArmInterrupts
1315 eventq_index=0
1316
1317 [system.cpu1.isa]
1318 type=ArmISA
1319 eventq_index=0
1320 fpsid=1090793632
1321 id_aa64afr0_el1=0
1322 id_aa64afr1_el1=0
1323 id_aa64dfr0_el1=1052678
1324 id_aa64dfr1_el1=0
1325 id_aa64isar0_el1=0
1326 id_aa64isar1_el1=0
1327 id_aa64mmfr0_el1=15728642
1328 id_aa64mmfr1_el1=0
1329 id_aa64pfr0_el1=17
1330 id_aa64pfr1_el1=0
1331 id_isar0=34607377
1332 id_isar1=34677009
1333 id_isar2=555950401
1334 id_isar3=17899825
1335 id_isar4=268501314
1336 id_isar5=0
1337 id_mmfr0=270536963
1338 id_mmfr1=0
1339 id_mmfr2=19070976
1340 id_mmfr3=34611729
1341 id_pfr0=49
1342 id_pfr1=4113
1343 midr=1091551472
1344 system=system
1345
1346 [system.cpu1.istage2_mmu]
1347 type=ArmStage2MMU
1348 children=stage2_tlb
1349 eventq_index=0
1350 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1351 tlb=system.cpu1.itb
1352
1353 [system.cpu1.istage2_mmu.stage2_tlb]
1354 type=ArmTLB
1355 children=walker
1356 eventq_index=0
1357 is_stage2=true
1358 size=32
1359 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1360
1361 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1362 type=ArmTableWalker
1363 clk_domain=system.cpu_clk_domain
1364 eventq_index=0
1365 is_stage2=true
1366 num_squash_per_cycle=2
1367 sys=system
1368 port=system.toL2Bus.slave[10]
1369
1370 [system.cpu1.itb]
1371 type=ArmTLB
1372 children=walker
1373 eventq_index=0
1374 is_stage2=false
1375 size=64
1376 walker=system.cpu1.itb.walker
1377
1378 [system.cpu1.itb.walker]
1379 type=ArmTableWalker
1380 clk_domain=system.cpu_clk_domain
1381 eventq_index=0
1382 is_stage2=false
1383 num_squash_per_cycle=2
1384 sys=system
1385 port=system.toL2Bus.slave[8]
1386
1387 [system.cpu1.tracer]
1388 type=ExeTracer
1389 eventq_index=0
1390
1391 [system.cpu_clk_domain]
1392 type=SrcClockDomain
1393 clock=500
1394 eventq_index=0
1395 voltage_domain=system.voltage_domain
1396
1397 [system.intrctrl]
1398 type=IntrControl
1399 eventq_index=0
1400 sys=system
1401
1402 [system.iobus]
1403 type=NoncoherentBus
1404 clk_domain=system.clk_domain
1405 eventq_index=0
1406 header_cycles=1
1407 use_default_range=false
1408 width=8
1409 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1410 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1411
1412 [system.iocache]
1413 type=BaseCache
1414 children=tags
1415 addr_ranges=0:134217727
1416 assoc=8
1417 clk_domain=system.clk_domain
1418 eventq_index=0
1419 forward_snoops=false
1420 hit_latency=50
1421 is_top_level=true
1422 max_miss_count=0
1423 mshrs=20
1424 prefetch_on_access=false
1425 prefetcher=Null
1426 response_latency=50
1427 sequential_access=false
1428 size=1024
1429 system=system
1430 tags=system.iocache.tags
1431 tgts_per_mshr=12
1432 two_queue=false
1433 write_buffers=8
1434 cpu_side=system.iobus.master[25]
1435 mem_side=system.membus.slave[2]
1436
1437 [system.iocache.tags]
1438 type=LRU
1439 assoc=8
1440 block_size=64
1441 clk_domain=system.clk_domain
1442 eventq_index=0
1443 hit_latency=50
1444 sequential_access=false
1445 size=1024
1446
1447 [system.l2c]
1448 type=BaseCache
1449 children=tags
1450 addr_ranges=0:18446744073709551615
1451 assoc=8
1452 clk_domain=system.cpu_clk_domain
1453 eventq_index=0
1454 forward_snoops=true
1455 hit_latency=20
1456 is_top_level=false
1457 max_miss_count=0
1458 mshrs=20
1459 prefetch_on_access=false
1460 prefetcher=Null
1461 response_latency=20
1462 sequential_access=false
1463 size=4194304
1464 system=system
1465 tags=system.l2c.tags
1466 tgts_per_mshr=12
1467 two_queue=false
1468 write_buffers=8
1469 cpu_side=system.toL2Bus.master[0]
1470 mem_side=system.membus.slave[1]
1471
1472 [system.l2c.tags]
1473 type=LRU
1474 assoc=8
1475 block_size=64
1476 clk_domain=system.cpu_clk_domain
1477 eventq_index=0
1478 hit_latency=20
1479 sequential_access=false
1480 size=4194304
1481
1482 [system.membus]
1483 type=CoherentBus
1484 children=badaddr_responder
1485 clk_domain=system.clk_domain
1486 eventq_index=0
1487 header_cycles=1
1488 system=system
1489 use_default_range=false
1490 width=8
1491 default=system.membus.badaddr_responder.pio
1492 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
1493 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1494
1495 [system.membus.badaddr_responder]
1496 type=IsaFake
1497 clk_domain=system.clk_domain
1498 eventq_index=0
1499 fake_mem=false
1500 pio_addr=0
1501 pio_latency=100000
1502 pio_size=8
1503 ret_bad_addr=true
1504 ret_data16=65535
1505 ret_data32=4294967295
1506 ret_data64=18446744073709551615
1507 ret_data8=255
1508 system=system
1509 update_data=false
1510 warn_access=warn
1511 pio=system.membus.default
1512
1513 [system.physmem]
1514 type=DRAMCtrl
1515 activation_limit=4
1516 addr_mapping=RoRaBaChCo
1517 banks_per_rank=8
1518 burst_length=8
1519 channels=1
1520 clk_domain=system.clk_domain
1521 conf_table_reported=true
1522 device_bus_width=8
1523 device_rowbuffer_size=1024
1524 devices_per_rank=8
1525 eventq_index=0
1526 in_addr_map=true
1527 max_accesses_per_row=16
1528 mem_sched_policy=frfcfs
1529 min_writes_per_switch=16
1530 null=false
1531 page_policy=open_adaptive
1532 range=0:134217727
1533 ranks_per_channel=2
1534 read_buffer_size=32
1535 static_backend_latency=10000
1536 static_frontend_latency=10000
1537 tBURST=5000
1538 tCL=13750
1539 tRAS=35000
1540 tRCD=13750
1541 tREFI=7800000
1542 tRFC=300000
1543 tRP=13750
1544 tRRD=6250
1545 tWTR=7500
1546 tXAW=40000
1547 write_buffer_size=64
1548 write_high_thresh_perc=85
1549 write_low_thresh_perc=50
1550 port=system.membus.master[6]
1551
1552 [system.realview]
1553 type=RealView
1554 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1555 eventq_index=0
1556 intrctrl=system.intrctrl
1557 max_mem_size=268435456
1558 mem_start_addr=0
1559 pci_cfg_base=0
1560 system=system
1561
1562 [system.realview.a9scu]
1563 type=A9SCU
1564 clk_domain=system.clk_domain
1565 eventq_index=0
1566 pio_addr=520093696
1567 pio_latency=100000
1568 system=system
1569 pio=system.membus.master[4]
1570
1571 [system.realview.aaci_fake]
1572 type=AmbaFake
1573 amba_id=0
1574 clk_domain=system.clk_domain
1575 eventq_index=0
1576 ignore_access=false
1577 pio_addr=268451840
1578 pio_latency=100000
1579 system=system
1580 pio=system.iobus.master[21]
1581
1582 [system.realview.cf_ctrl]
1583 type=IdeController
1584 BAR0=402653184
1585 BAR0LegacyIO=true
1586 BAR0Size=16
1587 BAR1=402653440
1588 BAR1LegacyIO=true
1589 BAR1Size=1
1590 BAR2=1
1591 BAR2LegacyIO=false
1592 BAR2Size=8
1593 BAR3=1
1594 BAR3LegacyIO=false
1595 BAR3Size=4
1596 BAR4=1
1597 BAR4LegacyIO=false
1598 BAR4Size=16
1599 BAR5=1
1600 BAR5LegacyIO=false
1601 BAR5Size=0
1602 BIST=0
1603 CacheLineSize=0
1604 CapabilityPtr=0
1605 CardbusCIS=0
1606 ClassCode=1
1607 Command=1
1608 DeviceID=28945
1609 ExpansionROM=0
1610 HeaderType=0
1611 InterruptLine=31
1612 InterruptPin=1
1613 LatencyTimer=0
1614 MSICAPBaseOffset=0
1615 MSICAPCapId=0
1616 MSICAPMaskBits=0
1617 MSICAPMsgAddr=0
1618 MSICAPMsgCtrl=0
1619 MSICAPMsgData=0
1620 MSICAPMsgUpperAddr=0
1621 MSICAPNextCapability=0
1622 MSICAPPendingBits=0
1623 MSIXCAPBaseOffset=0
1624 MSIXCAPCapId=0
1625 MSIXCAPNextCapability=0
1626 MSIXMsgCtrl=0
1627 MSIXPbaOffset=0
1628 MSIXTableOffset=0
1629 MaximumLatency=0
1630 MinimumGrant=0
1631 PMCAPBaseOffset=0
1632 PMCAPCapId=0
1633 PMCAPCapabilities=0
1634 PMCAPCtrlStatus=0
1635 PMCAPNextCapability=0
1636 PXCAPBaseOffset=0
1637 PXCAPCapId=0
1638 PXCAPCapabilities=0
1639 PXCAPDevCap2=0
1640 PXCAPDevCapabilities=0
1641 PXCAPDevCtrl=0
1642 PXCAPDevCtrl2=0
1643 PXCAPDevStatus=0
1644 PXCAPLinkCap=0
1645 PXCAPLinkCtrl=0
1646 PXCAPLinkStatus=0
1647 PXCAPNextCapability=0
1648 ProgIF=133
1649 Revision=0
1650 Status=640
1651 SubClassCode=1
1652 SubsystemID=0
1653 SubsystemVendorID=0
1654 VendorID=32902
1655 clk_domain=system.clk_domain
1656 config_latency=20000
1657 ctrl_offset=2
1658 disks=system.cf0
1659 eventq_index=0
1660 io_shift=1
1661 pci_bus=2
1662 pci_dev=7
1663 pci_func=0
1664 pio_latency=30000
1665 platform=system.realview
1666 system=system
1667 config=system.iobus.master[8]
1668 dma=system.iobus.slave[2]
1669 pio=system.iobus.master[7]
1670
1671 [system.realview.clcd]
1672 type=Pl111
1673 amba_id=1315089
1674 clk_domain=system.clk_domain
1675 enable_capture=true
1676 eventq_index=0
1677 gic=system.realview.gic
1678 int_num=55
1679 pio_addr=268566528
1680 pio_latency=10000
1681 pixel_clock=41667
1682 system=system
1683 vnc=system.vncserver
1684 dma=system.iobus.slave[1]
1685 pio=system.iobus.master[4]
1686
1687 [system.realview.dmac_fake]
1688 type=AmbaFake
1689 amba_id=0
1690 clk_domain=system.clk_domain
1691 eventq_index=0
1692 ignore_access=false
1693 pio_addr=268632064
1694 pio_latency=100000
1695 system=system
1696 pio=system.iobus.master[9]
1697
1698 [system.realview.flash_fake]
1699 type=IsaFake
1700 clk_domain=system.clk_domain
1701 eventq_index=0
1702 fake_mem=true
1703 pio_addr=1073741824
1704 pio_latency=100000
1705 pio_size=536870912
1706 ret_bad_addr=false
1707 ret_data16=65535
1708 ret_data32=4294967295
1709 ret_data64=18446744073709551615
1710 ret_data8=255
1711 system=system
1712 update_data=false
1713 warn_access=
1714 pio=system.iobus.master[24]
1715
1716 [system.realview.gic]
1717 type=Pl390
1718 clk_domain=system.clk_domain
1719 cpu_addr=520093952
1720 cpu_pio_delay=10000
1721 dist_addr=520097792
1722 dist_pio_delay=10000
1723 eventq_index=0
1724 int_latency=10000
1725 it_lines=128
1726 msix_addr=0
1727 platform=system.realview
1728 system=system
1729 pio=system.membus.master[2]
1730
1731 [system.realview.gpio0_fake]
1732 type=AmbaFake
1733 amba_id=0
1734 clk_domain=system.clk_domain
1735 eventq_index=0
1736 ignore_access=false
1737 pio_addr=268513280
1738 pio_latency=100000
1739 system=system
1740 pio=system.iobus.master[16]
1741
1742 [system.realview.gpio1_fake]
1743 type=AmbaFake
1744 amba_id=0
1745 clk_domain=system.clk_domain
1746 eventq_index=0
1747 ignore_access=false
1748 pio_addr=268517376
1749 pio_latency=100000
1750 system=system
1751 pio=system.iobus.master[17]
1752
1753 [system.realview.gpio2_fake]
1754 type=AmbaFake
1755 amba_id=0
1756 clk_domain=system.clk_domain
1757 eventq_index=0
1758 ignore_access=false
1759 pio_addr=268521472
1760 pio_latency=100000
1761 system=system
1762 pio=system.iobus.master[18]
1763
1764 [system.realview.kmi0]
1765 type=Pl050
1766 amba_id=1314896
1767 clk_domain=system.clk_domain
1768 eventq_index=0
1769 gic=system.realview.gic
1770 int_delay=1000000
1771 int_num=52
1772 is_mouse=false
1773 pio_addr=268460032
1774 pio_latency=100000
1775 system=system
1776 vnc=system.vncserver
1777 pio=system.iobus.master[5]
1778
1779 [system.realview.kmi1]
1780 type=Pl050
1781 amba_id=1314896
1782 clk_domain=system.clk_domain
1783 eventq_index=0
1784 gic=system.realview.gic
1785 int_delay=1000000
1786 int_num=53
1787 is_mouse=true
1788 pio_addr=268464128
1789 pio_latency=100000
1790 system=system
1791 vnc=system.vncserver
1792 pio=system.iobus.master[6]
1793
1794 [system.realview.l2x0_fake]
1795 type=IsaFake
1796 clk_domain=system.clk_domain
1797 eventq_index=0
1798 fake_mem=false
1799 pio_addr=520101888
1800 pio_latency=100000
1801 pio_size=4095
1802 ret_bad_addr=false
1803 ret_data16=65535
1804 ret_data32=4294967295
1805 ret_data64=18446744073709551615
1806 ret_data8=255
1807 system=system
1808 update_data=false
1809 warn_access=
1810 pio=system.membus.master[3]
1811
1812 [system.realview.local_cpu_timer]
1813 type=CpuLocalTimer
1814 clk_domain=system.clk_domain
1815 eventq_index=0
1816 gic=system.realview.gic
1817 int_num_timer=29
1818 int_num_watchdog=30
1819 pio_addr=520095232
1820 pio_latency=100000
1821 system=system
1822 pio=system.membus.master[5]
1823
1824 [system.realview.mmc_fake]
1825 type=AmbaFake
1826 amba_id=0
1827 clk_domain=system.clk_domain
1828 eventq_index=0
1829 ignore_access=false
1830 pio_addr=268455936
1831 pio_latency=100000
1832 system=system
1833 pio=system.iobus.master[22]
1834
1835 [system.realview.nvmem]
1836 type=SimpleMemory
1837 bandwidth=73.000000
1838 clk_domain=system.clk_domain
1839 conf_table_reported=false
1840 eventq_index=0
1841 in_addr_map=true
1842 latency=30000
1843 latency_var=0
1844 null=false
1845 range=2147483648:2214592511
1846 port=system.membus.master[1]
1847
1848 [system.realview.realview_io]
1849 type=RealViewCtrl
1850 clk_domain=system.clk_domain
1851 eventq_index=0
1852 idreg=0
1853 pio_addr=268435456
1854 pio_latency=100000
1855 proc_id0=201326592
1856 proc_id1=201327138
1857 system=system
1858 pio=system.iobus.master[1]
1859
1860 [system.realview.rtc]
1861 type=PL031
1862 amba_id=3412017
1863 clk_domain=system.clk_domain
1864 eventq_index=0
1865 gic=system.realview.gic
1866 int_delay=100000
1867 int_num=42
1868 pio_addr=268529664
1869 pio_latency=100000
1870 system=system
1871 time=Thu Jan  1 00:00:00 2009
1872 pio=system.iobus.master[23]
1873
1874 [system.realview.sci_fake]
1875 type=AmbaFake
1876 amba_id=0
1877 clk_domain=system.clk_domain
1878 eventq_index=0
1879 ignore_access=false
1880 pio_addr=268492800
1881 pio_latency=100000
1882 system=system
1883 pio=system.iobus.master[20]
1884
1885 [system.realview.smc_fake]
1886 type=AmbaFake
1887 amba_id=0
1888 clk_domain=system.clk_domain
1889 eventq_index=0
1890 ignore_access=false
1891 pio_addr=269357056
1892 pio_latency=100000
1893 system=system
1894 pio=system.iobus.master[13]
1895
1896 [system.realview.sp810_fake]
1897 type=AmbaFake
1898 amba_id=0
1899 clk_domain=system.clk_domain
1900 eventq_index=0
1901 ignore_access=true
1902 pio_addr=268439552
1903 pio_latency=100000
1904 system=system
1905 pio=system.iobus.master[14]
1906
1907 [system.realview.ssp_fake]
1908 type=AmbaFake
1909 amba_id=0
1910 clk_domain=system.clk_domain
1911 eventq_index=0
1912 ignore_access=false
1913 pio_addr=268488704
1914 pio_latency=100000
1915 system=system
1916 pio=system.iobus.master[19]
1917
1918 [system.realview.timer0]
1919 type=Sp804
1920 amba_id=1316868
1921 clk_domain=system.clk_domain
1922 clock0=1000000
1923 clock1=1000000
1924 eventq_index=0
1925 gic=system.realview.gic
1926 int_num0=36
1927 int_num1=36
1928 pio_addr=268505088
1929 pio_latency=100000
1930 system=system
1931 pio=system.iobus.master[2]
1932
1933 [system.realview.timer1]
1934 type=Sp804
1935 amba_id=1316868
1936 clk_domain=system.clk_domain
1937 clock0=1000000
1938 clock1=1000000
1939 eventq_index=0
1940 gic=system.realview.gic
1941 int_num0=37
1942 int_num1=37
1943 pio_addr=268509184
1944 pio_latency=100000
1945 system=system
1946 pio=system.iobus.master[3]
1947
1948 [system.realview.uart]
1949 type=Pl011
1950 clk_domain=system.clk_domain
1951 end_on_eot=false
1952 eventq_index=0
1953 gic=system.realview.gic
1954 int_delay=100000
1955 int_num=44
1956 pio_addr=268472320
1957 pio_latency=100000
1958 platform=system.realview
1959 system=system
1960 terminal=system.terminal
1961 pio=system.iobus.master[0]
1962
1963 [system.realview.uart1_fake]
1964 type=AmbaFake
1965 amba_id=0
1966 clk_domain=system.clk_domain
1967 eventq_index=0
1968 ignore_access=false
1969 pio_addr=268476416
1970 pio_latency=100000
1971 system=system
1972 pio=system.iobus.master[10]
1973
1974 [system.realview.uart2_fake]
1975 type=AmbaFake
1976 amba_id=0
1977 clk_domain=system.clk_domain
1978 eventq_index=0
1979 ignore_access=false
1980 pio_addr=268480512
1981 pio_latency=100000
1982 system=system
1983 pio=system.iobus.master[11]
1984
1985 [system.realview.uart3_fake]
1986 type=AmbaFake
1987 amba_id=0
1988 clk_domain=system.clk_domain
1989 eventq_index=0
1990 ignore_access=false
1991 pio_addr=268484608
1992 pio_latency=100000
1993 system=system
1994 pio=system.iobus.master[12]
1995
1996 [system.realview.watchdog_fake]
1997 type=AmbaFake
1998 amba_id=0
1999 clk_domain=system.clk_domain
2000 eventq_index=0
2001 ignore_access=false
2002 pio_addr=268500992
2003 pio_latency=100000
2004 system=system
2005 pio=system.iobus.master[15]
2006
2007 [system.terminal]
2008 type=Terminal
2009 eventq_index=0
2010 intr_control=system.intrctrl
2011 number=0
2012 output=true
2013 port=3456
2014
2015 [system.toL2Bus]
2016 type=CoherentBus
2017 clk_domain=system.cpu_clk_domain
2018 eventq_index=0
2019 header_cycles=1
2020 system=system
2021 use_default_range=false
2022 width=8
2023 master=system.l2c.cpu_side
2024 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
2025
2026 [system.vncserver]
2027 type=VncServer
2028 eventq_index=0
2029 frame_capture=false
2030 number=0
2031 port=5900
2032
2033 [system.voltage_domain]
2034 type=VoltageDomain
2035 eventq_index=0
2036 voltage=1.000000
2037