2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.846057 # Number of seconds simulated
4 sim_ticks 2846057099000 # Number of ticks simulated
5 final_tick 2846057099000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 157157 # Simulator instruction rate (inst/s)
8 host_op_rate 190318 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3507683540 # Simulator tick rate (ticks/s)
10 host_mem_usage 605024 # Number of bytes of host memory used
11 host_seconds 811.38 # Real time elapsed on the host
12 sim_insts 127513349 # Number of instructions simulated
13 sim_ops 154419501 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 1469184 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 1233972 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.l2cache.prefetcher 8227712 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.dtb.walker 2752 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.inst 383104 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.data 711064 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.l2cache.prefetcher 574528 # Number of bytes read from this memory
25 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26 system.physmem.bytes_read::total 12611084 # Number of bytes read from this memory
27 system.physmem.bytes_inst_read::cpu0.inst 1469184 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::cpu1.inst 383104 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::total 1852288 # Number of instructions bytes read from this memory
30 system.physmem.bytes_written::writebacks 8917568 # Number of bytes written to this memory
31 system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32 system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33 system.physmem.bytes_written::total 8935132 # Number of bytes written to this memory
34 system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.inst 22956 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.data 19804 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.l2cache.prefetcher 128558 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu1.dtb.walker 43 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu1.inst 5986 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.data 11132 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.l2cache.prefetcher 8977 # Number of read requests responded to by this memory
43 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44 system.physmem.num_reads::total 197593 # Number of read requests responded to by this memory
45 system.physmem.num_writes::writebacks 139337 # Number of write requests responded to by this memory
46 system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
47 system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
48 system.physmem.num_writes::total 143728 # Number of write requests responded to by this memory
49 system.physmem.bw_read::cpu0.dtb.walker 2721 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu0.inst 516217 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu0.data 433572 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.l2cache.prefetcher 2890916 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu1.dtb.walker 967 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu1.inst 134609 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu1.data 249842 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.l2cache.prefetcher 201868 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::total 4431072 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_inst_read::cpu0.inst 516217 # Instruction read bandwidth from this memory (bytes/s)
61 system.physmem.bw_inst_read::cpu1.inst 134609 # Instruction read bandwidth from this memory (bytes/s)
62 system.physmem.bw_inst_read::total 650826 # Instruction read bandwidth from this memory (bytes/s)
63 system.physmem.bw_write::writebacks 3133306 # Write bandwidth from this memory (bytes/s)
64 system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
65 system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::total 3139477 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_total::writebacks 3133306 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::cpu0.dtb.walker 2721 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu0.inst 516217 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu0.data 439730 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.l2cache.prefetcher 2890916 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu1.dtb.walker 967 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu1.inst 134609 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu1.data 249856 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu1.l2cache.prefetcher 201868 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::total 7570549 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.readReqs 197593 # Number of read requests accepted
80 system.physmem.writeReqs 143728 # Number of write requests accepted
81 system.physmem.readBursts 197593 # Number of DRAM read bursts, including those serviced by the write queue
82 system.physmem.writeBursts 143728 # Number of DRAM write bursts, including those merged in the write queue
83 system.physmem.bytesReadDRAM 12635520 # Total number of bytes read from DRAM
84 system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue
85 system.physmem.bytesWritten 8947648 # Total number of bytes written to DRAM
86 system.physmem.bytesReadSys 12611084 # Total read bytes from the system interface side
87 system.physmem.bytesWrittenSys 8935132 # Total written bytes from the system interface side
88 system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue
89 system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
90 system.physmem.neitherReadNorWriteReqs 51189 # Number of requests that are neither read nor write
91 system.physmem.perBankRdBursts::0 12157 # Per bank write bursts
92 system.physmem.perBankRdBursts::1 12292 # Per bank write bursts
93 system.physmem.perBankRdBursts::2 12950 # Per bank write bursts
94 system.physmem.perBankRdBursts::3 12405 # Per bank write bursts
95 system.physmem.perBankRdBursts::4 15321 # Per bank write bursts
96 system.physmem.perBankRdBursts::5 12434 # Per bank write bursts
97 system.physmem.perBankRdBursts::6 12677 # Per bank write bursts
98 system.physmem.perBankRdBursts::7 13084 # Per bank write bursts
99 system.physmem.perBankRdBursts::8 12267 # Per bank write bursts
100 system.physmem.perBankRdBursts::9 12426 # Per bank write bursts
101 system.physmem.perBankRdBursts::10 11655 # Per bank write bursts
102 system.physmem.perBankRdBursts::11 11073 # Per bank write bursts
103 system.physmem.perBankRdBursts::12 11997 # Per bank write bursts
104 system.physmem.perBankRdBursts::13 11769 # Per bank write bursts
105 system.physmem.perBankRdBursts::14 11320 # Per bank write bursts
106 system.physmem.perBankRdBursts::15 11603 # Per bank write bursts
107 system.physmem.perBankWrBursts::0 8631 # Per bank write bursts
108 system.physmem.perBankWrBursts::1 8804 # Per bank write bursts
109 system.physmem.perBankWrBursts::2 9518 # Per bank write bursts
110 system.physmem.perBankWrBursts::3 8865 # Per bank write bursts
111 system.physmem.perBankWrBursts::4 8658 # Per bank write bursts
112 system.physmem.perBankWrBursts::5 8780 # Per bank write bursts
113 system.physmem.perBankWrBursts::6 9135 # Per bank write bursts
114 system.physmem.perBankWrBursts::7 9275 # Per bank write bursts
115 system.physmem.perBankWrBursts::8 8996 # Per bank write bursts
116 system.physmem.perBankWrBursts::9 8951 # Per bank write bursts
117 system.physmem.perBankWrBursts::10 8409 # Per bank write bursts
118 system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
119 system.physmem.perBankWrBursts::12 8895 # Per bank write bursts
120 system.physmem.perBankWrBursts::13 8304 # Per bank write bursts
121 system.physmem.perBankWrBursts::14 8310 # Per bank write bursts
122 system.physmem.perBankWrBursts::15 8140 # Per bank write bursts
123 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124 system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
125 system.physmem.totGap 2846056522500 # Total gap between requests
126 system.physmem.readPktSize::0 0 # Read request sizes (log2)
127 system.physmem.readPktSize::1 0 # Read request sizes (log2)
128 system.physmem.readPktSize::2 555 # Read request sizes (log2)
129 system.physmem.readPktSize::3 28 # Read request sizes (log2)
130 system.physmem.readPktSize::4 0 # Read request sizes (log2)
131 system.physmem.readPktSize::5 0 # Read request sizes (log2)
132 system.physmem.readPktSize::6 197010 # Read request sizes (log2)
133 system.physmem.writePktSize::0 0 # Write request sizes (log2)
134 system.physmem.writePktSize::1 0 # Write request sizes (log2)
135 system.physmem.writePktSize::2 4391 # Write request sizes (log2)
136 system.physmem.writePktSize::3 0 # Write request sizes (log2)
137 system.physmem.writePktSize::4 0 # Write request sizes (log2)
138 system.physmem.writePktSize::5 0 # Write request sizes (log2)
139 system.physmem.writePktSize::6 139337 # Write request sizes (log2)
140 system.physmem.rdQLenPdf::0 84527 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::1 62953 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::2 11439 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::3 9638 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::4 7653 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::6 5113 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::7 4583 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::8 3751 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::9 746 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
172 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::15 2731 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::16 3213 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::17 4878 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::18 5520 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::19 6053 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::20 6627 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::21 7062 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::22 8465 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::23 8859 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::24 10175 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::25 9630 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::26 9702 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::27 8882 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::28 9201 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::29 10384 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::30 8548 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::31 7940 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::32 7665 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::34 283 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::41 200 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see
236 system.physmem.bytesPerActivate::samples 90385 # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::mean 238.790065 # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::gmean 135.540737 # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::stdev 300.321787 # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::0-127 48391 53.54% 53.54% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::128-255 17645 19.52% 73.06% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::256-383 6369 7.05% 80.11% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::384-511 3664 4.05% 84.16% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::512-639 2743 3.03% 87.20% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::640-767 1397 1.55% 88.74% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::768-895 884 0.98% 89.72% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::896-1023 1036 1.15% 90.87% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::1024-1151 8256 9.13% 100.00% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::total 90385 # Bytes accessed per row activation
250 system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes
251 system.physmem.rdPerTurnAround::mean 28.264567 # Reads before turning the bus around for writes
252 system.physmem.rdPerTurnAround::stdev 537.756673 # Reads before turning the bus around for writes
253 system.physmem.rdPerTurnAround::0-2047 6984 99.99% 99.99% # Reads before turning the bus around for writes
254 system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
255 system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes
256 system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::mean 20.015319 # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::gmean 18.579154 # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::stdev 12.029266 # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::16-19 5867 83.99% 83.99% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::20-23 359 5.14% 89.13% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::24-27 198 2.83% 91.97% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::28-31 50 0.72% 92.68% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::32-35 72 1.03% 93.72% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::36-39 159 2.28% 95.99% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::40-43 19 0.27% 96.26% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::44-47 12 0.17% 96.44% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::52-55 8 0.11% 96.71% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::56-59 6 0.09% 96.79% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::60-63 5 0.07% 96.86% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::64-67 162 2.32% 99.18% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::68-71 6 0.09% 99.27% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::72-75 6 0.09% 99.36% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::76-79 10 0.14% 99.50% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::80-83 1 0.01% 99.51% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::84-87 2 0.03% 99.54% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::88-91 2 0.03% 99.57% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::100-103 1 0.01% 99.61% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.64% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::128-131 14 0.20% 99.86% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::164-167 4 0.06% 99.96% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads
291 system.physmem.totQLat 5478181174 # Total ticks spent queuing
292 system.physmem.totMemAccLat 9179993674 # Total ticks spent from burst creation until serviced by the DRAM
293 system.physmem.totBusLat 987150000 # Total ticks spent in databus transfers
294 system.physmem.avgQLat 27747.46 # Average queueing delay per DRAM burst
295 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
296 system.physmem.avgMemAccLat 46497.46 # Average memory access latency per DRAM burst
297 system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s
298 system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
299 system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s
300 system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
301 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
302 system.physmem.busUtil 0.06 # Data bus utilization in percentage
303 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
304 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
305 system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
306 system.physmem.avgWrQLen 23.99 # Average write queue length when enqueuing
307 system.physmem.readRowHits 164056 # Number of row buffer hits during reads
308 system.physmem.writeRowHits 82794 # Number of row buffer hits during writes
309 system.physmem.readRowHitRate 83.10 # Row buffer hit rate for reads
310 system.physmem.writeRowHitRate 59.21 # Row buffer hit rate for writes
311 system.physmem.avgGap 8338357.51 # Average gap between requests
312 system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined
313 system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
314 system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
315 system.physmem_0.readEnergy 805888200 # Energy for read commands per rank (pJ)
316 system.physmem_0.writeEnergy 464395680 # Energy for write commands per rank (pJ)
317 system.physmem_0.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
318 system.physmem_0.actBackEnergy 83219414895 # Energy for active background per rank (pJ)
319 system.physmem_0.preBackEnergy 1634632736250 # Energy for precharge background per rank (pJ)
320 system.physmem_0.totalEnergy 1905564250425 # Total energy per rank (pJ)
321 system.physmem_0.averagePower 669.546132 # Core power per rank (mW)
322 system.physmem_0.memoryStateTime::IDLE 2719229075521 # Time in different power states
323 system.physmem_0.memoryStateTime::REF 95035980000 # Time in different power states
324 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
325 system.physmem_0.memoryStateTime::ACT 31791929979 # Time in different power states
326 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
327 system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ)
328 system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ)
329 system.physmem_1.readEnergy 734050200 # Energy for read commands per rank (pJ)
330 system.physmem_1.writeEnergy 441553680 # Energy for write commands per rank (pJ)
331 system.physmem_1.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
332 system.physmem_1.actBackEnergy 82136174355 # Energy for active background per rank (pJ)
333 system.physmem_1.preBackEnergy 1635582947250 # Energy for precharge background per rank (pJ)
334 system.physmem_1.totalEnergy 1905289812570 # Total energy per rank (pJ)
335 system.physmem_1.averagePower 669.449705 # Core power per rank (mW)
336 system.physmem_1.memoryStateTime::IDLE 2720812978493 # Time in different power states
337 system.physmem_1.memoryStateTime::REF 95035980000 # Time in different power states
338 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
339 system.physmem_1.memoryStateTime::ACT 30205644507 # Time in different power states
340 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
341 system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
342 system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
343 system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
344 system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
345 system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
346 system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
347 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
348 system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
349 system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
350 system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
351 system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
352 system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
353 system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
354 system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
355 system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
356 system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
357 system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
358 system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
359 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
360 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
361 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
362 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
363 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
364 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
365 system.cpu0.branchPred.lookups 19599196 # Number of BP lookups
366 system.cpu0.branchPred.condPredicted 12768904 # Number of conditional branches predicted
367 system.cpu0.branchPred.condIncorrect 991514 # Number of conditional branches incorrect
368 system.cpu0.branchPred.BTBLookups 12558764 # Number of BTB lookups
369 system.cpu0.branchPred.BTBHits 8839837 # Number of BTB hits
370 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
371 system.cpu0.branchPred.BTBHitPct 70.387795 # BTB Hit Percentage
372 system.cpu0.branchPred.usedRAS 3295346 # Number of times the RAS was used to get a target.
373 system.cpu0.branchPred.RASInCorrect 199810 # Number of incorrect RAS predictions.
374 system.cpu_clk_domain.clock 500 # Clock period in ticks
375 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
376 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
377 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
378 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
379 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
380 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
381 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
382 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
383 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
384 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
385 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
386 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
387 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
388 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
389 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
390 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
391 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
392 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
393 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
394 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
395 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
396 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
397 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
398 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
399 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
400 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
401 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
402 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
403 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
404 system.cpu0.dtb.walker.walks 67395 # Table walker walks requested
405 system.cpu0.dtb.walker.walksShort 67395 # Table walker walks initiated with short descriptors
406 system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44710 # Level at which table walker walks with short descriptors terminate
407 system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22685 # Level at which table walker walks with short descriptors terminate
408 system.cpu0.dtb.walker.walkWaitTime::samples 67395 # Table walker wait (enqueue to first request) latency
409 system.cpu0.dtb.walker.walkWaitTime::0 67395 100.00% 100.00% # Table walker wait (enqueue to first request) latency
410 system.cpu0.dtb.walker.walkWaitTime::total 67395 # Table walker wait (enqueue to first request) latency
411 system.cpu0.dtb.walker.walkCompletionTime::samples 6692 # Table walker service (enqueue to completion) latency
412 system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545 # Table walker service (enqueue to completion) latency
413 system.cpu0.dtb.walker.walkCompletionTime::gmean 9352.624092 # Table walker service (enqueue to completion) latency
414 system.cpu0.dtb.walker.walkCompletionTime::stdev 5969.180600 # Table walker service (enqueue to completion) latency
415 system.cpu0.dtb.walker.walkCompletionTime::0-16383 6501 97.15% 97.15% # Table walker service (enqueue to completion) latency
416 system.cpu0.dtb.walker.walkCompletionTime::16384-32767 173 2.59% 99.73% # Table walker service (enqueue to completion) latency
417 system.cpu0.dtb.walker.walkCompletionTime::32768-49151 11 0.16% 99.90% # Table walker service (enqueue to completion) latency
418 system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency
419 system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
420 system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
421 system.cpu0.dtb.walker.walkCompletionTime::total 6692 # Table walker service (enqueue to completion) latency
422 system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution
423 system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution
424 system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution
425 system.cpu0.dtb.walker.walkPageSizes::4K 5137 76.76% 76.76% # Table walker page sizes translated
426 system.cpu0.dtb.walker.walkPageSizes::1M 1555 23.24% 100.00% # Table walker page sizes translated
427 system.cpu0.dtb.walker.walkPageSizes::total 6692 # Table walker page sizes translated
428 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67395 # Table walker requests started/completed, data/inst
429 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
430 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67395 # Table walker requests started/completed, data/inst
431 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6692 # Table walker requests started/completed, data/inst
432 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
433 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6692 # Table walker requests started/completed, data/inst
434 system.cpu0.dtb.walker.walkRequestOrigin::total 74087 # Table walker requests started/completed, data/inst
435 system.cpu0.dtb.inst_hits 0 # ITB inst hits
436 system.cpu0.dtb.inst_misses 0 # ITB inst misses
437 system.cpu0.dtb.read_hits 16492967 # DTB read hits
438 system.cpu0.dtb.read_misses 61485 # DTB read misses
439 system.cpu0.dtb.write_hits 13879033 # DTB write hits
440 system.cpu0.dtb.write_misses 5910 # DTB write misses
441 system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
442 system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
443 system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
444 system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
445 system.cpu0.dtb.flush_entries 3512 # Number of entries that have been flushed from TLB
446 system.cpu0.dtb.align_faults 1104 # Number of TLB faults due to alignment restrictions
447 system.cpu0.dtb.prefetch_faults 1584 # Number of TLB faults due to prefetch
448 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
449 system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
450 system.cpu0.dtb.read_accesses 16554452 # DTB read accesses
451 system.cpu0.dtb.write_accesses 13884943 # DTB write accesses
452 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
453 system.cpu0.dtb.hits 30372000 # DTB hits
454 system.cpu0.dtb.misses 67395 # DTB misses
455 system.cpu0.dtb.accesses 30439395 # DTB accesses
456 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
457 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
458 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
459 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
460 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
461 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
462 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
463 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
464 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
465 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
466 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
467 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
468 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
469 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
470 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
471 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
472 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
473 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
474 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
475 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
476 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
477 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
478 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
479 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
480 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
481 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
482 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
483 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
484 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
485 system.cpu0.itb.walker.walks 3867 # Table walker walks requested
486 system.cpu0.itb.walker.walksShort 3867 # Table walker walks initiated with short descriptors
487 system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
488 system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate
489 system.cpu0.itb.walker.walkWaitTime::samples 3867 # Table walker wait (enqueue to first request) latency
490 system.cpu0.itb.walker.walkWaitTime::0 3867 100.00% 100.00% # Table walker wait (enqueue to first request) latency
491 system.cpu0.itb.walker.walkWaitTime::total 3867 # Table walker wait (enqueue to first request) latency
492 system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency
493 system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524 # Table walker service (enqueue to completion) latency
494 system.cpu0.itb.walker.walkCompletionTime::gmean 9615.276250 # Table walker service (enqueue to completion) latency
495 system.cpu0.itb.walker.walkCompletionTime::stdev 7885.681727 # Table walker service (enqueue to completion) latency
496 system.cpu0.itb.walker.walkCompletionTime::0-32767 2419 99.92% 99.92% # Table walker service (enqueue to completion) latency
497 system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
498 system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
499 system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency
500 system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution
501 system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution
502 system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution
503 system.cpu0.itb.walker.walkPageSizes::4K 2121 87.61% 87.61% # Table walker page sizes translated
504 system.cpu0.itb.walker.walkPageSizes::1M 300 12.39% 100.00% # Table walker page sizes translated
505 system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated
506 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
507 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3867 # Table walker requests started/completed, data/inst
508 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3867 # Table walker requests started/completed, data/inst
509 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
510 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst
511 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst
512 system.cpu0.itb.walker.walkRequestOrigin::total 6288 # Table walker requests started/completed, data/inst
513 system.cpu0.itb.inst_hits 36759532 # ITB inst hits
514 system.cpu0.itb.inst_misses 3867 # ITB inst misses
515 system.cpu0.itb.read_hits 0 # DTB read hits
516 system.cpu0.itb.read_misses 0 # DTB read misses
517 system.cpu0.itb.write_hits 0 # DTB write hits
518 system.cpu0.itb.write_misses 0 # DTB write misses
519 system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
520 system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
521 system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
522 system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
523 system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB
524 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
525 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
526 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
527 system.cpu0.itb.perms_faults 7295 # Number of TLB faults due to permissions restrictions
528 system.cpu0.itb.read_accesses 0 # DTB read accesses
529 system.cpu0.itb.write_accesses 0 # DTB write accesses
530 system.cpu0.itb.inst_accesses 36763399 # ITB inst accesses
531 system.cpu0.itb.hits 36759532 # DTB hits
532 system.cpu0.itb.misses 3867 # DTB misses
533 system.cpu0.itb.accesses 36763399 # DTB accesses
534 system.cpu0.numCycles 154883476 # number of cpu cycles simulated
535 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
536 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
537 system.cpu0.committedInsts 75627253 # Number of instructions committed
538 system.cpu0.committedOps 91033342 # Number of ops (including micro ops) committed
539 system.cpu0.discardedOps 4957970 # Number of ops (including micro ops) which were discarded before commit
540 system.cpu0.numFetchSuspends 2062 # Number of times Execute suspended instruction fetching
541 system.cpu0.quiesceCycles 5537267530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
542 system.cpu0.cpi 2.047985 # CPI: cycles per instruction
543 system.cpu0.ipc 0.488285 # IPC: instructions per cycle
544 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
545 system.cpu0.kern.inst.quiesce 2064 # number of quiesce instructions executed
546 system.cpu0.tickCycles 121009607 # Number of cycles that the object actually ticked
547 system.cpu0.idleCycles 33873869 # Total number of cycles that the object has spent stopped
548 system.cpu0.dcache.tags.replacements 680149 # number of replacements
549 system.cpu0.dcache.tags.tagsinuse 489.017964 # Cycle average of tags in use
550 system.cpu0.dcache.tags.total_refs 28930962 # Total number of references to valid blocks.
551 system.cpu0.dcache.tags.sampled_refs 680661 # Sample count of references to valid blocks.
552 system.cpu0.dcache.tags.avg_refs 42.504216 # Average number of references to valid blocks.
553 system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit.
554 system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.017964 # Average occupied blocks per requestor
555 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.955113 # Average percentage of cache occupancy
556 system.cpu0.dcache.tags.occ_percent::total 0.955113 # Average percentage of cache occupancy
557 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
558 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
559 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
560 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
561 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
562 system.cpu0.dcache.tags.tag_accesses 60723709 # Number of tag accesses
563 system.cpu0.dcache.tags.data_accesses 60723709 # Number of data accesses
564 system.cpu0.dcache.ReadReq_hits::cpu0.data 15008806 # number of ReadReq hits
565 system.cpu0.dcache.ReadReq_hits::total 15008806 # number of ReadReq hits
566 system.cpu0.dcache.WriteReq_hits::cpu0.data 12795540 # number of WriteReq hits
567 system.cpu0.dcache.WriteReq_hits::total 12795540 # number of WriteReq hits
568 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306691 # number of SoftPFReq hits
569 system.cpu0.dcache.SoftPFReq_hits::total 306691 # number of SoftPFReq hits
570 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356713 # number of LoadLockedReq hits
571 system.cpu0.dcache.LoadLockedReq_hits::total 356713 # number of LoadLockedReq hits
572 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352309 # number of StoreCondReq hits
573 system.cpu0.dcache.StoreCondReq_hits::total 352309 # number of StoreCondReq hits
574 system.cpu0.dcache.demand_hits::cpu0.data 27804346 # number of demand (read+write) hits
575 system.cpu0.dcache.demand_hits::total 27804346 # number of demand (read+write) hits
576 system.cpu0.dcache.overall_hits::cpu0.data 28111037 # number of overall hits
577 system.cpu0.dcache.overall_hits::total 28111037 # number of overall hits
578 system.cpu0.dcache.ReadReq_misses::cpu0.data 442745 # number of ReadReq misses
579 system.cpu0.dcache.ReadReq_misses::total 442745 # number of ReadReq misses
580 system.cpu0.dcache.WriteReq_misses::cpu0.data 557072 # number of WriteReq misses
581 system.cpu0.dcache.WriteReq_misses::total 557072 # number of WriteReq misses
582 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131875 # number of SoftPFReq misses
583 system.cpu0.dcache.SoftPFReq_misses::total 131875 # number of SoftPFReq misses
584 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21262 # number of LoadLockedReq misses
585 system.cpu0.dcache.LoadLockedReq_misses::total 21262 # number of LoadLockedReq misses
586 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21236 # number of StoreCondReq misses
587 system.cpu0.dcache.StoreCondReq_misses::total 21236 # number of StoreCondReq misses
588 system.cpu0.dcache.demand_misses::cpu0.data 999817 # number of demand (read+write) misses
589 system.cpu0.dcache.demand_misses::total 999817 # number of demand (read+write) misses
590 system.cpu0.dcache.overall_misses::cpu0.data 1131692 # number of overall misses
591 system.cpu0.dcache.overall_misses::total 1131692 # number of overall misses
592 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845429500 # number of ReadReq miss cycles
593 system.cpu0.dcache.ReadReq_miss_latency::total 5845429500 # number of ReadReq miss cycles
594 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8925410000 # number of WriteReq miss cycles
595 system.cpu0.dcache.WriteReq_miss_latency::total 8925410000 # number of WriteReq miss cycles
596 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323710500 # number of LoadLockedReq miss cycles
597 system.cpu0.dcache.LoadLockedReq_miss_latency::total 323710500 # number of LoadLockedReq miss cycles
598 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479970000 # number of StoreCondReq miss cycles
599 system.cpu0.dcache.StoreCondReq_miss_latency::total 479970000 # number of StoreCondReq miss cycles
600 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 445000 # number of StoreCondFailReq miss cycles
601 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 445000 # number of StoreCondFailReq miss cycles
602 system.cpu0.dcache.demand_miss_latency::cpu0.data 14770839500 # number of demand (read+write) miss cycles
603 system.cpu0.dcache.demand_miss_latency::total 14770839500 # number of demand (read+write) miss cycles
604 system.cpu0.dcache.overall_miss_latency::cpu0.data 14770839500 # number of overall miss cycles
605 system.cpu0.dcache.overall_miss_latency::total 14770839500 # number of overall miss cycles
606 system.cpu0.dcache.ReadReq_accesses::cpu0.data 15451551 # number of ReadReq accesses(hits+misses)
607 system.cpu0.dcache.ReadReq_accesses::total 15451551 # number of ReadReq accesses(hits+misses)
608 system.cpu0.dcache.WriteReq_accesses::cpu0.data 13352612 # number of WriteReq accesses(hits+misses)
609 system.cpu0.dcache.WriteReq_accesses::total 13352612 # number of WriteReq accesses(hits+misses)
610 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438566 # number of SoftPFReq accesses(hits+misses)
611 system.cpu0.dcache.SoftPFReq_accesses::total 438566 # number of SoftPFReq accesses(hits+misses)
612 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377975 # number of LoadLockedReq accesses(hits+misses)
613 system.cpu0.dcache.LoadLockedReq_accesses::total 377975 # number of LoadLockedReq accesses(hits+misses)
614 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373545 # number of StoreCondReq accesses(hits+misses)
615 system.cpu0.dcache.StoreCondReq_accesses::total 373545 # number of StoreCondReq accesses(hits+misses)
616 system.cpu0.dcache.demand_accesses::cpu0.data 28804163 # number of demand (read+write) accesses
617 system.cpu0.dcache.demand_accesses::total 28804163 # number of demand (read+write) accesses
618 system.cpu0.dcache.overall_accesses::cpu0.data 29242729 # number of overall (read+write) accesses
619 system.cpu0.dcache.overall_accesses::total 29242729 # number of overall (read+write) accesses
620 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028654 # miss rate for ReadReq accesses
621 system.cpu0.dcache.ReadReq_miss_rate::total 0.028654 # miss rate for ReadReq accesses
622 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041720 # miss rate for WriteReq accesses
623 system.cpu0.dcache.WriteReq_miss_rate::total 0.041720 # miss rate for WriteReq accesses
624 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300696 # miss rate for SoftPFReq accesses
625 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300696 # miss rate for SoftPFReq accesses
626 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056252 # miss rate for LoadLockedReq accesses
627 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056252 # miss rate for LoadLockedReq accesses
628 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056850 # miss rate for StoreCondReq accesses
629 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056850 # miss rate for StoreCondReq accesses
630 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034711 # miss rate for demand accesses
631 system.cpu0.dcache.demand_miss_rate::total 0.034711 # miss rate for demand accesses
632 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038700 # miss rate for overall accesses
633 system.cpu0.dcache.overall_miss_rate::total 0.038700 # miss rate for overall accesses
634 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200 # average ReadReq miss latency
635 system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200 # average ReadReq miss latency
636 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337 # average WriteReq miss latency
637 system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337 # average WriteReq miss latency
638 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739 # average LoadLockedReq miss latency
639 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739 # average LoadLockedReq miss latency
640 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070 # average StoreCondReq miss latency
641 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070 # average StoreCondReq miss latency
642 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
643 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
644 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058 # average overall miss latency
645 system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058 # average overall miss latency
646 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038 # average overall miss latency
647 system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038 # average overall miss latency
648 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
649 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
650 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
651 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
652 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
653 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
655 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
656 system.cpu0.dcache.writebacks::writebacks 493052 # number of writebacks
657 system.cpu0.dcache.writebacks::total 493052 # number of writebacks
658 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69962 # number of ReadReq MSHR hits
659 system.cpu0.dcache.ReadReq_mshr_hits::total 69962 # number of ReadReq MSHR hits
660 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244118 # number of WriteReq MSHR hits
661 system.cpu0.dcache.WriteReq_mshr_hits::total 244118 # number of WriteReq MSHR hits
662 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15072 # number of LoadLockedReq MSHR hits
663 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15072 # number of LoadLockedReq MSHR hits
664 system.cpu0.dcache.demand_mshr_hits::cpu0.data 314080 # number of demand (read+write) MSHR hits
665 system.cpu0.dcache.demand_mshr_hits::total 314080 # number of demand (read+write) MSHR hits
666 system.cpu0.dcache.overall_mshr_hits::cpu0.data 314080 # number of overall MSHR hits
667 system.cpu0.dcache.overall_mshr_hits::total 314080 # number of overall MSHR hits
668 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372783 # number of ReadReq MSHR misses
669 system.cpu0.dcache.ReadReq_mshr_misses::total 372783 # number of ReadReq MSHR misses
670 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312954 # number of WriteReq MSHR misses
671 system.cpu0.dcache.WriteReq_mshr_misses::total 312954 # number of WriteReq MSHR misses
672 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99314 # number of SoftPFReq MSHR misses
673 system.cpu0.dcache.SoftPFReq_mshr_misses::total 99314 # number of SoftPFReq MSHR misses
674 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6190 # number of LoadLockedReq MSHR misses
675 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6190 # number of LoadLockedReq MSHR misses
676 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21236 # number of StoreCondReq MSHR misses
677 system.cpu0.dcache.StoreCondReq_mshr_misses::total 21236 # number of StoreCondReq MSHR misses
678 system.cpu0.dcache.demand_mshr_misses::cpu0.data 685737 # number of demand (read+write) MSHR misses
679 system.cpu0.dcache.demand_mshr_misses::total 685737 # number of demand (read+write) MSHR misses
680 system.cpu0.dcache.overall_mshr_misses::cpu0.data 785051 # number of overall MSHR misses
681 system.cpu0.dcache.overall_mshr_misses::total 785051 # number of overall MSHR misses
682 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
683 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18001 # number of ReadReq MSHR uncacheable
684 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
685 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
686 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
687 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34757 # number of overall MSHR uncacheable misses
688 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4391149500 # number of ReadReq MSHR miss cycles
689 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4391149500 # number of ReadReq MSHR miss cycles
690 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4970740000 # number of WriteReq MSHR miss cycles
691 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4970740000 # number of WriteReq MSHR miss cycles
692 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1612906500 # number of SoftPFReq MSHR miss cycles
693 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1612906500 # number of SoftPFReq MSHR miss cycles
694 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94756000 # number of LoadLockedReq MSHR miss cycles
695 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94756000 # number of LoadLockedReq MSHR miss cycles
696 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458745000 # number of StoreCondReq MSHR miss cycles
697 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458745000 # number of StoreCondReq MSHR miss cycles
698 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 434000 # number of StoreCondFailReq MSHR miss cycles
699 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 434000 # number of StoreCondFailReq MSHR miss cycles
700 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9361889500 # number of demand (read+write) MSHR miss cycles
701 system.cpu0.dcache.demand_mshr_miss_latency::total 9361889500 # number of demand (read+write) MSHR miss cycles
702 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974796000 # number of overall MSHR miss cycles
703 system.cpu0.dcache.overall_mshr_miss_latency::total 10974796000 # number of overall MSHR miss cycles
704 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751362500 # number of ReadReq MSHR uncacheable cycles
705 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751362500 # number of ReadReq MSHR uncacheable cycles
706 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725552500 # number of WriteReq MSHR uncacheable cycles
707 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725552500 # number of WriteReq MSHR uncacheable cycles
708 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6476915000 # number of overall MSHR uncacheable cycles
709 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6476915000 # number of overall MSHR uncacheable cycles
710 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024126 # mshr miss rate for ReadReq accesses
711 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024126 # mshr miss rate for ReadReq accesses
712 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023438 # mshr miss rate for WriteReq accesses
713 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023438 # mshr miss rate for WriteReq accesses
714 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226452 # mshr miss rate for SoftPFReq accesses
715 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226452 # mshr miss rate for SoftPFReq accesses
716 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016377 # mshr miss rate for LoadLockedReq accesses
717 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016377 # mshr miss rate for LoadLockedReq accesses
718 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056850 # mshr miss rate for StoreCondReq accesses
719 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056850 # mshr miss rate for StoreCondReq accesses
720 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023807 # mshr miss rate for demand accesses
721 system.cpu0.dcache.demand_mshr_miss_rate::total 0.023807 # mshr miss rate for demand accesses
722 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026846 # mshr miss rate for overall accesses
723 system.cpu0.dcache.overall_mshr_miss_rate::total 0.026846 # mshr miss rate for overall accesses
724 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645 # average ReadReq mshr miss latency
725 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645 # average ReadReq mshr miss latency
726 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752 # average WriteReq mshr miss latency
727 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752 # average WriteReq mshr miss latency
728 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656 # average SoftPFReq mshr miss latency
729 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656 # average SoftPFReq mshr miss latency
730 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994 # average LoadLockedReq mshr miss latency
731 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994 # average LoadLockedReq mshr miss latency
732 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059 # average StoreCondReq mshr miss latency
733 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059 # average StoreCondReq mshr miss latency
734 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
735 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
736 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288 # average overall mshr miss latency
737 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288 # average overall mshr miss latency
738 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610 # average overall mshr miss latency
739 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610 # average overall mshr miss latency
740 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142 # average ReadReq mshr uncacheable latency
741 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142 # average ReadReq mshr uncacheable latency
742 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510 # average WriteReq mshr uncacheable latency
743 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510 # average WriteReq mshr uncacheable latency
744 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337 # average overall mshr uncacheable latency
745 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337 # average overall mshr uncacheable latency
746 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
747 system.cpu0.icache.tags.replacements 1879741 # number of replacements
748 system.cpu0.icache.tags.tagsinuse 511.785261 # Cycle average of tags in use
749 system.cpu0.icache.tags.total_refs 34871642 # Total number of references to valid blocks.
750 system.cpu0.icache.tags.sampled_refs 1880253 # Sample count of references to valid blocks.
751 system.cpu0.icache.tags.avg_refs 18.546250 # Average number of references to valid blocks.
752 system.cpu0.icache.tags.warmup_cycle 6165545000 # Cycle when the warmup percentage was hit.
753 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785261 # Average occupied blocks per requestor
754 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999581 # Average percentage of cache occupancy
755 system.cpu0.icache.tags.occ_percent::total 0.999581 # Average percentage of cache occupancy
756 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
757 system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
758 system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
759 system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
760 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
761 system.cpu0.icache.tags.tag_accesses 75384087 # Number of tag accesses
762 system.cpu0.icache.tags.data_accesses 75384087 # Number of data accesses
763 system.cpu0.icache.ReadReq_hits::cpu0.inst 34871642 # number of ReadReq hits
764 system.cpu0.icache.ReadReq_hits::total 34871642 # number of ReadReq hits
765 system.cpu0.icache.demand_hits::cpu0.inst 34871642 # number of demand (read+write) hits
766 system.cpu0.icache.demand_hits::total 34871642 # number of demand (read+write) hits
767 system.cpu0.icache.overall_hits::cpu0.inst 34871642 # number of overall hits
768 system.cpu0.icache.overall_hits::total 34871642 # number of overall hits
769 system.cpu0.icache.ReadReq_misses::cpu0.inst 1880268 # number of ReadReq misses
770 system.cpu0.icache.ReadReq_misses::total 1880268 # number of ReadReq misses
771 system.cpu0.icache.demand_misses::cpu0.inst 1880268 # number of demand (read+write) misses
772 system.cpu0.icache.demand_misses::total 1880268 # number of demand (read+write) misses
773 system.cpu0.icache.overall_misses::cpu0.inst 1880268 # number of overall misses
774 system.cpu0.icache.overall_misses::total 1880268 # number of overall misses
775 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494991000 # number of ReadReq miss cycles
776 system.cpu0.icache.ReadReq_miss_latency::total 17494991000 # number of ReadReq miss cycles
777 system.cpu0.icache.demand_miss_latency::cpu0.inst 17494991000 # number of demand (read+write) miss cycles
778 system.cpu0.icache.demand_miss_latency::total 17494991000 # number of demand (read+write) miss cycles
779 system.cpu0.icache.overall_miss_latency::cpu0.inst 17494991000 # number of overall miss cycles
780 system.cpu0.icache.overall_miss_latency::total 17494991000 # number of overall miss cycles
781 system.cpu0.icache.ReadReq_accesses::cpu0.inst 36751910 # number of ReadReq accesses(hits+misses)
782 system.cpu0.icache.ReadReq_accesses::total 36751910 # number of ReadReq accesses(hits+misses)
783 system.cpu0.icache.demand_accesses::cpu0.inst 36751910 # number of demand (read+write) accesses
784 system.cpu0.icache.demand_accesses::total 36751910 # number of demand (read+write) accesses
785 system.cpu0.icache.overall_accesses::cpu0.inst 36751910 # number of overall (read+write) accesses
786 system.cpu0.icache.overall_accesses::total 36751910 # number of overall (read+write) accesses
787 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051161 # miss rate for ReadReq accesses
788 system.cpu0.icache.ReadReq_miss_rate::total 0.051161 # miss rate for ReadReq accesses
789 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051161 # miss rate for demand accesses
790 system.cpu0.icache.demand_miss_rate::total 0.051161 # miss rate for demand accesses
791 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051161 # miss rate for overall accesses
792 system.cpu0.icache.overall_miss_rate::total 0.051161 # miss rate for overall accesses
793 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9304.519888 # average ReadReq miss latency
794 system.cpu0.icache.ReadReq_avg_miss_latency::total 9304.519888 # average ReadReq miss latency
795 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
796 system.cpu0.icache.demand_avg_miss_latency::total 9304.519888 # average overall miss latency
797 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
798 system.cpu0.icache.overall_avg_miss_latency::total 9304.519888 # average overall miss latency
799 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
800 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
801 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
802 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
803 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
804 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
805 system.cpu0.icache.fast_writes 0 # number of fast writes performed
806 system.cpu0.icache.cache_copies 0 # number of cache copies performed
807 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1880268 # number of ReadReq MSHR misses
808 system.cpu0.icache.ReadReq_mshr_misses::total 1880268 # number of ReadReq MSHR misses
809 system.cpu0.icache.demand_mshr_misses::cpu0.inst 1880268 # number of demand (read+write) MSHR misses
810 system.cpu0.icache.demand_mshr_misses::total 1880268 # number of demand (read+write) MSHR misses
811 system.cpu0.icache.overall_mshr_misses::cpu0.inst 1880268 # number of overall MSHR misses
812 system.cpu0.icache.overall_mshr_misses::total 1880268 # number of overall MSHR misses
813 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
814 system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable
815 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
816 system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses
817 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554857500 # number of ReadReq MSHR miss cycles
818 system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554857500 # number of ReadReq MSHR miss cycles
819 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554857500 # number of demand (read+write) MSHR miss cycles
820 system.cpu0.icache.demand_mshr_miss_latency::total 16554857500 # number of demand (read+write) MSHR miss cycles
821 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554857500 # number of overall MSHR miss cycles
822 system.cpu0.icache.overall_mshr_miss_latency::total 16554857500 # number of overall MSHR miss cycles
823 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles
824 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles
825 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles
826 system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles
827 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for ReadReq accesses
828 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051161 # mshr miss rate for ReadReq accesses
829 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for demand accesses
830 system.cpu0.icache.demand_mshr_miss_rate::total 0.051161 # mshr miss rate for demand accesses
831 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for overall accesses
832 system.cpu0.icache.overall_mshr_miss_rate::total 0.051161 # mshr miss rate for overall accesses
833 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average ReadReq mshr miss latency
834 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8804.520154 # average ReadReq mshr miss latency
835 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
836 system.cpu0.icache.demand_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
837 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
838 system.cpu0.icache.overall_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
839 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency
840 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency
841 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency
842 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency
843 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
844 system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762988 # number of hwpf issued
845 system.cpu0.l2cache.prefetcher.pfIdentified 1763146 # number of prefetch candidates identified
846 system.cpu0.l2cache.prefetcher.pfBufferHit 137 # number of redundant prefetches already in prefetch queue
847 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
848 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
849 system.cpu0.l2cache.prefetcher.pfSpanPage 223158 # number of prefetches not generated due to page crossing
850 system.cpu0.l2cache.tags.replacements 285163 # number of replacements
851 system.cpu0.l2cache.tags.tagsinuse 16064.441291 # Cycle average of tags in use
852 system.cpu0.l2cache.tags.total_refs 4801094 # Total number of references to valid blocks.
853 system.cpu0.l2cache.tags.sampled_refs 301400 # Sample count of references to valid blocks.
854 system.cpu0.l2cache.tags.avg_refs 15.929310 # Average number of references to valid blocks.
855 system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
856 system.cpu0.l2cache.tags.occ_blocks::writebacks 8613.892017 # Average occupied blocks per requestor
857 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.679204 # Average occupied blocks per requestor
858 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.072727 # Average occupied blocks per requestor
859 system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4663.239886 # Average occupied blocks per requestor
860 system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1620.721287 # Average occupied blocks per requestor
861 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1120.836170 # Average occupied blocks per requestor
862 system.cpu0.l2cache.tags.occ_percent::writebacks 0.525750 # Average percentage of cache occupancy
863 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002788 # Average percentage of cache occupancy
864 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
865 system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284622 # Average percentage of cache occupancy
866 system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098921 # Average percentage of cache occupancy
867 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068410 # Average percentage of cache occupancy
868 system.cpu0.l2cache.tags.occ_percent::total 0.980496 # Average percentage of cache occupancy
869 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id
870 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
871 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15199 # Occupied blocks per task id
872 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
873 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 305 # Occupied blocks per task id
874 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id
875 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 310 # Occupied blocks per task id
876 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
877 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
878 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
879 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
880 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
881 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4239 # Occupied blocks per task id
882 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7941 # Occupied blocks per task id
883 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2698 # Occupied blocks per task id
884 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id
885 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
886 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927673 # Percentage of cache occupancy per task id
887 system.cpu0.l2cache.tags.tag_accesses 85389688 # Number of tag accesses
888 system.cpu0.l2cache.tags.data_accesses 85389688 # Number of data accesses
889 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78899 # number of ReadReq hits
890 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4233 # number of ReadReq hits
891 system.cpu0.l2cache.ReadReq_hits::total 83132 # number of ReadReq hits
892 system.cpu0.l2cache.Writeback_hits::writebacks 493050 # number of Writeback hits
893 system.cpu0.l2cache.Writeback_hits::total 493050 # number of Writeback hits
894 system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28200 # number of UpgradeReq hits
895 system.cpu0.l2cache.UpgradeReq_hits::total 28200 # number of UpgradeReq hits
896 system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1701 # number of SCUpgradeReq hits
897 system.cpu0.l2cache.SCUpgradeReq_hits::total 1701 # number of SCUpgradeReq hits
898 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212815 # number of ReadExReq hits
899 system.cpu0.l2cache.ReadExReq_hits::total 212815 # number of ReadExReq hits
900 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1816263 # number of ReadCleanReq hits
901 system.cpu0.l2cache.ReadCleanReq_hits::total 1816263 # number of ReadCleanReq hits
902 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377267 # number of ReadSharedReq hits
903 system.cpu0.l2cache.ReadSharedReq_hits::total 377267 # number of ReadSharedReq hits
904 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78899 # number of demand (read+write) hits
905 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4233 # number of demand (read+write) hits
906 system.cpu0.l2cache.demand_hits::cpu0.inst 1816263 # number of demand (read+write) hits
907 system.cpu0.l2cache.demand_hits::cpu0.data 590082 # number of demand (read+write) hits
908 system.cpu0.l2cache.demand_hits::total 2489477 # number of demand (read+write) hits
909 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78899 # number of overall hits
910 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4233 # number of overall hits
911 system.cpu0.l2cache.overall_hits::cpu0.inst 1816263 # number of overall hits
912 system.cpu0.l2cache.overall_hits::cpu0.data 590082 # number of overall hits
913 system.cpu0.l2cache.overall_hits::total 2489477 # number of overall hits
914 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 767 # number of ReadReq misses
915 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 105 # number of ReadReq misses
916 system.cpu0.l2cache.ReadReq_misses::total 872 # number of ReadReq misses
917 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27843 # number of UpgradeReq misses
918 system.cpu0.l2cache.UpgradeReq_misses::total 27843 # number of UpgradeReq misses
919 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19534 # number of SCUpgradeReq misses
920 system.cpu0.l2cache.SCUpgradeReq_misses::total 19534 # number of SCUpgradeReq misses
921 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
922 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
923 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44100 # number of ReadExReq misses
924 system.cpu0.l2cache.ReadExReq_misses::total 44100 # number of ReadExReq misses
925 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64005 # number of ReadCleanReq misses
926 system.cpu0.l2cache.ReadCleanReq_misses::total 64005 # number of ReadCleanReq misses
927 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101018 # number of ReadSharedReq misses
928 system.cpu0.l2cache.ReadSharedReq_misses::total 101018 # number of ReadSharedReq misses
929 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 767 # number of demand (read+write) misses
930 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 105 # number of demand (read+write) misses
931 system.cpu0.l2cache.demand_misses::cpu0.inst 64005 # number of demand (read+write) misses
932 system.cpu0.l2cache.demand_misses::cpu0.data 145118 # number of demand (read+write) misses
933 system.cpu0.l2cache.demand_misses::total 209995 # number of demand (read+write) misses
934 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 767 # number of overall misses
935 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 105 # number of overall misses
936 system.cpu0.l2cache.overall_misses::cpu0.inst 64005 # number of overall misses
937 system.cpu0.l2cache.overall_misses::cpu0.data 145118 # number of overall misses
938 system.cpu0.l2cache.overall_misses::total 209995 # number of overall misses
939 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 26175500 # number of ReadReq miss cycles
940 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2558000 # number of ReadReq miss cycles
941 system.cpu0.l2cache.ReadReq_miss_latency::total 28733500 # number of ReadReq miss cycles
942 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 514961000 # number of UpgradeReq miss cycles
943 system.cpu0.l2cache.UpgradeReq_miss_latency::total 514961000 # number of UpgradeReq miss cycles
944 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395123500 # number of SCUpgradeReq miss cycles
945 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395123500 # number of SCUpgradeReq miss cycles
946 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 417500 # number of SCUpgradeFailReq miss cycles
947 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 417500 # number of SCUpgradeFailReq miss cycles
948 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2206381000 # number of ReadExReq miss cycles
949 system.cpu0.l2cache.ReadExReq_miss_latency::total 2206381000 # number of ReadExReq miss cycles
950 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2858183000 # number of ReadCleanReq miss cycles
951 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2858183000 # number of ReadCleanReq miss cycles
952 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2907472497 # number of ReadSharedReq miss cycles
953 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2907472497 # number of ReadSharedReq miss cycles
954 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 26175500 # number of demand (read+write) miss cycles
955 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2558000 # number of demand (read+write) miss cycles
956 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2858183000 # number of demand (read+write) miss cycles
957 system.cpu0.l2cache.demand_miss_latency::cpu0.data 5113853497 # number of demand (read+write) miss cycles
958 system.cpu0.l2cache.demand_miss_latency::total 8000769997 # number of demand (read+write) miss cycles
959 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 26175500 # number of overall miss cycles
960 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2558000 # number of overall miss cycles
961 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2858183000 # number of overall miss cycles
962 system.cpu0.l2cache.overall_miss_latency::cpu0.data 5113853497 # number of overall miss cycles
963 system.cpu0.l2cache.overall_miss_latency::total 8000769997 # number of overall miss cycles
964 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79666 # number of ReadReq accesses(hits+misses)
965 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4338 # number of ReadReq accesses(hits+misses)
966 system.cpu0.l2cache.ReadReq_accesses::total 84004 # number of ReadReq accesses(hits+misses)
967 system.cpu0.l2cache.Writeback_accesses::writebacks 493050 # number of Writeback accesses(hits+misses)
968 system.cpu0.l2cache.Writeback_accesses::total 493050 # number of Writeback accesses(hits+misses)
969 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56043 # number of UpgradeReq accesses(hits+misses)
970 system.cpu0.l2cache.UpgradeReq_accesses::total 56043 # number of UpgradeReq accesses(hits+misses)
971 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21235 # number of SCUpgradeReq accesses(hits+misses)
972 system.cpu0.l2cache.SCUpgradeReq_accesses::total 21235 # number of SCUpgradeReq accesses(hits+misses)
973 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
974 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
975 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256915 # number of ReadExReq accesses(hits+misses)
976 system.cpu0.l2cache.ReadExReq_accesses::total 256915 # number of ReadExReq accesses(hits+misses)
977 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1880268 # number of ReadCleanReq accesses(hits+misses)
978 system.cpu0.l2cache.ReadCleanReq_accesses::total 1880268 # number of ReadCleanReq accesses(hits+misses)
979 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478285 # number of ReadSharedReq accesses(hits+misses)
980 system.cpu0.l2cache.ReadSharedReq_accesses::total 478285 # number of ReadSharedReq accesses(hits+misses)
981 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79666 # number of demand (read+write) accesses
982 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4338 # number of demand (read+write) accesses
983 system.cpu0.l2cache.demand_accesses::cpu0.inst 1880268 # number of demand (read+write) accesses
984 system.cpu0.l2cache.demand_accesses::cpu0.data 735200 # number of demand (read+write) accesses
985 system.cpu0.l2cache.demand_accesses::total 2699472 # number of demand (read+write) accesses
986 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79666 # number of overall (read+write) accesses
987 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4338 # number of overall (read+write) accesses
988 system.cpu0.l2cache.overall_accesses::cpu0.inst 1880268 # number of overall (read+write) accesses
989 system.cpu0.l2cache.overall_accesses::cpu0.data 735200 # number of overall (read+write) accesses
990 system.cpu0.l2cache.overall_accesses::total 2699472 # number of overall (read+write) accesses
991 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for ReadReq accesses
992 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.024205 # miss rate for ReadReq accesses
993 system.cpu0.l2cache.ReadReq_miss_rate::total 0.010380 # miss rate for ReadReq accesses
994 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496815 # miss rate for UpgradeReq accesses
995 system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496815 # miss rate for UpgradeReq accesses
996 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.919896 # miss rate for SCUpgradeReq accesses
997 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.919896 # miss rate for SCUpgradeReq accesses
998 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
999 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1000 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171652 # miss rate for ReadExReq accesses
1001 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171652 # miss rate for ReadExReq accesses
1002 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034040 # miss rate for ReadCleanReq accesses
1003 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034040 # miss rate for ReadCleanReq accesses
1004 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211209 # miss rate for ReadSharedReq accesses
1005 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211209 # miss rate for ReadSharedReq accesses
1006 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for demand accesses
1007 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.024205 # miss rate for demand accesses
1008 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034040 # miss rate for demand accesses
1009 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197386 # miss rate for demand accesses
1010 system.cpu0.l2cache.demand_miss_rate::total 0.077791 # miss rate for demand accesses
1011 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for overall accesses
1012 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.024205 # miss rate for overall accesses
1013 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034040 # miss rate for overall accesses
1014 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197386 # miss rate for overall accesses
1015 system.cpu0.l2cache.overall_miss_rate::total 0.077791 # miss rate for overall accesses
1016 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average ReadReq miss latency
1017 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762 # average ReadReq miss latency
1018 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468 # average ReadReq miss latency
1019 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342 # average UpgradeReq miss latency
1020 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342 # average UpgradeReq miss latency
1021 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171 # average SCUpgradeReq miss latency
1022 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171 # average SCUpgradeReq miss latency
1023 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 417500 # average SCUpgradeFailReq miss latency
1024 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 417500 # average SCUpgradeFailReq miss latency
1025 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193 # average ReadExReq miss latency
1026 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193 # average ReadExReq miss latency
1027 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655 # average ReadCleanReq miss latency
1028 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655 # average ReadCleanReq miss latency
1029 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989 # average ReadSharedReq miss latency
1030 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989 # average ReadSharedReq miss latency
1031 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
1032 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
1033 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
1034 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
1035 system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886 # average overall miss latency
1036 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
1037 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
1038 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
1039 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
1040 system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886 # average overall miss latency
1041 system.cpu0.l2cache.blocked_cycles::no_mshrs 60 # number of cycles access was blocked
1042 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1043 system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1044 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1045 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1046 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1047 system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1048 system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1049 system.cpu0.l2cache.writebacks::writebacks 195910 # number of writebacks
1050 system.cpu0.l2cache.writebacks::total 195910 # number of writebacks
1051 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2609 # number of ReadExReq MSHR hits
1052 system.cpu0.l2cache.ReadExReq_mshr_hits::total 2609 # number of ReadExReq MSHR hits
1053 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 70 # number of ReadCleanReq MSHR hits
1054 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 70 # number of ReadCleanReq MSHR hits
1055 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 363 # number of ReadSharedReq MSHR hits
1056 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
1057 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 70 # number of demand (read+write) MSHR hits
1058 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 2972 # number of demand (read+write) MSHR hits
1059 system.cpu0.l2cache.demand_mshr_hits::total 3042 # number of demand (read+write) MSHR hits
1060 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 70 # number of overall MSHR hits
1061 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 2972 # number of overall MSHR hits
1062 system.cpu0.l2cache.overall_mshr_hits::total 3042 # number of overall MSHR hits
1063 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 767 # number of ReadReq MSHR misses
1064 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 105 # number of ReadReq MSHR misses
1065 system.cpu0.l2cache.ReadReq_mshr_misses::total 872 # number of ReadReq MSHR misses
1066 system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9288 # number of CleanEvict MSHR misses
1067 system.cpu0.l2cache.CleanEvict_mshr_misses::total 9288 # number of CleanEvict MSHR misses
1068 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of HardPFReq MSHR misses
1069 system.cpu0.l2cache.HardPFReq_mshr_misses::total 233934 # number of HardPFReq MSHR misses
1070 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27843 # number of UpgradeReq MSHR misses
1071 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27843 # number of UpgradeReq MSHR misses
1072 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19534 # number of SCUpgradeReq MSHR misses
1073 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19534 # number of SCUpgradeReq MSHR misses
1074 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
1075 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
1076 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41491 # number of ReadExReq MSHR misses
1077 system.cpu0.l2cache.ReadExReq_mshr_misses::total 41491 # number of ReadExReq MSHR misses
1078 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 63935 # number of ReadCleanReq MSHR misses
1079 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 63935 # number of ReadCleanReq MSHR misses
1080 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100655 # number of ReadSharedReq MSHR misses
1081 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100655 # number of ReadSharedReq MSHR misses
1082 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 767 # number of demand (read+write) MSHR misses
1083 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 105 # number of demand (read+write) MSHR misses
1084 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63935 # number of demand (read+write) MSHR misses
1085 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142146 # number of demand (read+write) MSHR misses
1086 system.cpu0.l2cache.demand_mshr_misses::total 206953 # number of demand (read+write) MSHR misses
1087 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 767 # number of overall MSHR misses
1088 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 105 # number of overall MSHR misses
1089 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63935 # number of overall MSHR misses
1090 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142146 # number of overall MSHR misses
1091 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of overall MSHR misses
1092 system.cpu0.l2cache.overall_mshr_misses::total 440887 # number of overall MSHR misses
1093 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
1094 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
1095 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21427 # number of ReadReq MSHR uncacheable
1096 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
1097 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
1098 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
1099 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
1100 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38183 # number of overall MSHR uncacheable misses
1101 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of ReadReq MSHR miss cycles
1102 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1928000 # number of ReadReq MSHR miss cycles
1103 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 23501500 # number of ReadReq MSHR miss cycles
1104 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of HardPFReq MSHR miss cycles
1105 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13851204796 # number of HardPFReq MSHR miss cycles
1106 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 554776500 # number of UpgradeReq MSHR miss cycles
1107 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 554776500 # number of UpgradeReq MSHR miss cycles
1108 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298118500 # number of SCUpgradeReq MSHR miss cycles
1109 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298118500 # number of SCUpgradeReq MSHR miss cycles
1110 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 351500 # number of SCUpgradeFailReq MSHR miss cycles
1111 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 351500 # number of SCUpgradeFailReq MSHR miss cycles
1112 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1669946000 # number of ReadExReq MSHR miss cycles
1113 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1669946000 # number of ReadExReq MSHR miss cycles
1114 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2472260000 # number of ReadCleanReq MSHR miss cycles
1115 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2472260000 # number of ReadCleanReq MSHR miss cycles
1116 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2283319997 # number of ReadSharedReq MSHR miss cycles
1117 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2283319997 # number of ReadSharedReq MSHR miss cycles
1118 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of demand (read+write) MSHR miss cycles
1119 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1928000 # number of demand (read+write) MSHR miss cycles
1120 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2472260000 # number of demand (read+write) MSHR miss cycles
1121 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3953265997 # number of demand (read+write) MSHR miss cycles
1122 system.cpu0.l2cache.demand_mshr_miss_latency::total 6449027497 # number of demand (read+write) MSHR miss cycles
1123 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of overall MSHR miss cycles
1124 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1928000 # number of overall MSHR miss cycles
1125 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2472260000 # number of overall MSHR miss cycles
1126 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3953265997 # number of overall MSHR miss cycles
1127 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of overall MSHR miss cycles
1128 system.cpu0.l2cache.overall_mshr_miss_latency::total 20300232293 # number of overall MSHR miss cycles
1129 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles
1130 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607256500 # number of ReadReq MSHR uncacheable cycles
1131 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894127000 # number of ReadReq MSHR uncacheable cycles
1132 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599622000 # number of WriteReq MSHR uncacheable cycles
1133 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599622000 # number of WriteReq MSHR uncacheable cycles
1134 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles
1135 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6206878500 # number of overall MSHR uncacheable cycles
1136 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6493749000 # number of overall MSHR uncacheable cycles
1137 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for ReadReq accesses
1138 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for ReadReq accesses
1139 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010380 # mshr miss rate for ReadReq accesses
1140 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1141 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1142 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1143 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1144 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496815 # mshr miss rate for UpgradeReq accesses
1145 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496815 # mshr miss rate for UpgradeReq accesses
1146 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.919896 # mshr miss rate for SCUpgradeReq accesses
1147 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.919896 # mshr miss rate for SCUpgradeReq accesses
1148 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1149 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1150 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161497 # mshr miss rate for ReadExReq accesses
1151 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161497 # mshr miss rate for ReadExReq accesses
1152 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for ReadCleanReq accesses
1153 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034003 # mshr miss rate for ReadCleanReq accesses
1154 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210450 # mshr miss rate for ReadSharedReq accesses
1155 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210450 # mshr miss rate for ReadSharedReq accesses
1156 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for demand accesses
1157 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for demand accesses
1158 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for demand accesses
1159 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for demand accesses
1160 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076664 # mshr miss rate for demand accesses
1161 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for overall accesses
1162 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for overall accesses
1163 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for overall accesses
1164 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for overall accesses
1165 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1166 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163323 # mshr miss rate for overall accesses
1167 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average ReadReq mshr miss latency
1168 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average ReadReq mshr miss latency
1169 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468 # average ReadReq mshr miss latency
1170 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average HardPFReq mshr miss latency
1171 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112 # average HardPFReq mshr miss latency
1172 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702 # average UpgradeReq mshr miss latency
1173 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702 # average UpgradeReq mshr miss latency
1174 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378 # average SCUpgradeReq mshr miss latency
1175 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378 # average SCUpgradeReq mshr miss latency
1176 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 351500 # average SCUpgradeFailReq mshr miss latency
1177 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 351500 # average SCUpgradeFailReq mshr miss latency
1178 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217 # average ReadExReq mshr miss latency
1179 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217 # average ReadExReq mshr miss latency
1180 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average ReadCleanReq mshr miss latency
1181 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028 # average ReadCleanReq mshr miss latency
1182 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737 # average ReadSharedReq mshr miss latency
1183 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737 # average ReadSharedReq mshr miss latency
1184 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
1185 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
1186 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
1187 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
1188 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592 # average overall mshr miss latency
1189 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
1190 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
1191 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
1192 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
1193 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average overall mshr miss latency
1194 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914 # average overall mshr miss latency
1195 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency
1196 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000 # average ReadReq mshr uncacheable latency
1197 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212 # average ReadReq mshr uncacheable latency
1198 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840 # average WriteReq mshr uncacheable latency
1199 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840 # average WriteReq mshr uncacheable latency
1200 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency
1201 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837 # average overall mshr uncacheable latency
1202 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527 # average overall mshr uncacheable latency
1203 system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1204 system.cpu0.toL2Bus.trans_dist::ReadReq 136175 # Transaction distribution
1205 system.cpu0.toL2Bus.trans_dist::ReadResp 2526619 # Transaction distribution
1206 system.cpu0.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
1207 system.cpu0.toL2Bus.trans_dist::WriteResp 16756 # Transaction distribution
1208 system.cpu0.toL2Bus.trans_dist::Writeback 865136 # Transaction distribution
1209 system.cpu0.toL2Bus.trans_dist::CleanEvict 2178805 # Transaction distribution
1210 system.cpu0.toL2Bus.trans_dist::HardPFReq 280675 # Transaction distribution
1211 system.cpu0.toL2Bus.trans_dist::UpgradeReq 92865 # Transaction distribution
1212 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43660 # Transaction distribution
1213 system.cpu0.toL2Bus.trans_dist::UpgradeResp 114593 # Transaction distribution
1214 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution
1215 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
1216 system.cpu0.toL2Bus.trans_dist::ReadExReq 285252 # Transaction distribution
1217 system.cpu0.toL2Bus.trans_dist::ReadExResp 271172 # Transaction distribution
1218 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1880268 # Transaction distribution
1219 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604912 # Transaction distribution
1220 system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1221 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5613549 # Packet count per connected master and slave (bytes)
1222 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2467613 # Packet count per connected master and slave (bytes)
1223 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11765 # Packet count per connected master and slave (bytes)
1224 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 169746 # Packet count per connected master and slave (bytes)
1225 system.cpu0.toL2Bus.pkt_count::total 8262673 # Packet count per connected master and slave (bytes)
1226 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120556352 # Cumulative packet size per connected master and slave (bytes)
1227 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82765674 # Cumulative packet size per connected master and slave (bytes)
1228 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17352 # Cumulative packet size per connected master and slave (bytes)
1229 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 318664 # Cumulative packet size per connected master and slave (bytes)
1230 system.cpu0.toL2Bus.pkt_size::total 203658042 # Cumulative packet size per connected master and slave (bytes)
1231 system.cpu0.toL2Bus.snoops 1202366 # Total snoops (count)
1232 system.cpu0.toL2Bus.snoop_fanout::samples 6476462 # Request fanout histogram
1233 system.cpu0.toL2Bus.snoop_fanout::mean 1.183069 # Request fanout histogram
1234 system.cpu0.toL2Bus.snoop_fanout::stdev 0.386723 # Request fanout histogram
1235 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1236 system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1237 system.cpu0.toL2Bus.snoop_fanout::1 5290820 81.69% 81.69% # Request fanout histogram
1238 system.cpu0.toL2Bus.snoop_fanout::2 1185642 18.31% 100.00% # Request fanout histogram
1239 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1240 system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1241 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1242 system.cpu0.toL2Bus.snoop_fanout::total 6476462 # Request fanout histogram
1243 system.cpu0.toL2Bus.reqLayer0.occupancy 3195593995 # Layer occupancy (ticks)
1244 system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1245 system.cpu0.toL2Bus.snoopLayer0.occupancy 113765999 # Layer occupancy (ticks)
1246 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1247 system.cpu0.toL2Bus.respLayer0.occupancy 2825774529 # Layer occupancy (ticks)
1248 system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1249 system.cpu0.toL2Bus.respLayer1.occupancy 1168364927 # Layer occupancy (ticks)
1250 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1251 system.cpu0.toL2Bus.respLayer2.occupancy 7430992 # Layer occupancy (ticks)
1252 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1253 system.cpu0.toL2Bus.respLayer3.occupancy 90084491 # Layer occupancy (ticks)
1254 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1255 system.cpu1.branchPred.lookups 20439224 # Number of BP lookups
1256 system.cpu1.branchPred.condPredicted 7037667 # Number of conditional branches predicted
1257 system.cpu1.branchPred.condIncorrect 906738 # Number of conditional branches incorrect
1258 system.cpu1.branchPred.BTBLookups 10483361 # Number of BTB lookups
1259 system.cpu1.branchPred.BTBHits 7695105 # Number of BTB hits
1260 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1261 system.cpu1.branchPred.BTBHitPct 73.403034 # BTB Hit Percentage
1262 system.cpu1.branchPred.usedRAS 8822837 # Number of times the RAS was used to get a target.
1263 system.cpu1.branchPred.RASInCorrect 629691 # Number of incorrect RAS predictions.
1264 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1265 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1266 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1267 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1268 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1269 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1270 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1271 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1272 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1273 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1274 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1275 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1276 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1277 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1278 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1279 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1280 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1281 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1282 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1283 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1284 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1285 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1286 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1287 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1288 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1289 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1290 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1291 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1292 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1293 system.cpu1.dtb.walker.walks 30282 # Table walker walks requested
1294 system.cpu1.dtb.walker.walksShort 30282 # Table walker walks initiated with short descriptors
1295 system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22625 # Level at which table walker walks with short descriptors terminate
1296 system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7657 # Level at which table walker walks with short descriptors terminate
1297 system.cpu1.dtb.walker.walkWaitTime::samples 30282 # Table walker wait (enqueue to first request) latency
1298 system.cpu1.dtb.walker.walkWaitTime::0 30282 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1299 system.cpu1.dtb.walker.walkWaitTime::total 30282 # Table walker wait (enqueue to first request) latency
1300 system.cpu1.dtb.walker.walkCompletionTime::samples 2657 # Table walker service (enqueue to completion) latency
1301 system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670 # Table walker service (enqueue to completion) latency
1302 system.cpu1.dtb.walker.walkCompletionTime::gmean 9441.717442 # Table walker service (enqueue to completion) latency
1303 system.cpu1.dtb.walker.walkCompletionTime::stdev 7245.373074 # Table walker service (enqueue to completion) latency
1304 system.cpu1.dtb.walker.walkCompletionTime::0-16383 2512 94.54% 94.54% # Table walker service (enqueue to completion) latency
1305 system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 4.89% 99.44% # Table walker service (enqueue to completion) latency
1306 system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.26% 99.70% # Table walker service (enqueue to completion) latency
1307 system.cpu1.dtb.walker.walkCompletionTime::81920-98303 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
1308 system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
1309 system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1310 system.cpu1.dtb.walker.walkCompletionTime::total 2657 # Table walker service (enqueue to completion) latency
1311 system.cpu1.dtb.walker.walksPending::samples 1594102264 # Table walker pending requests distribution
1312 system.cpu1.dtb.walker.walksPending::0 1594102264 100.00% 100.00% # Table walker pending requests distribution
1313 system.cpu1.dtb.walker.walksPending::total 1594102264 # Table walker pending requests distribution
1314 system.cpu1.dtb.walker.walkPageSizes::4K 1972 74.22% 74.22% # Table walker page sizes translated
1315 system.cpu1.dtb.walker.walkPageSizes::1M 685 25.78% 100.00% # Table walker page sizes translated
1316 system.cpu1.dtb.walker.walkPageSizes::total 2657 # Table walker page sizes translated
1317 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30282 # Table walker requests started/completed, data/inst
1318 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1319 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30282 # Table walker requests started/completed, data/inst
1320 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2657 # Table walker requests started/completed, data/inst
1321 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1322 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2657 # Table walker requests started/completed, data/inst
1323 system.cpu1.dtb.walker.walkRequestOrigin::total 32939 # Table walker requests started/completed, data/inst
1324 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1325 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1326 system.cpu1.dtb.read_hits 12124185 # DTB read hits
1327 system.cpu1.dtb.read_misses 27903 # DTB read misses
1328 system.cpu1.dtb.write_hits 7716793 # DTB write hits
1329 system.cpu1.dtb.write_misses 2379 # DTB write misses
1330 system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1331 system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1332 system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1333 system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1334 system.cpu1.dtb.flush_entries 2053 # Number of entries that have been flushed from TLB
1335 system.cpu1.dtb.align_faults 374 # Number of TLB faults due to alignment restrictions
1336 system.cpu1.dtb.prefetch_faults 549 # Number of TLB faults due to prefetch
1337 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1338 system.cpu1.dtb.perms_faults 291 # Number of TLB faults due to permissions restrictions
1339 system.cpu1.dtb.read_accesses 12152088 # DTB read accesses
1340 system.cpu1.dtb.write_accesses 7719172 # DTB write accesses
1341 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1342 system.cpu1.dtb.hits 19840978 # DTB hits
1343 system.cpu1.dtb.misses 30282 # DTB misses
1344 system.cpu1.dtb.accesses 19871260 # DTB accesses
1345 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1346 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1347 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1348 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1349 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1350 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1351 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1352 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1353 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1354 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1355 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1356 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1357 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1358 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1359 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1360 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1361 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1362 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1363 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1364 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1365 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1366 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1367 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1368 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1369 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1370 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1371 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1372 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1373 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1374 system.cpu1.itb.walker.walks 2290 # Table walker walks requested
1375 system.cpu1.itb.walker.walksShort 2290 # Table walker walks initiated with short descriptors
1376 system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate
1377 system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2108 # Level at which table walker walks with short descriptors terminate
1378 system.cpu1.itb.walker.walkWaitTime::samples 2290 # Table walker wait (enqueue to first request) latency
1379 system.cpu1.itb.walker.walkWaitTime::0 2290 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1380 system.cpu1.itb.walker.walkWaitTime::total 2290 # Table walker wait (enqueue to first request) latency
1381 system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
1382 system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489 # Table walker service (enqueue to completion) latency
1383 system.cpu1.itb.walker.walkCompletionTime::gmean 9754.511529 # Table walker service (enqueue to completion) latency
1384 system.cpu1.itb.walker.walkCompletionTime::stdev 5025.096618 # Table walker service (enqueue to completion) latency
1385 system.cpu1.itb.walker.walkCompletionTime::4096-8191 329 29.30% 29.30% # Table walker service (enqueue to completion) latency
1386 system.cpu1.itb.walker.walkCompletionTime::8192-12287 526 46.84% 76.14% # Table walker service (enqueue to completion) latency
1387 system.cpu1.itb.walker.walkCompletionTime::12288-16383 229 20.39% 96.53% # Table walker service (enqueue to completion) latency
1388 system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.71% # Table walker service (enqueue to completion) latency
1389 system.cpu1.itb.walker.walkCompletionTime::24576-28671 14 1.25% 97.95% # Table walker service (enqueue to completion) latency
1390 system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.87% 99.82% # Table walker service (enqueue to completion) latency
1391 system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
1392 system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1393 system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
1394 system.cpu1.itb.walker.walksPending::samples 1593536764 # Table walker pending requests distribution
1395 system.cpu1.itb.walker.walksPending::0 1593536764 100.00% 100.00% # Table walker pending requests distribution
1396 system.cpu1.itb.walker.walksPending::total 1593536764 # Table walker pending requests distribution
1397 system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated
1398 system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated
1399 system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
1400 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1401 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2290 # Table walker requests started/completed, data/inst
1402 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2290 # Table walker requests started/completed, data/inst
1403 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1404 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
1405 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
1406 system.cpu1.itb.walker.walkRequestOrigin::total 3413 # Table walker requests started/completed, data/inst
1407 system.cpu1.itb.inst_hits 41919801 # ITB inst hits
1408 system.cpu1.itb.inst_misses 2290 # ITB inst misses
1409 system.cpu1.itb.read_hits 0 # DTB read hits
1410 system.cpu1.itb.read_misses 0 # DTB read misses
1411 system.cpu1.itb.write_hits 0 # DTB write hits
1412 system.cpu1.itb.write_misses 0 # DTB write misses
1413 system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1414 system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1415 system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1416 system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1417 system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
1418 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1419 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1420 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1421 system.cpu1.itb.perms_faults 1868 # Number of TLB faults due to permissions restrictions
1422 system.cpu1.itb.read_accesses 0 # DTB read accesses
1423 system.cpu1.itb.write_accesses 0 # DTB write accesses
1424 system.cpu1.itb.inst_accesses 41922091 # ITB inst accesses
1425 system.cpu1.itb.hits 41919801 # DTB hits
1426 system.cpu1.itb.misses 2290 # DTB misses
1427 system.cpu1.itb.accesses 41922091 # DTB accesses
1428 system.cpu1.numCycles 125017818 # number of cpu cycles simulated
1429 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1430 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1431 system.cpu1.committedInsts 51886096 # Number of instructions committed
1432 system.cpu1.committedOps 63386159 # Number of ops (including micro ops) committed
1433 system.cpu1.discardedOps 5353179 # Number of ops (including micro ops) which were discarded before commit
1434 system.cpu1.numFetchSuspends 2738 # Number of times Execute suspended instruction fetching
1435 system.cpu1.quiesceCycles 5566469050 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1436 system.cpu1.cpi 2.409467 # CPI: cycles per instruction
1437 system.cpu1.ipc 0.415030 # IPC: instructions per cycle
1438 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1439 system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
1440 system.cpu1.tickCycles 105304281 # Number of cycles that the object actually ticked
1441 system.cpu1.idleCycles 19713537 # Total number of cycles that the object has spent stopped
1442 system.cpu1.dcache.tags.replacements 231375 # number of replacements
1443 system.cpu1.dcache.tags.tagsinuse 483.037999 # Cycle average of tags in use
1444 system.cpu1.dcache.tags.total_refs 19321104 # Total number of references to valid blocks.
1445 system.cpu1.dcache.tags.sampled_refs 231701 # Sample count of references to valid blocks.
1446 system.cpu1.dcache.tags.avg_refs 83.388091 # Average number of references to valid blocks.
1447 system.cpu1.dcache.tags.warmup_cycle 90467560500 # Cycle when the warmup percentage was hit.
1448 system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.037999 # Average occupied blocks per requestor
1449 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943434 # Average percentage of cache occupancy
1450 system.cpu1.dcache.tags.occ_percent::total 0.943434 # Average percentage of cache occupancy
1451 system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id
1452 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id
1453 system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id
1454 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id
1455 system.cpu1.dcache.tags.tag_accesses 39693132 # Number of tag accesses
1456 system.cpu1.dcache.tags.data_accesses 39693132 # Number of data accesses
1457 system.cpu1.dcache.ReadReq_hits::cpu1.data 11664966 # number of ReadReq hits
1458 system.cpu1.dcache.ReadReq_hits::total 11664966 # number of ReadReq hits
1459 system.cpu1.dcache.WriteReq_hits::cpu1.data 7379255 # number of WriteReq hits
1460 system.cpu1.dcache.WriteReq_hits::total 7379255 # number of WriteReq hits
1461 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66113 # number of SoftPFReq hits
1462 system.cpu1.dcache.SoftPFReq_hits::total 66113 # number of SoftPFReq hits
1463 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88582 # number of LoadLockedReq hits
1464 system.cpu1.dcache.LoadLockedReq_hits::total 88582 # number of LoadLockedReq hits
1465 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80498 # number of StoreCondReq hits
1466 system.cpu1.dcache.StoreCondReq_hits::total 80498 # number of StoreCondReq hits
1467 system.cpu1.dcache.demand_hits::cpu1.data 19044221 # number of demand (read+write) hits
1468 system.cpu1.dcache.demand_hits::total 19044221 # number of demand (read+write) hits
1469 system.cpu1.dcache.overall_hits::cpu1.data 19110334 # number of overall hits
1470 system.cpu1.dcache.overall_hits::total 19110334 # number of overall hits
1471 system.cpu1.dcache.ReadReq_misses::cpu1.data 184342 # number of ReadReq misses
1472 system.cpu1.dcache.ReadReq_misses::total 184342 # number of ReadReq misses
1473 system.cpu1.dcache.WriteReq_misses::cpu1.data 167268 # number of WriteReq misses
1474 system.cpu1.dcache.WriteReq_misses::total 167268 # number of WriteReq misses
1475 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34982 # number of SoftPFReq misses
1476 system.cpu1.dcache.SoftPFReq_misses::total 34982 # number of SoftPFReq misses
1477 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17676 # number of LoadLockedReq misses
1478 system.cpu1.dcache.LoadLockedReq_misses::total 17676 # number of LoadLockedReq misses
1479 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23450 # number of StoreCondReq misses
1480 system.cpu1.dcache.StoreCondReq_misses::total 23450 # number of StoreCondReq misses
1481 system.cpu1.dcache.demand_misses::cpu1.data 351610 # number of demand (read+write) misses
1482 system.cpu1.dcache.demand_misses::total 351610 # number of demand (read+write) misses
1483 system.cpu1.dcache.overall_misses::cpu1.data 386592 # number of overall misses
1484 system.cpu1.dcache.overall_misses::total 386592 # number of overall misses
1485 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719374500 # number of ReadReq miss cycles
1486 system.cpu1.dcache.ReadReq_miss_latency::total 2719374500 # number of ReadReq miss cycles
1487 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4153510500 # number of WriteReq miss cycles
1488 system.cpu1.dcache.WriteReq_miss_latency::total 4153510500 # number of WriteReq miss cycles
1489 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325753000 # number of LoadLockedReq miss cycles
1490 system.cpu1.dcache.LoadLockedReq_miss_latency::total 325753000 # number of LoadLockedReq miss cycles
1491 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548137000 # number of StoreCondReq miss cycles
1492 system.cpu1.dcache.StoreCondReq_miss_latency::total 548137000 # number of StoreCondReq miss cycles
1493 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 684500 # number of StoreCondFailReq miss cycles
1494 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 684500 # number of StoreCondFailReq miss cycles
1495 system.cpu1.dcache.demand_miss_latency::cpu1.data 6872885000 # number of demand (read+write) miss cycles
1496 system.cpu1.dcache.demand_miss_latency::total 6872885000 # number of demand (read+write) miss cycles
1497 system.cpu1.dcache.overall_miss_latency::cpu1.data 6872885000 # number of overall miss cycles
1498 system.cpu1.dcache.overall_miss_latency::total 6872885000 # number of overall miss cycles
1499 system.cpu1.dcache.ReadReq_accesses::cpu1.data 11849308 # number of ReadReq accesses(hits+misses)
1500 system.cpu1.dcache.ReadReq_accesses::total 11849308 # number of ReadReq accesses(hits+misses)
1501 system.cpu1.dcache.WriteReq_accesses::cpu1.data 7546523 # number of WriteReq accesses(hits+misses)
1502 system.cpu1.dcache.WriteReq_accesses::total 7546523 # number of WriteReq accesses(hits+misses)
1503 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101095 # number of SoftPFReq accesses(hits+misses)
1504 system.cpu1.dcache.SoftPFReq_accesses::total 101095 # number of SoftPFReq accesses(hits+misses)
1505 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106258 # number of LoadLockedReq accesses(hits+misses)
1506 system.cpu1.dcache.LoadLockedReq_accesses::total 106258 # number of LoadLockedReq accesses(hits+misses)
1507 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103948 # number of StoreCondReq accesses(hits+misses)
1508 system.cpu1.dcache.StoreCondReq_accesses::total 103948 # number of StoreCondReq accesses(hits+misses)
1509 system.cpu1.dcache.demand_accesses::cpu1.data 19395831 # number of demand (read+write) accesses
1510 system.cpu1.dcache.demand_accesses::total 19395831 # number of demand (read+write) accesses
1511 system.cpu1.dcache.overall_accesses::cpu1.data 19496926 # number of overall (read+write) accesses
1512 system.cpu1.dcache.overall_accesses::total 19496926 # number of overall (read+write) accesses
1513 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015557 # miss rate for ReadReq accesses
1514 system.cpu1.dcache.ReadReq_miss_rate::total 0.015557 # miss rate for ReadReq accesses
1515 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022165 # miss rate for WriteReq accesses
1516 system.cpu1.dcache.WriteReq_miss_rate::total 0.022165 # miss rate for WriteReq accesses
1517 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346031 # miss rate for SoftPFReq accesses
1518 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346031 # miss rate for SoftPFReq accesses
1519 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166350 # miss rate for LoadLockedReq accesses
1520 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166350 # miss rate for LoadLockedReq accesses
1521 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225594 # miss rate for StoreCondReq accesses
1522 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225594 # miss rate for StoreCondReq accesses
1523 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018128 # miss rate for demand accesses
1524 system.cpu1.dcache.demand_miss_rate::total 0.018128 # miss rate for demand accesses
1525 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019828 # miss rate for overall accesses
1526 system.cpu1.dcache.overall_miss_rate::total 0.019828 # miss rate for overall accesses
1527 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151 # average ReadReq miss latency
1528 system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151 # average ReadReq miss latency
1529 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052 # average WriteReq miss latency
1530 system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052 # average WriteReq miss latency
1531 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921 # average LoadLockedReq miss latency
1532 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921 # average LoadLockedReq miss latency
1533 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154 # average StoreCondReq miss latency
1534 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154 # average StoreCondReq miss latency
1535 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1536 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1537 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552 # average overall miss latency
1538 system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552 # average overall miss latency
1539 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605 # average overall miss latency
1540 system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605 # average overall miss latency
1541 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1542 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1543 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1544 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1545 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1546 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1547 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1548 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1549 system.cpu1.dcache.writebacks::writebacks 138377 # number of writebacks
1550 system.cpu1.dcache.writebacks::total 138377 # number of writebacks
1551 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18221 # number of ReadReq MSHR hits
1552 system.cpu1.dcache.ReadReq_mshr_hits::total 18221 # number of ReadReq MSHR hits
1553 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62038 # number of WriteReq MSHR hits
1554 system.cpu1.dcache.WriteReq_mshr_hits::total 62038 # number of WriteReq MSHR hits
1555 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12225 # number of LoadLockedReq MSHR hits
1556 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12225 # number of LoadLockedReq MSHR hits
1557 system.cpu1.dcache.demand_mshr_hits::cpu1.data 80259 # number of demand (read+write) MSHR hits
1558 system.cpu1.dcache.demand_mshr_hits::total 80259 # number of demand (read+write) MSHR hits
1559 system.cpu1.dcache.overall_mshr_hits::cpu1.data 80259 # number of overall MSHR hits
1560 system.cpu1.dcache.overall_mshr_hits::total 80259 # number of overall MSHR hits
1561 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166121 # number of ReadReq MSHR misses
1562 system.cpu1.dcache.ReadReq_mshr_misses::total 166121 # number of ReadReq MSHR misses
1563 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105230 # number of WriteReq MSHR misses
1564 system.cpu1.dcache.WriteReq_mshr_misses::total 105230 # number of WriteReq MSHR misses
1565 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33463 # number of SoftPFReq MSHR misses
1566 system.cpu1.dcache.SoftPFReq_mshr_misses::total 33463 # number of SoftPFReq MSHR misses
1567 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5451 # number of LoadLockedReq MSHR misses
1568 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5451 # number of LoadLockedReq MSHR misses
1569 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23450 # number of StoreCondReq MSHR misses
1570 system.cpu1.dcache.StoreCondReq_mshr_misses::total 23450 # number of StoreCondReq MSHR misses
1571 system.cpu1.dcache.demand_mshr_misses::cpu1.data 271351 # number of demand (read+write) MSHR misses
1572 system.cpu1.dcache.demand_mshr_misses::total 271351 # number of demand (read+write) MSHR misses
1573 system.cpu1.dcache.overall_mshr_misses::cpu1.data 304814 # number of overall MSHR misses
1574 system.cpu1.dcache.overall_mshr_misses::total 304814 # number of overall MSHR misses
1575 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
1576 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17128 # number of ReadReq MSHR uncacheable
1577 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
1578 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
1579 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
1580 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31533 # number of overall MSHR uncacheable misses
1581 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2295109000 # number of ReadReq MSHR miss cycles
1582 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2295109000 # number of ReadReq MSHR miss cycles
1583 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517034000 # number of WriteReq MSHR miss cycles
1584 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517034000 # number of WriteReq MSHR miss cycles
1585 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 544638000 # number of SoftPFReq MSHR miss cycles
1586 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 544638000 # number of SoftPFReq MSHR miss cycles
1587 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92810500 # number of LoadLockedReq MSHR miss cycles
1588 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92810500 # number of LoadLockedReq MSHR miss cycles
1589 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524700000 # number of StoreCondReq MSHR miss cycles
1590 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524700000 # number of StoreCondReq MSHR miss cycles
1591 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 671500 # number of StoreCondFailReq MSHR miss cycles
1592 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 671500 # number of StoreCondFailReq MSHR miss cycles
1593 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4812143000 # number of demand (read+write) MSHR miss cycles
1594 system.cpu1.dcache.demand_mshr_miss_latency::total 4812143000 # number of demand (read+write) MSHR miss cycles
1595 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5356781000 # number of overall MSHR miss cycles
1596 system.cpu1.dcache.overall_mshr_miss_latency::total 5356781000 # number of overall MSHR miss cycles
1597 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2934873000 # number of ReadReq MSHR uncacheable cycles
1598 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2934873000 # number of ReadReq MSHR uncacheable cycles
1599 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2446602500 # number of WriteReq MSHR uncacheable cycles
1600 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2446602500 # number of WriteReq MSHR uncacheable cycles
1601 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5381475500 # number of overall MSHR uncacheable cycles
1602 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5381475500 # number of overall MSHR uncacheable cycles
1603 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014019 # mshr miss rate for ReadReq accesses
1604 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014019 # mshr miss rate for ReadReq accesses
1605 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013944 # mshr miss rate for WriteReq accesses
1606 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013944 # mshr miss rate for WriteReq accesses
1607 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331005 # mshr miss rate for SoftPFReq accesses
1608 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331005 # mshr miss rate for SoftPFReq accesses
1609 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051300 # mshr miss rate for LoadLockedReq accesses
1610 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051300 # mshr miss rate for LoadLockedReq accesses
1611 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225594 # mshr miss rate for StoreCondReq accesses
1612 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225594 # mshr miss rate for StoreCondReq accesses
1613 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013990 # mshr miss rate for demand accesses
1614 system.cpu1.dcache.demand_mshr_miss_rate::total 0.013990 # mshr miss rate for demand accesses
1615 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015634 # mshr miss rate for overall accesses
1616 system.cpu1.dcache.overall_mshr_miss_rate::total 0.015634 # mshr miss rate for overall accesses
1617 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215 # average ReadReq mshr miss latency
1618 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215 # average ReadReq mshr miss latency
1619 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598 # average WriteReq mshr miss latency
1620 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598 # average WriteReq mshr miss latency
1621 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033 # average SoftPFReq mshr miss latency
1622 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033 # average SoftPFReq mshr miss latency
1623 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445 # average LoadLockedReq mshr miss latency
1624 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445 # average LoadLockedReq mshr miss latency
1625 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525 # average StoreCondReq mshr miss latency
1626 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525 # average StoreCondReq mshr miss latency
1627 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1628 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1629 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090 # average overall mshr miss latency
1630 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090 # average overall mshr miss latency
1631 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612 # average overall mshr miss latency
1632 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612 # average overall mshr miss latency
1633 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837 # average ReadReq mshr uncacheable latency
1634 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837 # average ReadReq mshr uncacheable latency
1635 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785 # average WriteReq mshr uncacheable latency
1636 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785 # average WriteReq mshr uncacheable latency
1637 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612 # average overall mshr uncacheable latency
1638 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612 # average overall mshr uncacheable latency
1639 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1640 system.cpu1.icache.tags.replacements 1042125 # number of replacements
1641 system.cpu1.icache.tags.tagsinuse 499.329120 # Cycle average of tags in use
1642 system.cpu1.icache.tags.total_refs 40875126 # Total number of references to valid blocks.
1643 system.cpu1.icache.tags.sampled_refs 1042637 # Sample count of references to valid blocks.
1644 system.cpu1.icache.tags.avg_refs 39.203602 # Average number of references to valid blocks.
1645 system.cpu1.icache.tags.warmup_cycle 72106351500 # Cycle when the warmup percentage was hit.
1646 system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.329120 # Average occupied blocks per requestor
1647 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975252 # Average percentage of cache occupancy
1648 system.cpu1.icache.tags.occ_percent::total 0.975252 # Average percentage of cache occupancy
1649 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1650 system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id
1651 system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id
1652 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1653 system.cpu1.icache.tags.tag_accesses 84878163 # Number of tag accesses
1654 system.cpu1.icache.tags.data_accesses 84878163 # Number of data accesses
1655 system.cpu1.icache.ReadReq_hits::cpu1.inst 40875126 # number of ReadReq hits
1656 system.cpu1.icache.ReadReq_hits::total 40875126 # number of ReadReq hits
1657 system.cpu1.icache.demand_hits::cpu1.inst 40875126 # number of demand (read+write) hits
1658 system.cpu1.icache.demand_hits::total 40875126 # number of demand (read+write) hits
1659 system.cpu1.icache.overall_hits::cpu1.inst 40875126 # number of overall hits
1660 system.cpu1.icache.overall_hits::total 40875126 # number of overall hits
1661 system.cpu1.icache.ReadReq_misses::cpu1.inst 1042637 # number of ReadReq misses
1662 system.cpu1.icache.ReadReq_misses::total 1042637 # number of ReadReq misses
1663 system.cpu1.icache.demand_misses::cpu1.inst 1042637 # number of demand (read+write) misses
1664 system.cpu1.icache.demand_misses::total 1042637 # number of demand (read+write) misses
1665 system.cpu1.icache.overall_misses::cpu1.inst 1042637 # number of overall misses
1666 system.cpu1.icache.overall_misses::total 1042637 # number of overall misses
1667 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9237616500 # number of ReadReq miss cycles
1668 system.cpu1.icache.ReadReq_miss_latency::total 9237616500 # number of ReadReq miss cycles
1669 system.cpu1.icache.demand_miss_latency::cpu1.inst 9237616500 # number of demand (read+write) miss cycles
1670 system.cpu1.icache.demand_miss_latency::total 9237616500 # number of demand (read+write) miss cycles
1671 system.cpu1.icache.overall_miss_latency::cpu1.inst 9237616500 # number of overall miss cycles
1672 system.cpu1.icache.overall_miss_latency::total 9237616500 # number of overall miss cycles
1673 system.cpu1.icache.ReadReq_accesses::cpu1.inst 41917763 # number of ReadReq accesses(hits+misses)
1674 system.cpu1.icache.ReadReq_accesses::total 41917763 # number of ReadReq accesses(hits+misses)
1675 system.cpu1.icache.demand_accesses::cpu1.inst 41917763 # number of demand (read+write) accesses
1676 system.cpu1.icache.demand_accesses::total 41917763 # number of demand (read+write) accesses
1677 system.cpu1.icache.overall_accesses::cpu1.inst 41917763 # number of overall (read+write) accesses
1678 system.cpu1.icache.overall_accesses::total 41917763 # number of overall (read+write) accesses
1679 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024873 # miss rate for ReadReq accesses
1680 system.cpu1.icache.ReadReq_miss_rate::total 0.024873 # miss rate for ReadReq accesses
1681 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024873 # miss rate for demand accesses
1682 system.cpu1.icache.demand_miss_rate::total 0.024873 # miss rate for demand accesses
1683 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024873 # miss rate for overall accesses
1684 system.cpu1.icache.overall_miss_rate::total 0.024873 # miss rate for overall accesses
1685 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8859.858704 # average ReadReq miss latency
1686 system.cpu1.icache.ReadReq_avg_miss_latency::total 8859.858704 # average ReadReq miss latency
1687 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
1688 system.cpu1.icache.demand_avg_miss_latency::total 8859.858704 # average overall miss latency
1689 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
1690 system.cpu1.icache.overall_avg_miss_latency::total 8859.858704 # average overall miss latency
1691 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1692 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1693 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1694 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1695 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1696 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1697 system.cpu1.icache.fast_writes 0 # number of fast writes performed
1698 system.cpu1.icache.cache_copies 0 # number of cache copies performed
1699 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1042637 # number of ReadReq MSHR misses
1700 system.cpu1.icache.ReadReq_mshr_misses::total 1042637 # number of ReadReq MSHR misses
1701 system.cpu1.icache.demand_mshr_misses::cpu1.inst 1042637 # number of demand (read+write) MSHR misses
1702 system.cpu1.icache.demand_mshr_misses::total 1042637 # number of demand (read+write) MSHR misses
1703 system.cpu1.icache.overall_mshr_misses::cpu1.inst 1042637 # number of overall MSHR misses
1704 system.cpu1.icache.overall_mshr_misses::total 1042637 # number of overall MSHR misses
1705 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
1706 system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable
1707 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
1708 system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses
1709 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8716298000 # number of ReadReq MSHR miss cycles
1710 system.cpu1.icache.ReadReq_mshr_miss_latency::total 8716298000 # number of ReadReq MSHR miss cycles
1711 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8716298000 # number of demand (read+write) MSHR miss cycles
1712 system.cpu1.icache.demand_mshr_miss_latency::total 8716298000 # number of demand (read+write) MSHR miss cycles
1713 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8716298000 # number of overall MSHR miss cycles
1714 system.cpu1.icache.overall_mshr_miss_latency::total 8716298000 # number of overall MSHR miss cycles
1715 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10126000 # number of ReadReq MSHR uncacheable cycles
1716 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10126000 # number of ReadReq MSHR uncacheable cycles
1717 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10126000 # number of overall MSHR uncacheable cycles
1718 system.cpu1.icache.overall_mshr_uncacheable_latency::total 10126000 # number of overall MSHR uncacheable cycles
1719 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for ReadReq accesses
1720 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024873 # mshr miss rate for ReadReq accesses
1721 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for demand accesses
1722 system.cpu1.icache.demand_mshr_miss_rate::total 0.024873 # mshr miss rate for demand accesses
1723 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for overall accesses
1724 system.cpu1.icache.overall_mshr_miss_rate::total 0.024873 # mshr miss rate for overall accesses
1725 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average ReadReq mshr miss latency
1726 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8359.858704 # average ReadReq mshr miss latency
1727 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
1728 system.cpu1.icache.demand_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
1729 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
1730 system.cpu1.icache.overall_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
1731 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average ReadReq mshr uncacheable latency
1732 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469 # average ReadReq mshr uncacheable latency
1733 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average overall mshr uncacheable latency
1734 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469 # average overall mshr uncacheable latency
1735 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1736 system.cpu1.l2cache.prefetcher.num_hwpf_issued 270674 # number of hwpf issued
1737 system.cpu1.l2cache.prefetcher.pfIdentified 270706 # number of prefetch candidates identified
1738 system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
1739 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1740 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1741 system.cpu1.l2cache.prefetcher.pfSpanPage 70190 # number of prefetches not generated due to page crossing
1742 system.cpu1.l2cache.tags.replacements 69559 # number of replacements
1743 system.cpu1.l2cache.tags.tagsinuse 15624.003278 # Cycle average of tags in use
1744 system.cpu1.l2cache.tags.total_refs 2421583 # Total number of references to valid blocks.
1745 system.cpu1.l2cache.tags.sampled_refs 84278 # Sample count of references to valid blocks.
1746 system.cpu1.l2cache.tags.avg_refs 28.733276 # Average number of references to valid blocks.
1747 system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1748 system.cpu1.l2cache.tags.occ_blocks::writebacks 6091.947681 # Average occupied blocks per requestor
1749 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 59.671167 # Average occupied blocks per requestor
1750 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.103493 # Average occupied blocks per requestor
1751 system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5612.930096 # Average occupied blocks per requestor
1752 system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2321.677903 # Average occupied blocks per requestor
1753 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1537.672938 # Average occupied blocks per requestor
1754 system.cpu1.l2cache.tags.occ_percent::writebacks 0.371823 # Average percentage of cache occupancy
1755 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003642 # Average percentage of cache occupancy
1756 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
1757 system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.342586 # Average percentage of cache occupancy
1758 system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141704 # Average percentage of cache occupancy
1759 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093852 # Average percentage of cache occupancy
1760 system.cpu1.l2cache.tags.occ_percent::total 0.953613 # Average percentage of cache occupancy
1761 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1225 # Occupied blocks per task id
1762 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
1763 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13444 # Occupied blocks per task id
1764 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
1765 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id
1766 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 522 # Occupied blocks per task id
1767 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
1768 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
1769 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
1770 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id
1771 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5775 # Occupied blocks per task id
1772 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7342 # Occupied blocks per task id
1773 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074768 # Percentage of cache occupancy per task id
1774 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
1775 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820557 # Percentage of cache occupancy per task id
1776 system.cpu1.l2cache.tags.tag_accesses 42869923 # Number of tag accesses
1777 system.cpu1.l2cache.tags.data_accesses 42869923 # Number of data accesses
1778 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33040 # number of ReadReq hits
1779 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2583 # number of ReadReq hits
1780 system.cpu1.l2cache.ReadReq_hits::total 35623 # number of ReadReq hits
1781 system.cpu1.l2cache.Writeback_hits::writebacks 138377 # number of Writeback hits
1782 system.cpu1.l2cache.Writeback_hits::total 138377 # number of Writeback hits
1783 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2042 # number of UpgradeReq hits
1784 system.cpu1.l2cache.UpgradeReq_hits::total 2042 # number of UpgradeReq hits
1785 system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1012 # number of SCUpgradeReq hits
1786 system.cpu1.l2cache.SCUpgradeReq_hits::total 1012 # number of SCUpgradeReq hits
1787 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37732 # number of ReadExReq hits
1788 system.cpu1.l2cache.ReadExReq_hits::total 37732 # number of ReadExReq hits
1789 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1015029 # number of ReadCleanReq hits
1790 system.cpu1.l2cache.ReadCleanReq_hits::total 1015029 # number of ReadCleanReq hits
1791 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131048 # number of ReadSharedReq hits
1792 system.cpu1.l2cache.ReadSharedReq_hits::total 131048 # number of ReadSharedReq hits
1793 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33040 # number of demand (read+write) hits
1794 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2583 # number of demand (read+write) hits
1795 system.cpu1.l2cache.demand_hits::cpu1.inst 1015029 # number of demand (read+write) hits
1796 system.cpu1.l2cache.demand_hits::cpu1.data 168780 # number of demand (read+write) hits
1797 system.cpu1.l2cache.demand_hits::total 1219432 # number of demand (read+write) hits
1798 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33040 # number of overall hits
1799 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2583 # number of overall hits
1800 system.cpu1.l2cache.overall_hits::cpu1.inst 1015029 # number of overall hits
1801 system.cpu1.l2cache.overall_hits::cpu1.data 168780 # number of overall hits
1802 system.cpu1.l2cache.overall_hits::total 1219432 # number of overall hits
1803 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 727 # number of ReadReq misses
1804 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses
1805 system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses
1806 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29373 # number of UpgradeReq misses
1807 system.cpu1.l2cache.UpgradeReq_misses::total 29373 # number of UpgradeReq misses
1808 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22436 # number of SCUpgradeReq misses
1809 system.cpu1.l2cache.SCUpgradeReq_misses::total 22436 # number of SCUpgradeReq misses
1810 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
1811 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1812 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36088 # number of ReadExReq misses
1813 system.cpu1.l2cache.ReadExReq_misses::total 36088 # number of ReadExReq misses
1814 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27608 # number of ReadCleanReq misses
1815 system.cpu1.l2cache.ReadCleanReq_misses::total 27608 # number of ReadCleanReq misses
1816 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73984 # number of ReadSharedReq misses
1817 system.cpu1.l2cache.ReadSharedReq_misses::total 73984 # number of ReadSharedReq misses
1818 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 727 # number of demand (read+write) misses
1819 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses
1820 system.cpu1.l2cache.demand_misses::cpu1.inst 27608 # number of demand (read+write) misses
1821 system.cpu1.l2cache.demand_misses::cpu1.data 110072 # number of demand (read+write) misses
1822 system.cpu1.l2cache.demand_misses::total 138628 # number of demand (read+write) misses
1823 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 727 # number of overall misses
1824 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses
1825 system.cpu1.l2cache.overall_misses::cpu1.inst 27608 # number of overall misses
1826 system.cpu1.l2cache.overall_misses::cpu1.data 110072 # number of overall misses
1827 system.cpu1.l2cache.overall_misses::total 138628 # number of overall misses
1828 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 18603000 # number of ReadReq miss cycles
1829 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4457500 # number of ReadReq miss cycles
1830 system.cpu1.l2cache.ReadReq_miss_latency::total 23060500 # number of ReadReq miss cycles
1831 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 554124000 # number of UpgradeReq miss cycles
1832 system.cpu1.l2cache.UpgradeReq_miss_latency::total 554124000 # number of UpgradeReq miss cycles
1833 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449909000 # number of SCUpgradeReq miss cycles
1834 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449909000 # number of SCUpgradeReq miss cycles
1835 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 652000 # number of SCUpgradeFailReq miss cycles
1836 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 652000 # number of SCUpgradeFailReq miss cycles
1837 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418232500 # number of ReadExReq miss cycles
1838 system.cpu1.l2cache.ReadExReq_miss_latency::total 1418232500 # number of ReadExReq miss cycles
1839 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071283000 # number of ReadCleanReq miss cycles
1840 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071283000 # number of ReadCleanReq miss cycles
1841 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1763586495 # number of ReadSharedReq miss cycles
1842 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1763586495 # number of ReadSharedReq miss cycles
1843 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 18603000 # number of demand (read+write) miss cycles
1844 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4457500 # number of demand (read+write) miss cycles
1845 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071283000 # number of demand (read+write) miss cycles
1846 system.cpu1.l2cache.demand_miss_latency::cpu1.data 3181818995 # number of demand (read+write) miss cycles
1847 system.cpu1.l2cache.demand_miss_latency::total 4276162495 # number of demand (read+write) miss cycles
1848 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 18603000 # number of overall miss cycles
1849 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4457500 # number of overall miss cycles
1850 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071283000 # number of overall miss cycles
1851 system.cpu1.l2cache.overall_miss_latency::cpu1.data 3181818995 # number of overall miss cycles
1852 system.cpu1.l2cache.overall_miss_latency::total 4276162495 # number of overall miss cycles
1853 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33767 # number of ReadReq accesses(hits+misses)
1854 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2804 # number of ReadReq accesses(hits+misses)
1855 system.cpu1.l2cache.ReadReq_accesses::total 36571 # number of ReadReq accesses(hits+misses)
1856 system.cpu1.l2cache.Writeback_accesses::writebacks 138377 # number of Writeback accesses(hits+misses)
1857 system.cpu1.l2cache.Writeback_accesses::total 138377 # number of Writeback accesses(hits+misses)
1858 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31415 # number of UpgradeReq accesses(hits+misses)
1859 system.cpu1.l2cache.UpgradeReq_accesses::total 31415 # number of UpgradeReq accesses(hits+misses)
1860 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23448 # number of SCUpgradeReq accesses(hits+misses)
1861 system.cpu1.l2cache.SCUpgradeReq_accesses::total 23448 # number of SCUpgradeReq accesses(hits+misses)
1862 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1863 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1864 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73820 # number of ReadExReq accesses(hits+misses)
1865 system.cpu1.l2cache.ReadExReq_accesses::total 73820 # number of ReadExReq accesses(hits+misses)
1866 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1042637 # number of ReadCleanReq accesses(hits+misses)
1867 system.cpu1.l2cache.ReadCleanReq_accesses::total 1042637 # number of ReadCleanReq accesses(hits+misses)
1868 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205032 # number of ReadSharedReq accesses(hits+misses)
1869 system.cpu1.l2cache.ReadSharedReq_accesses::total 205032 # number of ReadSharedReq accesses(hits+misses)
1870 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33767 # number of demand (read+write) accesses
1871 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2804 # number of demand (read+write) accesses
1872 system.cpu1.l2cache.demand_accesses::cpu1.inst 1042637 # number of demand (read+write) accesses
1873 system.cpu1.l2cache.demand_accesses::cpu1.data 278852 # number of demand (read+write) accesses
1874 system.cpu1.l2cache.demand_accesses::total 1358060 # number of demand (read+write) accesses
1875 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33767 # number of overall (read+write) accesses
1876 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2804 # number of overall (read+write) accesses
1877 system.cpu1.l2cache.overall_accesses::cpu1.inst 1042637 # number of overall (read+write) accesses
1878 system.cpu1.l2cache.overall_accesses::cpu1.data 278852 # number of overall (read+write) accesses
1879 system.cpu1.l2cache.overall_accesses::total 1358060 # number of overall (read+write) accesses
1880 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for ReadReq accesses
1881 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078816 # miss rate for ReadReq accesses
1882 system.cpu1.l2cache.ReadReq_miss_rate::total 0.025922 # miss rate for ReadReq accesses
1883 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.934999 # miss rate for UpgradeReq accesses
1884 system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.934999 # miss rate for UpgradeReq accesses
1885 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.956841 # miss rate for SCUpgradeReq accesses
1886 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.956841 # miss rate for SCUpgradeReq accesses
1887 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1888 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1889 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.488865 # miss rate for ReadExReq accesses
1890 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.488865 # miss rate for ReadExReq accesses
1891 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026479 # miss rate for ReadCleanReq accesses
1892 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026479 # miss rate for ReadCleanReq accesses
1893 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360841 # miss rate for ReadSharedReq accesses
1894 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360841 # miss rate for ReadSharedReq accesses
1895 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for demand accesses
1896 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078816 # miss rate for demand accesses
1897 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026479 # miss rate for demand accesses
1898 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.394733 # miss rate for demand accesses
1899 system.cpu1.l2cache.demand_miss_rate::total 0.102078 # miss rate for demand accesses
1900 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for overall accesses
1901 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078816 # miss rate for overall accesses
1902 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026479 # miss rate for overall accesses
1903 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.394733 # miss rate for overall accesses
1904 system.cpu1.l2cache.overall_miss_rate::total 0.102078 # miss rate for overall accesses
1905 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average ReadReq miss latency
1906 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258 # average ReadReq miss latency
1907 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941 # average ReadReq miss latency
1908 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176 # average UpgradeReq miss latency
1909 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176 # average UpgradeReq miss latency
1910 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186 # average SCUpgradeReq miss latency
1911 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186 # average SCUpgradeReq miss latency
1912 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 326000 # average SCUpgradeFailReq miss latency
1913 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326000 # average SCUpgradeFailReq miss latency
1914 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310 # average ReadExReq miss latency
1915 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310 # average ReadExReq miss latency
1916 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100 # average ReadCleanReq miss latency
1917 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100 # average ReadCleanReq miss latency
1918 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966 # average ReadSharedReq miss latency
1919 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966 # average ReadSharedReq miss latency
1920 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
1921 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
1922 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
1923 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
1924 system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676 # average overall miss latency
1925 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
1926 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
1927 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
1928 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
1929 system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676 # average overall miss latency
1930 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1931 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1932 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1933 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1934 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1935 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1936 system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1937 system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1938 system.cpu1.l2cache.writebacks::writebacks 36799 # number of writebacks
1939 system.cpu1.l2cache.writebacks::total 36799 # number of writebacks
1940 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 302 # number of ReadExReq MSHR hits
1941 system.cpu1.l2cache.ReadExReq_mshr_hits::total 302 # number of ReadExReq MSHR hits
1942 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 26 # number of ReadCleanReq MSHR hits
1943 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
1944 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 134 # number of ReadSharedReq MSHR hits
1945 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 134 # number of ReadSharedReq MSHR hits
1946 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits
1947 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 436 # number of demand (read+write) MSHR hits
1948 system.cpu1.l2cache.demand_mshr_hits::total 462 # number of demand (read+write) MSHR hits
1949 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits
1950 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 436 # number of overall MSHR hits
1951 system.cpu1.l2cache.overall_mshr_hits::total 462 # number of overall MSHR hits
1952 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 727 # number of ReadReq MSHR misses
1953 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses
1954 system.cpu1.l2cache.ReadReq_mshr_misses::total 948 # number of ReadReq MSHR misses
1955 system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3205 # number of CleanEvict MSHR misses
1956 system.cpu1.l2cache.CleanEvict_mshr_misses::total 3205 # number of CleanEvict MSHR misses
1957 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of HardPFReq MSHR misses
1958 system.cpu1.l2cache.HardPFReq_mshr_misses::total 35196 # number of HardPFReq MSHR misses
1959 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29373 # number of UpgradeReq MSHR misses
1960 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29373 # number of UpgradeReq MSHR misses
1961 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22436 # number of SCUpgradeReq MSHR misses
1962 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22436 # number of SCUpgradeReq MSHR misses
1963 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
1964 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1965 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35786 # number of ReadExReq MSHR misses
1966 system.cpu1.l2cache.ReadExReq_mshr_misses::total 35786 # number of ReadExReq MSHR misses
1967 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27582 # number of ReadCleanReq MSHR misses
1968 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27582 # number of ReadCleanReq MSHR misses
1969 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73850 # number of ReadSharedReq MSHR misses
1970 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73850 # number of ReadSharedReq MSHR misses
1971 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 727 # number of demand (read+write) MSHR misses
1972 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses
1973 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27582 # number of demand (read+write) MSHR misses
1974 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109636 # number of demand (read+write) MSHR misses
1975 system.cpu1.l2cache.demand_mshr_misses::total 138166 # number of demand (read+write) MSHR misses
1976 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 727 # number of overall MSHR misses
1977 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses
1978 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27582 # number of overall MSHR misses
1979 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109636 # number of overall MSHR misses
1980 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of overall MSHR misses
1981 system.cpu1.l2cache.overall_mshr_misses::total 173362 # number of overall MSHR misses
1982 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
1983 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
1984 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17241 # number of ReadReq MSHR uncacheable
1985 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
1986 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
1987 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
1988 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
1989 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31646 # number of overall MSHR uncacheable misses
1990 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of ReadReq MSHR miss cycles
1991 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3131500 # number of ReadReq MSHR miss cycles
1992 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17372500 # number of ReadReq MSHR miss cycles
1993 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of HardPFReq MSHR miss cycles
1994 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1238467331 # number of HardPFReq MSHR miss cycles
1995 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 502709499 # number of UpgradeReq MSHR miss cycles
1996 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 502709499 # number of UpgradeReq MSHR miss cycles
1997 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348029000 # number of SCUpgradeReq MSHR miss cycles
1998 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348029000 # number of SCUpgradeReq MSHR miss cycles
1999 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 574000 # number of SCUpgradeFailReq MSHR miss cycles
2000 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 574000 # number of SCUpgradeFailReq MSHR miss cycles
2001 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1167759000 # number of ReadExReq MSHR miss cycles
2002 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1167759000 # number of ReadExReq MSHR miss cycles
2003 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 904893000 # number of ReadCleanReq MSHR miss cycles
2004 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 904893000 # number of ReadCleanReq MSHR miss cycles
2005 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1316095995 # number of ReadSharedReq MSHR miss cycles
2006 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1316095995 # number of ReadSharedReq MSHR miss cycles
2007 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of demand (read+write) MSHR miss cycles
2008 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3131500 # number of demand (read+write) MSHR miss cycles
2009 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 904893000 # number of demand (read+write) MSHR miss cycles
2010 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483854995 # number of demand (read+write) MSHR miss cycles
2011 system.cpu1.l2cache.demand_mshr_miss_latency::total 3406120495 # number of demand (read+write) MSHR miss cycles
2012 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of overall MSHR miss cycles
2013 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3131500 # number of overall MSHR miss cycles
2014 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 904893000 # number of overall MSHR miss cycles
2015 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483854995 # number of overall MSHR miss cycles
2016 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of overall MSHR miss cycles
2017 system.cpu1.l2cache.overall_mshr_miss_latency::total 4644587826 # number of overall MSHR miss cycles
2018 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9222000 # number of ReadReq MSHR uncacheable cycles
2019 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2797805500 # number of ReadReq MSHR uncacheable cycles
2020 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807027500 # number of ReadReq MSHR uncacheable cycles
2021 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338455000 # number of WriteReq MSHR uncacheable cycles
2022 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338455000 # number of WriteReq MSHR uncacheable cycles
2023 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9222000 # number of overall MSHR uncacheable cycles
2024 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5136260500 # number of overall MSHR uncacheable cycles
2025 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5145482500 # number of overall MSHR uncacheable cycles
2026 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for ReadReq accesses
2027 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for ReadReq accesses
2028 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025922 # mshr miss rate for ReadReq accesses
2029 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2030 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2031 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2032 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2033 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.934999 # mshr miss rate for UpgradeReq accesses
2034 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.934999 # mshr miss rate for UpgradeReq accesses
2035 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956841 # mshr miss rate for SCUpgradeReq accesses
2036 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.956841 # mshr miss rate for SCUpgradeReq accesses
2037 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2038 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2039 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.484774 # mshr miss rate for ReadExReq accesses
2040 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.484774 # mshr miss rate for ReadExReq accesses
2041 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for ReadCleanReq accesses
2042 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026454 # mshr miss rate for ReadCleanReq accesses
2043 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.360188 # mshr miss rate for ReadSharedReq accesses
2044 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.360188 # mshr miss rate for ReadSharedReq accesses
2045 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for demand accesses
2046 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for demand accesses
2047 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for demand accesses
2048 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for demand accesses
2049 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101738 # mshr miss rate for demand accesses
2050 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for overall accesses
2051 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for overall accesses
2052 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for overall accesses
2053 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for overall accesses
2054 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2055 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127654 # mshr miss rate for overall accesses
2056 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average ReadReq mshr miss latency
2057 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average ReadReq mshr miss latency
2058 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941 # average ReadReq mshr miss latency
2059 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average HardPFReq mshr miss latency
2060 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600 # average HardPFReq mshr miss latency
2061 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114 # average UpgradeReq mshr miss latency
2062 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114 # average UpgradeReq mshr miss latency
2063 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802 # average SCUpgradeReq mshr miss latency
2064 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802 # average SCUpgradeReq mshr miss latency
2065 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 287000 # average SCUpgradeFailReq mshr miss latency
2066 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 287000 # average SCUpgradeFailReq mshr miss latency
2067 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491 # average ReadExReq mshr miss latency
2068 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491 # average ReadExReq mshr miss latency
2069 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average ReadCleanReq mshr miss latency
2070 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375 # average ReadCleanReq mshr miss latency
2071 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078 # average ReadSharedReq mshr miss latency
2072 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078 # average ReadSharedReq mshr miss latency
2073 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
2074 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
2075 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
2076 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
2077 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262 # average overall mshr miss latency
2078 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
2079 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
2080 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
2081 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
2082 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average overall mshr miss latency
2083 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133 # average overall mshr miss latency
2084 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average ReadReq mshr uncacheable latency
2085 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136 # average ReadReq mshr uncacheable latency
2086 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846 # average ReadReq mshr uncacheable latency
2087 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548 # average WriteReq mshr uncacheable latency
2088 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548 # average WriteReq mshr uncacheable latency
2089 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average overall mshr uncacheable latency
2090 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201 # average overall mshr uncacheable latency
2091 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708 # average overall mshr uncacheable latency
2092 system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2093 system.cpu1.toL2Bus.trans_dist::ReadReq 81005 # Transaction distribution
2094 system.cpu1.toL2Bus.trans_dist::ReadResp 1348099 # Transaction distribution
2095 system.cpu1.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
2096 system.cpu1.toL2Bus.trans_dist::WriteResp 14405 # Transaction distribution
2097 system.cpu1.toL2Bus.trans_dist::Writeback 510462 # Transaction distribution
2098 system.cpu1.toL2Bus.trans_dist::CleanEvict 1265020 # Transaction distribution
2099 system.cpu1.toL2Bus.trans_dist::HardPFReq 43516 # Transaction distribution
2100 system.cpu1.toL2Bus.trans_dist::UpgradeReq 77320 # Transaction distribution
2101 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42972 # Transaction distribution
2102 system.cpu1.toL2Bus.trans_dist::UpgradeResp 89288 # Transaction distribution
2103 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
2104 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
2105 system.cpu1.toL2Bus.trans_dist::ReadExReq 97251 # Transaction distribution
2106 system.cpu1.toL2Bus.trans_dist::ReadExResp 79776 # Transaction distribution
2107 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1042637 # Transaction distribution
2108 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 559861 # Transaction distribution
2109 system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2110 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3108261 # Packet count per connected master and slave (bytes)
2111 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1040223 # Packet count per connected master and slave (bytes)
2112 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7202 # Packet count per connected master and slave (bytes)
2113 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71706 # Packet count per connected master and slave (bytes)
2114 system.cpu1.toL2Bus.pkt_count::total 4227392 # Packet count per connected master and slave (bytes)
2115 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66736000 # Cumulative packet size per connected master and slave (bytes)
2116 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29812791 # Cumulative packet size per connected master and slave (bytes)
2117 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11216 # Cumulative packet size per connected master and slave (bytes)
2118 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135068 # Cumulative packet size per connected master and slave (bytes)
2119 system.cpu1.toL2Bus.pkt_size::total 96695075 # Cumulative packet size per connected master and slave (bytes)
2120 system.cpu1.toL2Bus.snoops 1172897 # Total snoops (count)
2121 system.cpu1.toL2Bus.snoop_fanout::samples 3809713 # Request fanout histogram
2122 system.cpu1.toL2Bus.snoop_fanout::mean 1.296141 # Request fanout histogram
2123 system.cpu1.toL2Bus.snoop_fanout::stdev 0.456554 # Request fanout histogram
2124 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2125 system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2126 system.cpu1.toL2Bus.snoop_fanout::1 2681500 70.39% 70.39% # Request fanout histogram
2127 system.cpu1.toL2Bus.snoop_fanout::2 1128213 29.61% 100.00% # Request fanout histogram
2128 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2129 system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2130 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2131 system.cpu1.toL2Bus.snoop_fanout::total 3809713 # Request fanout histogram
2132 system.cpu1.toL2Bus.reqLayer0.occupancy 1507501992 # Layer occupancy (ticks)
2133 system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2134 system.cpu1.toL2Bus.snoopLayer0.occupancy 87443999 # Layer occupancy (ticks)
2135 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2136 system.cpu1.toL2Bus.respLayer0.occupancy 1564193862 # Layer occupancy (ticks)
2137 system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2138 system.cpu1.toL2Bus.respLayer1.occupancy 470956198 # Layer occupancy (ticks)
2139 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2140 system.cpu1.toL2Bus.respLayer2.occupancy 4398499 # Layer occupancy (ticks)
2141 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2142 system.cpu1.toL2Bus.respLayer3.occupancy 37948980 # Layer occupancy (ticks)
2143 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2144 system.iobus.trans_dist::ReadReq 31013 # Transaction distribution
2145 system.iobus.trans_dist::ReadResp 31013 # Transaction distribution
2146 system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2147 system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2148 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2149 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2150 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2151 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2152 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2153 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
2154 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2155 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2156 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2157 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2158 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2159 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2160 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2161 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2162 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2163 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2164 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2165 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2166 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2167 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2168 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2169 system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes)
2170 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
2171 system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
2172 system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
2173 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2174 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2175 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2176 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2177 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2178 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
2179 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2180 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2181 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2182 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2183 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2184 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2185 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2186 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2187 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2188 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2189 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2190 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2191 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2192 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2193 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2194 system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
2195 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
2196 system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
2197 system.iobus.pkt_size::total 2484073 # Cumulative packet size per connected master and slave (bytes)
2198 system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
2199 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2200 system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2201 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2202 system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2203 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2204 system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2205 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2206 system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2207 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2208 system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
2209 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2210 system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2211 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2212 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2213 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2214 system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2215 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2216 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
2217 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2218 system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
2219 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2220 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2221 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2222 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
2223 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2224 system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
2225 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2226 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
2227 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2228 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
2229 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2230 system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2231 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2232 system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2233 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2234 system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2235 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2236 system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2237 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2238 system.iobus.reqLayer27.occupancy 187545199 # Layer occupancy (ticks)
2239 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2240 system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2241 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2242 system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks)
2243 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2244 system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks)
2245 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2246 system.iocache.tags.replacements 36462 # number of replacements
2247 system.iocache.tags.tagsinuse 14.479963 # Cycle average of tags in use
2248 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2249 system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks.
2250 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2251 system.iocache.tags.warmup_cycle 270370198000 # Cycle when the warmup percentage was hit.
2252 system.iocache.tags.occ_blocks::realview.ide 14.479963 # Average occupied blocks per requestor
2253 system.iocache.tags.occ_percent::realview.ide 0.904998 # Average percentage of cache occupancy
2254 system.iocache.tags.occ_percent::total 0.904998 # Average percentage of cache occupancy
2255 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2256 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2257 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2258 system.iocache.tags.tag_accesses 328320 # Number of tag accesses
2259 system.iocache.tags.data_accesses 328320 # Number of data accesses
2260 system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses
2261 system.iocache.ReadReq_misses::total 256 # number of ReadReq misses
2262 system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2263 system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2264 system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses
2265 system.iocache.demand_misses::total 256 # number of demand (read+write) misses
2266 system.iocache.overall_misses::realview.ide 256 # number of overall misses
2267 system.iocache.overall_misses::total 256 # number of overall misses
2268 system.iocache.ReadReq_miss_latency::realview.ide 32688877 # number of ReadReq miss cycles
2269 system.iocache.ReadReq_miss_latency::total 32688877 # number of ReadReq miss cycles
2270 system.iocache.WriteLineReq_miss_latency::realview.ide 4277206322 # number of WriteLineReq miss cycles
2271 system.iocache.WriteLineReq_miss_latency::total 4277206322 # number of WriteLineReq miss cycles
2272 system.iocache.demand_miss_latency::realview.ide 32688877 # number of demand (read+write) miss cycles
2273 system.iocache.demand_miss_latency::total 32688877 # number of demand (read+write) miss cycles
2274 system.iocache.overall_miss_latency::realview.ide 32688877 # number of overall miss cycles
2275 system.iocache.overall_miss_latency::total 32688877 # number of overall miss cycles
2276 system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses)
2277 system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses)
2278 system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2279 system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2280 system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses
2281 system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses
2282 system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses
2283 system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses
2284 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2285 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2286 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2287 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2288 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2289 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2290 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2291 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2292 system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781 # average ReadReq miss latency
2293 system.iocache.ReadReq_avg_miss_latency::total 127690.925781 # average ReadReq miss latency
2294 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953 # average WriteLineReq miss latency
2295 system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953 # average WriteLineReq miss latency
2296 system.iocache.demand_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
2297 system.iocache.demand_avg_miss_latency::total 127690.925781 # average overall miss latency
2298 system.iocache.overall_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
2299 system.iocache.overall_avg_miss_latency::total 127690.925781 # average overall miss latency
2300 system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
2301 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2302 system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2303 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2304 system.iocache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked
2305 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2306 system.iocache.fast_writes 0 # number of fast writes performed
2307 system.iocache.cache_copies 0 # number of cache copies performed
2308 system.iocache.writebacks::writebacks 36206 # number of writebacks
2309 system.iocache.writebacks::total 36206 # number of writebacks
2310 system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses
2311 system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses
2312 system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2313 system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2314 system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses
2315 system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
2316 system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses
2317 system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses
2318 system.iocache.ReadReq_mshr_miss_latency::realview.ide 19888877 # number of ReadReq MSHR miss cycles
2319 system.iocache.ReadReq_mshr_miss_latency::total 19888877 # number of ReadReq MSHR miss cycles
2320 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466006322 # number of WriteLineReq MSHR miss cycles
2321 system.iocache.WriteLineReq_mshr_miss_latency::total 2466006322 # number of WriteLineReq MSHR miss cycles
2322 system.iocache.demand_mshr_miss_latency::realview.ide 19888877 # number of demand (read+write) MSHR miss cycles
2323 system.iocache.demand_mshr_miss_latency::total 19888877 # number of demand (read+write) MSHR miss cycles
2324 system.iocache.overall_mshr_miss_latency::realview.ide 19888877 # number of overall MSHR miss cycles
2325 system.iocache.overall_mshr_miss_latency::total 19888877 # number of overall MSHR miss cycles
2326 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2327 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2328 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2329 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2330 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2331 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2332 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2333 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2334 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781 # average ReadReq mshr miss latency
2335 system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781 # average ReadReq mshr miss latency
2336 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953 # average WriteLineReq mshr miss latency
2337 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953 # average WriteLineReq mshr miss latency
2338 system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
2339 system.iocache.demand_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
2340 system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
2341 system.iocache.overall_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
2342 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2343 system.l2c.tags.replacements 134724 # number of replacements
2344 system.l2c.tags.tagsinuse 64068.233504 # Cycle average of tags in use
2345 system.l2c.tags.total_refs 443602 # Total number of references to valid blocks.
2346 system.l2c.tags.sampled_refs 199053 # Sample count of references to valid blocks.
2347 system.l2c.tags.avg_refs 2.228562 # Average number of references to valid blocks.
2348 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2349 system.l2c.tags.occ_blocks::writebacks 12835.902941 # Average occupied blocks per requestor
2350 system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.531822 # Average occupied blocks per requestor
2351 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025215 # Average occupied blocks per requestor
2352 system.l2c.tags.occ_blocks::cpu0.inst 7257.127456 # Average occupied blocks per requestor
2353 system.l2c.tags.occ_blocks::cpu0.data 2101.817094 # Average occupied blocks per requestor
2354 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605 # Average occupied blocks per requestor
2355 system.l2c.tags.occ_blocks::cpu1.dtb.walker 30.126345 # Average occupied blocks per requestor
2356 system.l2c.tags.occ_blocks::cpu1.inst 4045.876721 # Average occupied blocks per requestor
2357 system.l2c.tags.occ_blocks::cpu1.data 1535.093827 # Average occupied blocks per requestor
2358 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4184.707478 # Average occupied blocks per requestor
2359 system.l2c.tags.occ_percent::writebacks 0.195860 # Average percentage of cache occupancy
2360 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001046 # Average percentage of cache occupancy
2361 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2362 system.l2c.tags.occ_percent::cpu0.inst 0.110735 # Average percentage of cache occupancy
2363 system.l2c.tags.occ_percent::cpu0.data 0.032071 # Average percentage of cache occupancy
2364 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.488419 # Average percentage of cache occupancy
2365 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000460 # Average percentage of cache occupancy
2366 system.l2c.tags.occ_percent::cpu1.inst 0.061735 # Average percentage of cache occupancy
2367 system.l2c.tags.occ_percent::cpu1.data 0.023424 # Average percentage of cache occupancy
2368 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.063854 # Average percentage of cache occupancy
2369 system.l2c.tags.occ_percent::total 0.977604 # Average percentage of cache occupancy
2370 system.l2c.tags.occ_task_id_blocks::1022 29296 # Occupied blocks per task id
2371 system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id
2372 system.l2c.tags.occ_task_id_blocks::1024 34966 # Occupied blocks per task id
2373 system.l2c.tags.age_task_id_blocks_1022::2 113 # Occupied blocks per task id
2374 system.l2c.tags.age_task_id_blocks_1022::3 5383 # Occupied blocks per task id
2375 system.l2c.tags.age_task_id_blocks_1022::4 23800 # Occupied blocks per task id
2376 system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2377 system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id
2378 system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
2379 system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
2380 system.l2c.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id
2381 system.l2c.tags.age_task_id_blocks_1024::3 2923 # Occupied blocks per task id
2382 system.l2c.tags.age_task_id_blocks_1024::4 31711 # Occupied blocks per task id
2383 system.l2c.tags.occ_task_id_percent::1022 0.447021 # Percentage of cache occupancy per task id
2384 system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id
2385 system.l2c.tags.occ_task_id_percent::1024 0.533539 # Percentage of cache occupancy per task id
2386 system.l2c.tags.tag_accesses 5827626 # Number of tag accesses
2387 system.l2c.tags.data_accesses 5827626 # Number of data accesses
2388 system.l2c.Writeback_hits::writebacks 232709 # number of Writeback hits
2389 system.l2c.Writeback_hits::total 232709 # number of Writeback hits
2390 system.l2c.UpgradeReq_hits::cpu0.data 3025 # number of UpgradeReq hits
2391 system.l2c.UpgradeReq_hits::cpu1.data 939 # number of UpgradeReq hits
2392 system.l2c.UpgradeReq_hits::total 3964 # number of UpgradeReq hits
2393 system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits
2394 system.l2c.SCUpgradeReq_hits::cpu1.data 83 # number of SCUpgradeReq hits
2395 system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits
2396 system.l2c.ReadExReq_hits::cpu0.data 4055 # number of ReadExReq hits
2397 system.l2c.ReadExReq_hits::cpu1.data 2183 # number of ReadExReq hits
2398 system.l2c.ReadExReq_hits::total 6238 # number of ReadExReq hits
2399 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 387 # number of ReadSharedReq hits
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2401 system.l2c.ReadSharedReq_hits::cpu0.inst 44381 # number of ReadSharedReq hits
2402 system.l2c.ReadSharedReq_hits::cpu0.data 47292 # number of ReadSharedReq hits
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2404 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 171 # number of ReadSharedReq hits
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2406 system.l2c.ReadSharedReq_hits::cpu1.inst 21681 # number of ReadSharedReq hits
2407 system.l2c.ReadSharedReq_hits::cpu1.data 11241 # number of ReadSharedReq hits
2408 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8230 # number of ReadSharedReq hits
2409 system.l2c.ReadSharedReq_hits::total 179657 # number of ReadSharedReq hits
2410 system.l2c.demand_hits::cpu0.dtb.walker 387 # number of demand (read+write) hits
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2412 system.l2c.demand_hits::cpu0.inst 44381 # number of demand (read+write) hits
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2415 system.l2c.demand_hits::cpu1.dtb.walker 171 # number of demand (read+write) hits
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2417 system.l2c.demand_hits::cpu1.inst 21681 # number of demand (read+write) hits
2418 system.l2c.demand_hits::cpu1.data 13424 # number of demand (read+write) hits
2419 system.l2c.demand_hits::cpu1.l2cache.prefetcher 8230 # number of demand (read+write) hits
2420 system.l2c.demand_hits::total 185895 # number of demand (read+write) hits
2421 system.l2c.overall_hits::cpu0.dtb.walker 387 # number of overall hits
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2423 system.l2c.overall_hits::cpu0.inst 44381 # number of overall hits
2424 system.l2c.overall_hits::cpu0.data 51347 # number of overall hits
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2426 system.l2c.overall_hits::cpu1.dtb.walker 171 # number of overall hits
2427 system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
2428 system.l2c.overall_hits::cpu1.inst 21681 # number of overall hits
2429 system.l2c.overall_hits::cpu1.data 13424 # number of overall hits
2430 system.l2c.overall_hits::cpu1.l2cache.prefetcher 8230 # number of overall hits
2431 system.l2c.overall_hits::total 185895 # number of overall hits
2432 system.l2c.UpgradeReq_misses::cpu0.data 8753 # number of UpgradeReq misses
2433 system.l2c.UpgradeReq_misses::cpu1.data 4074 # number of UpgradeReq misses
2434 system.l2c.UpgradeReq_misses::total 12827 # number of UpgradeReq misses
2435 system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses
2436 system.l2c.SCUpgradeReq_misses::cpu1.data 1213 # number of SCUpgradeReq misses
2437 system.l2c.SCUpgradeReq_misses::total 2010 # number of SCUpgradeReq misses
2438 system.l2c.ReadExReq_misses::cpu0.data 10969 # number of ReadExReq misses
2439 system.l2c.ReadExReq_misses::cpu1.data 8454 # number of ReadExReq misses
2440 system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses
2441 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 121 # number of ReadSharedReq misses
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2443 system.l2c.ReadSharedReq_misses::cpu0.inst 19546 # number of ReadSharedReq misses
2444 system.l2c.ReadSharedReq_misses::cpu0.data 8542 # number of ReadSharedReq misses
2445 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq misses
2446 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 43 # number of ReadSharedReq misses
2447 system.l2c.ReadSharedReq_misses::cpu1.inst 5890 # number of ReadSharedReq misses
2448 system.l2c.ReadSharedReq_misses::cpu1.data 2696 # number of ReadSharedReq misses
2449 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq misses
2450 system.l2c.ReadSharedReq_misses::total 174531 # number of ReadSharedReq misses
2451 system.l2c.demand_misses::cpu0.dtb.walker 121 # number of demand (read+write) misses
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2453 system.l2c.demand_misses::cpu0.inst 19546 # number of demand (read+write) misses
2454 system.l2c.demand_misses::cpu0.data 19511 # number of demand (read+write) misses
2455 system.l2c.demand_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) misses
2456 system.l2c.demand_misses::cpu1.dtb.walker 43 # number of demand (read+write) misses
2457 system.l2c.demand_misses::cpu1.inst 5890 # number of demand (read+write) misses
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2459 system.l2c.demand_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) misses
2460 system.l2c.demand_misses::total 193954 # number of demand (read+write) misses
2461 system.l2c.overall_misses::cpu0.dtb.walker 121 # number of overall misses
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2463 system.l2c.overall_misses::cpu0.inst 19546 # number of overall misses
2464 system.l2c.overall_misses::cpu0.data 19511 # number of overall misses
2465 system.l2c.overall_misses::cpu0.l2cache.prefetcher 128715 # number of overall misses
2466 system.l2c.overall_misses::cpu1.dtb.walker 43 # number of overall misses
2467 system.l2c.overall_misses::cpu1.inst 5890 # number of overall misses
2468 system.l2c.overall_misses::cpu1.data 11150 # number of overall misses
2469 system.l2c.overall_misses::cpu1.l2cache.prefetcher 8977 # number of overall misses
2470 system.l2c.overall_misses::total 193954 # number of overall misses
2471 system.l2c.UpgradeReq_miss_latency::cpu0.data 9167000 # number of UpgradeReq miss cycles
2472 system.l2c.UpgradeReq_miss_latency::cpu1.data 5104000 # number of UpgradeReq miss cycles
2473 system.l2c.UpgradeReq_miss_latency::total 14271000 # number of UpgradeReq miss cycles
2474 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1330000 # number of SCUpgradeReq miss cycles
2475 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1451500 # number of SCUpgradeReq miss cycles
2476 system.l2c.SCUpgradeReq_miss_latency::total 2781500 # number of SCUpgradeReq miss cycles
2477 system.l2c.ReadExReq_miss_latency::cpu0.data 1087997000 # number of ReadExReq miss cycles
2478 system.l2c.ReadExReq_miss_latency::cpu1.data 696148000 # number of ReadExReq miss cycles
2479 system.l2c.ReadExReq_miss_latency::total 1784145000 # number of ReadExReq miss cycles
2480 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10392000 # number of ReadSharedReq miss cycles
2481 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles
2482 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1558395000 # number of ReadSharedReq miss cycles
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2484 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13067901493 # number of ReadSharedReq miss cycles
2485 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3962000 # number of ReadSharedReq miss cycles
2486 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483846500 # number of ReadSharedReq miss cycles
2487 system.l2c.ReadSharedReq_miss_latency::cpu1.data 240245000 # number of ReadSharedReq miss cycles
2488 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of ReadSharedReq miss cycles
2489 system.l2c.ReadSharedReq_miss_latency::total 17184117504 # number of ReadSharedReq miss cycles
2490 system.l2c.demand_miss_latency::cpu0.dtb.walker 10392000 # number of demand (read+write) miss cycles
2491 system.l2c.demand_miss_latency::cpu0.itb.walker 303000 # number of demand (read+write) miss cycles
2492 system.l2c.demand_miss_latency::cpu0.inst 1558395000 # number of demand (read+write) miss cycles
2493 system.l2c.demand_miss_latency::cpu0.data 1837220000 # number of demand (read+write) miss cycles
2494 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13067901493 # number of demand (read+write) miss cycles
2495 system.l2c.demand_miss_latency::cpu1.dtb.walker 3962000 # number of demand (read+write) miss cycles
2496 system.l2c.demand_miss_latency::cpu1.inst 483846500 # number of demand (read+write) miss cycles
2497 system.l2c.demand_miss_latency::cpu1.data 936393000 # number of demand (read+write) miss cycles
2498 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of demand (read+write) miss cycles
2499 system.l2c.demand_miss_latency::total 18968262504 # number of demand (read+write) miss cycles
2500 system.l2c.overall_miss_latency::cpu0.dtb.walker 10392000 # number of overall miss cycles
2501 system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles
2502 system.l2c.overall_miss_latency::cpu0.inst 1558395000 # number of overall miss cycles
2503 system.l2c.overall_miss_latency::cpu0.data 1837220000 # number of overall miss cycles
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2505 system.l2c.overall_miss_latency::cpu1.dtb.walker 3962000 # number of overall miss cycles
2506 system.l2c.overall_miss_latency::cpu1.inst 483846500 # number of overall miss cycles
2507 system.l2c.overall_miss_latency::cpu1.data 936393000 # number of overall miss cycles
2508 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of overall miss cycles
2509 system.l2c.overall_miss_latency::total 18968262504 # number of overall miss cycles
2510 system.l2c.Writeback_accesses::writebacks 232709 # number of Writeback accesses(hits+misses)
2511 system.l2c.Writeback_accesses::total 232709 # number of Writeback accesses(hits+misses)
2512 system.l2c.UpgradeReq_accesses::cpu0.data 11778 # number of UpgradeReq accesses(hits+misses)
2513 system.l2c.UpgradeReq_accesses::cpu1.data 5013 # number of UpgradeReq accesses(hits+misses)
2514 system.l2c.UpgradeReq_accesses::total 16791 # number of UpgradeReq accesses(hits+misses)
2515 system.l2c.SCUpgradeReq_accesses::cpu0.data 1054 # number of SCUpgradeReq accesses(hits+misses)
2516 system.l2c.SCUpgradeReq_accesses::cpu1.data 1296 # number of SCUpgradeReq accesses(hits+misses)
2517 system.l2c.SCUpgradeReq_accesses::total 2350 # number of SCUpgradeReq accesses(hits+misses)
2518 system.l2c.ReadExReq_accesses::cpu0.data 15024 # number of ReadExReq accesses(hits+misses)
2519 system.l2c.ReadExReq_accesses::cpu1.data 10637 # number of ReadExReq accesses(hits+misses)
2520 system.l2c.ReadExReq_accesses::total 25661 # number of ReadExReq accesses(hits+misses)
2521 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 508 # number of ReadSharedReq accesses(hits+misses)
2522 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 53 # number of ReadSharedReq accesses(hits+misses)
2523 system.l2c.ReadSharedReq_accesses::cpu0.inst 63927 # number of ReadSharedReq accesses(hits+misses)
2524 system.l2c.ReadSharedReq_accesses::cpu0.data 55834 # number of ReadSharedReq accesses(hits+misses)
2525 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 174904 # number of ReadSharedReq accesses(hits+misses)
2526 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 214 # number of ReadSharedReq accesses(hits+misses)
2527 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 33 # number of ReadSharedReq accesses(hits+misses)
2528 system.l2c.ReadSharedReq_accesses::cpu1.inst 27571 # number of ReadSharedReq accesses(hits+misses)
2529 system.l2c.ReadSharedReq_accesses::cpu1.data 13937 # number of ReadSharedReq accesses(hits+misses)
2530 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17207 # number of ReadSharedReq accesses(hits+misses)
2531 system.l2c.ReadSharedReq_accesses::total 354188 # number of ReadSharedReq accesses(hits+misses)
2532 system.l2c.demand_accesses::cpu0.dtb.walker 508 # number of demand (read+write) accesses
2533 system.l2c.demand_accesses::cpu0.itb.walker 53 # number of demand (read+write) accesses
2534 system.l2c.demand_accesses::cpu0.inst 63927 # number of demand (read+write) accesses
2535 system.l2c.demand_accesses::cpu0.data 70858 # number of demand (read+write) accesses
2536 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 174904 # number of demand (read+write) accesses
2537 system.l2c.demand_accesses::cpu1.dtb.walker 214 # number of demand (read+write) accesses
2538 system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses
2539 system.l2c.demand_accesses::cpu1.inst 27571 # number of demand (read+write) accesses
2540 system.l2c.demand_accesses::cpu1.data 24574 # number of demand (read+write) accesses
2541 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17207 # number of demand (read+write) accesses
2542 system.l2c.demand_accesses::total 379849 # number of demand (read+write) accesses
2543 system.l2c.overall_accesses::cpu0.dtb.walker 508 # number of overall (read+write) accesses
2544 system.l2c.overall_accesses::cpu0.itb.walker 53 # number of overall (read+write) accesses
2545 system.l2c.overall_accesses::cpu0.inst 63927 # number of overall (read+write) accesses
2546 system.l2c.overall_accesses::cpu0.data 70858 # number of overall (read+write) accesses
2547 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 174904 # number of overall (read+write) accesses
2548 system.l2c.overall_accesses::cpu1.dtb.walker 214 # number of overall (read+write) accesses
2549 system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses
2550 system.l2c.overall_accesses::cpu1.inst 27571 # number of overall (read+write) accesses
2551 system.l2c.overall_accesses::cpu1.data 24574 # number of overall (read+write) accesses
2552 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17207 # number of overall (read+write) accesses
2553 system.l2c.overall_accesses::total 379849 # number of overall (read+write) accesses
2554 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.743165 # miss rate for UpgradeReq accesses
2555 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.812687 # miss rate for UpgradeReq accesses
2556 system.l2c.UpgradeReq_miss_rate::total 0.763921 # miss rate for UpgradeReq accesses
2557 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.756167 # miss rate for SCUpgradeReq accesses
2558 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.935957 # miss rate for SCUpgradeReq accesses
2559 system.l2c.SCUpgradeReq_miss_rate::total 0.855319 # miss rate for SCUpgradeReq accesses
2560 system.l2c.ReadExReq_miss_rate::cpu0.data 0.730099 # miss rate for ReadExReq accesses
2561 system.l2c.ReadExReq_miss_rate::cpu1.data 0.794773 # miss rate for ReadExReq accesses
2562 system.l2c.ReadExReq_miss_rate::total 0.756907 # miss rate for ReadExReq accesses
2563 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for ReadSharedReq accesses
2564 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.018868 # miss rate for ReadSharedReq accesses
2565 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.305755 # miss rate for ReadSharedReq accesses
2566 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.152989 # miss rate for ReadSharedReq accesses
2567 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for ReadSharedReq accesses
2568 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for ReadSharedReq accesses
2569 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.213630 # miss rate for ReadSharedReq accesses
2570 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.193442 # miss rate for ReadSharedReq accesses
2571 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for ReadSharedReq accesses
2572 system.l2c.ReadSharedReq_miss_rate::total 0.492764 # miss rate for ReadSharedReq accesses
2573 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for demand accesses
2574 system.l2c.demand_miss_rate::cpu0.itb.walker 0.018868 # miss rate for demand accesses
2575 system.l2c.demand_miss_rate::cpu0.inst 0.305755 # miss rate for demand accesses
2576 system.l2c.demand_miss_rate::cpu0.data 0.275354 # miss rate for demand accesses
2577 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for demand accesses
2578 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for demand accesses
2579 system.l2c.demand_miss_rate::cpu1.inst 0.213630 # miss rate for demand accesses
2580 system.l2c.demand_miss_rate::cpu1.data 0.453732 # miss rate for demand accesses
2581 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for demand accesses
2582 system.l2c.demand_miss_rate::total 0.510608 # miss rate for demand accesses
2583 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for overall accesses
2584 system.l2c.overall_miss_rate::cpu0.itb.walker 0.018868 # miss rate for overall accesses
2585 system.l2c.overall_miss_rate::cpu0.inst 0.305755 # miss rate for overall accesses
2586 system.l2c.overall_miss_rate::cpu0.data 0.275354 # miss rate for overall accesses
2587 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for overall accesses
2588 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for overall accesses
2589 system.l2c.overall_miss_rate::cpu1.inst 0.213630 # miss rate for overall accesses
2590 system.l2c.overall_miss_rate::cpu1.data 0.453732 # miss rate for overall accesses
2591 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for overall accesses
2592 system.l2c.overall_miss_rate::total 0.510608 # miss rate for overall accesses
2593 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1047.298069 # average UpgradeReq miss latency
2594 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1252.822779 # average UpgradeReq miss latency
2595 system.l2c.UpgradeReq_avg_miss_latency::total 1112.575037 # average UpgradeReq miss latency
2596 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1668.757842 # average SCUpgradeReq miss latency
2597 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.619951 # average SCUpgradeReq miss latency
2598 system.l2c.SCUpgradeReq_avg_miss_latency::total 1383.830846 # average SCUpgradeReq miss latency
2599 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983 # average ReadExReq miss latency
2600 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628 # average ReadExReq miss latency
2601 system.l2c.ReadExReq_avg_miss_latency::total 91857.334088 # average ReadExReq miss latency
2602 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average ReadSharedReq miss latency
2603 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 303000 # average ReadSharedReq miss latency
2604 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197 # average ReadSharedReq miss latency
2605 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347 # average ReadSharedReq miss latency
2606 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average ReadSharedReq miss latency
2607 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average ReadSharedReq miss latency
2608 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752 # average ReadSharedReq miss latency
2609 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884 # average ReadSharedReq miss latency
2610 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average ReadSharedReq miss latency
2611 system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822 # average ReadSharedReq miss latency
2612 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2613 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
2614 system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
2615 system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
2616 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
2617 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
2618 system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
2619 system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
2620 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
2621 system.l2c.demand_avg_miss_latency::total 97797.738144 # average overall miss latency
2622 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2623 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
2624 system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
2625 system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
2626 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
2627 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
2628 system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
2629 system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
2630 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
2631 system.l2c.overall_avg_miss_latency::total 97797.738144 # average overall miss latency
2632 system.l2c.blocked_cycles::no_mshrs 442 # number of cycles access was blocked
2633 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2634 system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
2635 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2636 system.l2c.avg_blocked_cycles::no_mshrs 221 # average number of cycles each access was blocked
2637 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2638 system.l2c.fast_writes 0 # number of fast writes performed
2639 system.l2c.cache_copies 0 # number of cache copies performed
2640 system.l2c.writebacks::writebacks 103131 # number of writebacks
2641 system.l2c.writebacks::total 103131 # number of writebacks
2642 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2643 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
2644 system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
2645 system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2646 system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
2647 system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
2648 system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
2649 system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
2650 system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
2651 system.l2c.CleanEvict_mshr_misses::writebacks 3812 # number of CleanEvict MSHR misses
2652 system.l2c.CleanEvict_mshr_misses::total 3812 # number of CleanEvict MSHR misses
2653 system.l2c.UpgradeReq_mshr_misses::cpu0.data 8753 # number of UpgradeReq MSHR misses
2654 system.l2c.UpgradeReq_mshr_misses::cpu1.data 4074 # number of UpgradeReq MSHR misses
2655 system.l2c.UpgradeReq_mshr_misses::total 12827 # number of UpgradeReq MSHR misses
2656 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 797 # number of SCUpgradeReq MSHR misses
2657 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1213 # number of SCUpgradeReq MSHR misses
2658 system.l2c.SCUpgradeReq_mshr_misses::total 2010 # number of SCUpgradeReq MSHR misses
2659 system.l2c.ReadExReq_mshr_misses::cpu0.data 10969 # number of ReadExReq MSHR misses
2660 system.l2c.ReadExReq_mshr_misses::cpu1.data 8454 # number of ReadExReq MSHR misses
2661 system.l2c.ReadExReq_mshr_misses::total 19423 # number of ReadExReq MSHR misses
2662 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 121 # number of ReadSharedReq MSHR misses
2663 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
2664 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19541 # number of ReadSharedReq MSHR misses
2665 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8542 # number of ReadSharedReq MSHR misses
2666 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq MSHR misses
2667 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 43 # number of ReadSharedReq MSHR misses
2668 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5886 # number of ReadSharedReq MSHR misses
2669 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2696 # number of ReadSharedReq MSHR misses
2670 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq MSHR misses
2671 system.l2c.ReadSharedReq_mshr_misses::total 174522 # number of ReadSharedReq MSHR misses
2672 system.l2c.demand_mshr_misses::cpu0.dtb.walker 121 # number of demand (read+write) MSHR misses
2673 system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2674 system.l2c.demand_mshr_misses::cpu0.inst 19541 # number of demand (read+write) MSHR misses
2675 system.l2c.demand_mshr_misses::cpu0.data 19511 # number of demand (read+write) MSHR misses
2676 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) MSHR misses
2677 system.l2c.demand_mshr_misses::cpu1.dtb.walker 43 # number of demand (read+write) MSHR misses
2678 system.l2c.demand_mshr_misses::cpu1.inst 5886 # number of demand (read+write) MSHR misses
2679 system.l2c.demand_mshr_misses::cpu1.data 11150 # number of demand (read+write) MSHR misses
2680 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) MSHR misses
2681 system.l2c.demand_mshr_misses::total 193945 # number of demand (read+write) MSHR misses
2682 system.l2c.overall_mshr_misses::cpu0.dtb.walker 121 # number of overall MSHR misses
2683 system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2684 system.l2c.overall_mshr_misses::cpu0.inst 19541 # number of overall MSHR misses
2685 system.l2c.overall_mshr_misses::cpu0.data 19511 # number of overall MSHR misses
2686 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of overall MSHR misses
2687 system.l2c.overall_mshr_misses::cpu1.dtb.walker 43 # number of overall MSHR misses
2688 system.l2c.overall_mshr_misses::cpu1.inst 5886 # number of overall MSHR misses
2689 system.l2c.overall_mshr_misses::cpu1.data 11150 # number of overall MSHR misses
2690 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of overall MSHR misses
2691 system.l2c.overall_mshr_misses::total 193945 # number of overall MSHR misses
2692 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
2693 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
2694 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
2695 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable
2696 system.l2c.ReadReq_mshr_uncacheable::total 38664 # number of ReadReq MSHR uncacheable
2697 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
2698 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
2699 system.l2c.WriteReq_mshr_uncacheable::total 31161 # number of WriteReq MSHR uncacheable
2700 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
2701 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
2702 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
2703 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31529 # number of overall MSHR uncacheable misses
2704 system.l2c.overall_mshr_uncacheable_misses::total 69825 # number of overall MSHR uncacheable misses
2705 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 181795500 # number of UpgradeReq MSHR miss cycles
2706 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 84589501 # number of UpgradeReq MSHR miss cycles
2707 system.l2c.UpgradeReq_mshr_miss_latency::total 266385001 # number of UpgradeReq MSHR miss cycles
2708 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16646000 # number of SCUpgradeReq MSHR miss cycles
2709 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25174500 # number of SCUpgradeReq MSHR miss cycles
2710 system.l2c.SCUpgradeReq_mshr_miss_latency::total 41820500 # number of SCUpgradeReq MSHR miss cycles
2711 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 978307000 # number of ReadExReq MSHR miss cycles
2712 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 611608000 # number of ReadExReq MSHR miss cycles
2713 system.l2c.ReadExReq_mshr_miss_latency::total 1589915000 # number of ReadExReq MSHR miss cycles
2714 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of ReadSharedReq MSHR miss cycles
2715 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 293000 # number of ReadSharedReq MSHR miss cycles
2716 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1362728000 # number of ReadSharedReq MSHR miss cycles
2717 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 663803000 # number of ReadSharedReq MSHR miss cycles
2718 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of ReadSharedReq MSHR miss cycles
2719 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of ReadSharedReq MSHR miss cycles
2720 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 424750500 # number of ReadSharedReq MSHR miss cycles
2721 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 213285000 # number of ReadSharedReq MSHR miss cycles
2722 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of ReadSharedReq MSHR miss cycles
2723 system.l2c.ReadSharedReq_mshr_miss_latency::total 15438404504 # number of ReadSharedReq MSHR miss cycles
2724 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of demand (read+write) MSHR miss cycles
2725 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) MSHR miss cycles
2726 system.l2c.demand_mshr_miss_latency::cpu0.inst 1362728000 # number of demand (read+write) MSHR miss cycles
2727 system.l2c.demand_mshr_miss_latency::cpu0.data 1642110000 # number of demand (read+write) MSHR miss cycles
2728 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of demand (read+write) MSHR miss cycles
2729 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of demand (read+write) MSHR miss cycles
2730 system.l2c.demand_mshr_miss_latency::cpu1.inst 424750500 # number of demand (read+write) MSHR miss cycles
2731 system.l2c.demand_mshr_miss_latency::cpu1.data 824893000 # number of demand (read+write) MSHR miss cycles
2732 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of demand (read+write) MSHR miss cycles
2733 system.l2c.demand_mshr_miss_latency::total 17028319504 # number of demand (read+write) MSHR miss cycles
2734 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of overall MSHR miss cycles
2735 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 293000 # number of overall MSHR miss cycles
2736 system.l2c.overall_mshr_miss_latency::cpu0.inst 1362728000 # number of overall MSHR miss cycles
2737 system.l2c.overall_mshr_miss_latency::cpu0.data 1642110000 # number of overall MSHR miss cycles
2738 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of overall MSHR miss cycles
2739 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of overall MSHR miss cycles
2740 system.l2c.overall_mshr_miss_latency::cpu1.inst 424750500 # number of overall MSHR miss cycles
2741 system.l2c.overall_mshr_miss_latency::cpu1.data 824893000 # number of overall MSHR miss cycles
2742 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of overall MSHR miss cycles
2743 system.l2c.overall_mshr_miss_latency::total 17028319504 # number of overall MSHR miss cycles
2744 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles
2745 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283233500 # number of ReadReq MSHR uncacheable cycles
2746 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6848500 # number of ReadReq MSHR uncacheable cycles
2747 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489515500 # number of ReadReq MSHR uncacheable cycles
2748 system.l2c.ReadReq_mshr_uncacheable_latency::total 5994522000 # number of ReadReq MSHR uncacheable cycles
2749 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314676500 # number of WriteReq MSHR uncacheable cycles
2750 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093562500 # number of WriteReq MSHR uncacheable cycles
2751 system.l2c.WriteReq_mshr_uncacheable_latency::total 4408239000 # number of WriteReq MSHR uncacheable cycles
2752 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles
2753 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5597910000 # number of overall MSHR uncacheable cycles
2754 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6848500 # number of overall MSHR uncacheable cycles
2755 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583078000 # number of overall MSHR uncacheable cycles
2756 system.l2c.overall_mshr_uncacheable_latency::total 10402761000 # number of overall MSHR uncacheable cycles
2757 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2758 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2759 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.743165 # mshr miss rate for UpgradeReq accesses
2760 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812687 # mshr miss rate for UpgradeReq accesses
2761 system.l2c.UpgradeReq_mshr_miss_rate::total 0.763921 # mshr miss rate for UpgradeReq accesses
2762 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756167 # mshr miss rate for SCUpgradeReq accesses
2763 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935957 # mshr miss rate for SCUpgradeReq accesses
2764 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855319 # mshr miss rate for SCUpgradeReq accesses
2765 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730099 # mshr miss rate for ReadExReq accesses
2766 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794773 # mshr miss rate for ReadExReq accesses
2767 system.l2c.ReadExReq_mshr_miss_rate::total 0.756907 # mshr miss rate for ReadExReq accesses
2768 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for ReadSharedReq accesses
2769 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for ReadSharedReq accesses
2770 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for ReadSharedReq accesses
2771 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.152989 # mshr miss rate for ReadSharedReq accesses
2772 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for ReadSharedReq accesses
2773 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for ReadSharedReq accesses
2774 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for ReadSharedReq accesses
2775 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.193442 # mshr miss rate for ReadSharedReq accesses
2776 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for ReadSharedReq accesses
2777 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492738 # mshr miss rate for ReadSharedReq accesses
2778 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for demand accesses
2779 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for demand accesses
2780 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for demand accesses
2781 system.l2c.demand_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for demand accesses
2782 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for demand accesses
2783 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for demand accesses
2784 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for demand accesses
2785 system.l2c.demand_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for demand accesses
2786 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for demand accesses
2787 system.l2c.demand_mshr_miss_rate::total 0.510584 # mshr miss rate for demand accesses
2788 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for overall accesses
2789 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for overall accesses
2790 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for overall accesses
2791 system.l2c.overall_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for overall accesses
2792 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for overall accesses
2793 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for overall accesses
2794 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for overall accesses
2795 system.l2c.overall_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for overall accesses
2796 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for overall accesses
2797 system.l2c.overall_mshr_miss_rate::total 0.510584 # mshr miss rate for overall accesses
2798 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597 # average UpgradeReq mshr miss latency
2799 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032 # average UpgradeReq mshr miss latency
2800 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712 # average UpgradeReq mshr miss latency
2801 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832 # average SCUpgradeReq mshr miss latency
2802 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911 # average SCUpgradeReq mshr miss latency
2803 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905 # average SCUpgradeReq mshr miss latency
2804 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983 # average ReadExReq mshr miss latency
2805 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628 # average ReadExReq mshr miss latency
2806 system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088 # average ReadExReq mshr miss latency
2807 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average ReadSharedReq mshr miss latency
2808 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency
2809 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average ReadSharedReq mshr miss latency
2810 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347 # average ReadSharedReq mshr miss latency
2811 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average ReadSharedReq mshr miss latency
2812 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average ReadSharedReq mshr miss latency
2813 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average ReadSharedReq mshr miss latency
2814 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884 # average ReadSharedReq mshr miss latency
2815 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average ReadSharedReq mshr miss latency
2816 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428 # average ReadSharedReq mshr miss latency
2817 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2818 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
2819 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
2820 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
2821 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
2822 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
2823 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
2824 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
2825 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
2826 system.l2c.demand_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
2827 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2828 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
2829 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
2830 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
2831 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
2832 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
2833 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
2834 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
2835 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
2836 system.l2c.overall_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
2837 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency
2838 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237 # average ReadReq mshr uncacheable latency
2839 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average ReadReq mshr uncacheable latency
2840 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323 # average ReadReq mshr uncacheable latency
2841 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892 # average ReadReq mshr uncacheable latency
2842 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749 # average WriteReq mshr uncacheable latency
2843 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896 # average WriteReq mshr uncacheable latency
2844 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719 # average WriteReq mshr uncacheable latency
2845 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency
2846 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815 # average overall mshr uncacheable latency
2847 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average overall mshr uncacheable latency
2848 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532 # average overall mshr uncacheable latency
2849 system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753 # average overall mshr uncacheable latency
2850 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2851 system.membus.trans_dist::ReadReq 38664 # Transaction distribution
2852 system.membus.trans_dist::ReadResp 213442 # Transaction distribution
2853 system.membus.trans_dist::WriteReq 31161 # Transaction distribution
2854 system.membus.trans_dist::WriteResp 31161 # Transaction distribution
2855 system.membus.trans_dist::Writeback 139337 # Transaction distribution
2856 system.membus.trans_dist::CleanEvict 18210 # Transaction distribution
2857 system.membus.trans_dist::UpgradeReq 78893 # Transaction distribution
2858 system.membus.trans_dist::SCUpgradeReq 41609 # Transaction distribution
2859 system.membus.trans_dist::UpgradeResp 14967 # Transaction distribution
2860 system.membus.trans_dist::ReadExReq 39746 # Transaction distribution
2861 system.membus.trans_dist::ReadExResp 19293 # Transaction distribution
2862 system.membus.trans_dist::ReadSharedReq 174778 # Transaction distribution
2863 system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2864 system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2865 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes)
2866 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
2867 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14714 # Packet count per connected master and slave (bytes)
2868 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 681524 # Packet count per connected master and slave (bytes)
2869 system.membus.pkt_count_system.l2c.mem_side::total 804190 # Packet count per connected master and slave (bytes)
2870 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108938 # Packet count per connected master and slave (bytes)
2871 system.membus.pkt_count_system.iocache.mem_side::total 108938 # Packet count per connected master and slave (bytes)
2872 system.membus.pkt_count::total 913128 # Packet count per connected master and slave (bytes)
2873 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
2874 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
2875 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29428 # Cumulative packet size per connected master and slave (bytes)
2876 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19228072 # Cumulative packet size per connected master and slave (bytes)
2877 system.membus.pkt_size_system.l2c.mem_side::total 19421637 # Cumulative packet size per connected master and slave (bytes)
2878 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
2879 system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2880 system.membus.pkt_size::total 21739781 # Cumulative packet size per connected master and slave (bytes)
2881 system.membus.snoops 126569 # Total snoops (count)
2882 system.membus.snoop_fanout::samples 598906 # Request fanout histogram
2883 system.membus.snoop_fanout::mean 1 # Request fanout histogram
2884 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2885 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2886 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2887 system.membus.snoop_fanout::1 598906 100.00% 100.00% # Request fanout histogram
2888 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2889 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2890 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2891 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2892 system.membus.snoop_fanout::total 598906 # Request fanout histogram
2893 system.membus.reqLayer0.occupancy 91147500 # Layer occupancy (ticks)
2894 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2895 system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks)
2896 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2897 system.membus.reqLayer2.occupancy 12904500 # Layer occupancy (ticks)
2898 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2899 system.membus.reqLayer5.occupancy 1003618732 # Layer occupancy (ticks)
2900 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2901 system.membus.respLayer2.occupancy 1163956699 # Layer occupancy (ticks)
2902 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2903 system.membus.respLayer3.occupancy 64493538 # Layer occupancy (ticks)
2904 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2905 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2906 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2907 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2908 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2909 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2910 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2911 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2912 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2913 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
2914 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2915 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2916 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
2917 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2918 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2919 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
2920 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2921 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2922 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
2923 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2924 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2925 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
2926 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2927 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2928 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2929 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2930 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2931 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2932 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2933 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2934 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2935 system.realview.ethernet.droppedPackets 0 # number of packets dropped
2936 system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
2937 system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
2938 system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
2939 system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
2940 system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
2941 system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
2942 system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2943 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
2944 system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
2945 system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2946 system.toL2Bus.trans_dist::ReadReq 38668 # Transaction distribution
2947 system.toL2Bus.trans_dist::ReadResp 519865 # Transaction distribution
2948 system.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
2949 system.toL2Bus.trans_dist::WriteResp 31161 # Transaction distribution
2950 system.toL2Bus.trans_dist::Writeback 372085 # Transaction distribution
2951 system.toL2Bus.trans_dist::CleanEvict 99404 # Transaction distribution
2952 system.toL2Bus.trans_dist::UpgradeReq 82727 # Transaction distribution
2953 system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution
2954 system.toL2Bus.trans_dist::UpgradeResp 124676 # Transaction distribution
2955 system.toL2Bus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution
2956 system.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
2957 system.toL2Bus.trans_dist::ReadExReq 51768 # Transaction distribution
2958 system.toL2Bus.trans_dist::ReadExResp 51768 # Transaction distribution
2959 system.toL2Bus.trans_dist::ReadSharedReq 481212 # Transaction distribution
2960 system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2961 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1091980 # Packet count per connected master and slave (bytes)
2962 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404567 # Packet count per connected master and slave (bytes)
2963 system.toL2Bus.pkt_count::total 1496547 # Packet count per connected master and slave (bytes)
2964 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32727326 # Cumulative packet size per connected master and slave (bytes)
2965 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6930535 # Cumulative packet size per connected master and slave (bytes)
2966 system.toL2Bus.pkt_size::total 39657861 # Cumulative packet size per connected master and slave (bytes)
2967 system.toL2Bus.snoops 466410 # Total snoops (count)
2968 system.toL2Bus.snoop_fanout::samples 1287380 # Request fanout histogram
2969 system.toL2Bus.snoop_fanout::mean 1.161360 # Request fanout histogram
2970 system.toL2Bus.snoop_fanout::stdev 0.367862 # Request fanout histogram
2971 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2972 system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2973 system.toL2Bus.snoop_fanout::1 1079649 83.86% 83.86% # Request fanout histogram
2974 system.toL2Bus.snoop_fanout::2 207731 16.14% 100.00% # Request fanout histogram
2975 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2976 system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2977 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2978 system.toL2Bus.snoop_fanout::total 1287380 # Request fanout histogram
2979 system.toL2Bus.reqLayer0.occupancy 861414818 # Layer occupancy (ticks)
2980 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2981 system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks)
2982 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2983 system.toL2Bus.respLayer0.occupancy 631551677 # Layer occupancy (ticks)
2984 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2985 system.toL2Bus.respLayer1.occupancy 286263459 # Layer occupancy (ticks)
2986 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2988 ---------- End Simulation Statistics ----------
projects / gem5.git / blob