tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=0
  37 machine_type=RealView_PBX
  38 mem_mode=timing
  39 mem_ranges=0:134217727
  40 memories=system.physmem system.realview.nvmem
  41 multi_proc=true
  42 num_work_ids=16
  43 panic_on_oops=true
  44 panic_on_panic=true
  45 phys_addr_range_64=40
  46 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  47 reset_addr_64=0
  48 symbolfile=
  49 work_begin_ckpt_count=0
  50 work_begin_cpu_id_exit=-1
  51 work_begin_exit_count=0
  52 work_cpus_ckpt_count=0
  53 work_end_ckpt_count=0
  54 work_end_exit_count=0
  55 work_item_id=-1
  56 system_port=system.membus.slave[0]
  57
  58 [system.bridge]
  59 type=Bridge
  60 clk_domain=system.clk_domain
  61 delay=50000
  62 eventq_index=0
  63 ranges=268435456:520093695 1073741824:1610612735
  64 req_size=16
  65 resp_size=16
  66 master=system.iobus.slave[0]
  67 slave=system.membus.master[0]
  68
  69 [system.cf0]
  70 type=IdeDisk
  71 children=image
  72 delay=1000000
  73 driveID=master
  74 eventq_index=0
  75 image=system.cf0.image
  76
  77 [system.cf0.image]
  78 type=CowDiskImage
  79 children=child
  80 child=system.cf0.image.child
  81 eventq_index=0
  82 image_file=
  83 read_only=false
  84 table_size=65536
  85
  86 [system.cf0.image.child]
  87 type=RawDiskImage
  88 eventq_index=0
  89 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  90 read_only=true
  91
  92 [system.clk_domain]
  93 type=SrcClockDomain
  94 clock=1000
  95 domain_id=-1
  96 eventq_index=0
  97 init_perf_level=0
  98 voltage_domain=system.voltage_domain
  99
 100 [system.cpu]
 101 type=DerivO3CPU
 102 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 103 LFSTSize=1024
 104 LQEntries=16
 105 LSQCheckLoads=true
 106 LSQDepCheckShift=0
 107 SQEntries=16
 108 SSITSize=1024
 109 activity=0
 110 backComSize=5
 111 branchPred=system.cpu.branchPred
 112 cachePorts=200
 113 checker=Null
 114 clk_domain=system.cpu_clk_domain
 115 commitToDecodeDelay=1
 116 commitToFetchDelay=1
 117 commitToIEWDelay=1
 118 commitToRenameDelay=1
 119 commitWidth=8
 120 cpu_id=0
 121 decodeToFetchDelay=1
 122 decodeToRenameDelay=2
 123 decodeWidth=3
 124 dispatchWidth=6
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu.dstage2_mmu
 129 dtb=system.cpu.dtb
 130 eventq_index=0
 131 fetchBufferSize=16
 132 fetchQueueSize=32
 133 fetchToDecodeDelay=3
 134 fetchTrapLatency=1
 135 fetchWidth=3
 136 forwardComSize=5
 137 fuPool=system.cpu.fuPool
 138 function_trace=false
 139 function_trace_start=0
 140 iewToCommitDelay=1
 141 iewToDecodeDelay=1
 142 iewToFetchDelay=1
 143 iewToRenameDelay=1
 144 interrupts=system.cpu.interrupts
 145 isa=system.cpu.isa
 146 issueToExecuteDelay=1
 147 issueWidth=8
 148 istage2_mmu=system.cpu.istage2_mmu
 149 itb=system.cpu.itb
 150 max_insts_all_threads=0
 151 max_insts_any_thread=0
 152 max_loads_all_threads=0
 153 max_loads_any_thread=0
 154 needsTSO=false
 155 numIQEntries=32
 156 numPhysCCRegs=640
 157 numPhysFloatRegs=192
 158 numPhysIntRegs=128
 159 numROBEntries=40
 160 numRobs=1
 161 numThreads=1
 162 profile=0
 163 progress_interval=0
 164 renameToDecodeDelay=1
 165 renameToFetchDelay=1
 166 renameToIEWDelay=1
 167 renameToROBDelay=1
 168 renameWidth=3
 169 simpoint_start_insts=
 170 smtCommitPolicy=RoundRobin
 171 smtFetchPolicy=SingleThread
 172 smtIQPolicy=Partitioned
 173 smtIQThreshold=100
 174 smtLSQPolicy=Partitioned
 175 smtLSQThreshold=100
 176 smtNumFetchingThreads=1
 177 smtROBPolicy=Partitioned
 178 smtROBThreshold=100
 179 socket_id=0
 180 squashWidth=8
 181 store_set_clear_period=250000
 182 switched_out=false
 183 system=system
 184 tracer=system.cpu.tracer
 185 trapLatency=13
 186 wbWidth=8
 187 workload=
 188 dcache_port=system.cpu.dcache.cpu_side
 189 icache_port=system.cpu.icache.cpu_side
 190
 191 [system.cpu.branchPred]
 192 type=BranchPredictor
 193 BTBEntries=2048
 194 BTBTagSize=18
 195 RASSize=16
 196 choiceCtrBits=2
 197 choicePredictorSize=8192
 198 eventq_index=0
 199 globalCtrBits=2
 200 globalPredictorSize=8192
 201 instShiftAmt=2
 202 localCtrBits=2
 203 localHistoryTableSize=2048
 204 localPredictorSize=2048
 205 numThreads=1
 206 predType=bi-mode
 207
 208 [system.cpu.dcache]
 209 type=BaseCache
 210 children=tags
 211 addr_ranges=0:18446744073709551615
 212 assoc=4
 213 clk_domain=system.cpu_clk_domain
 214 eventq_index=0
 215 forward_snoops=true
 216 hit_latency=2
 217 is_top_level=true
 218 max_miss_count=0
 219 mshrs=4
 220 prefetch_on_access=false
 221 prefetcher=Null
 222 response_latency=2
 223 sequential_access=false
 224 size=32768
 225 system=system
 226 tags=system.cpu.dcache.tags
 227 tgts_per_mshr=20
 228 two_queue=false
 229 write_buffers=8
 230 cpu_side=system.cpu.dcache_port
 231 mem_side=system.cpu.toL2Bus.slave[1]
 232
 233 [system.cpu.dcache.tags]
 234 type=LRU
 235 assoc=4
 236 block_size=64
 237 clk_domain=system.cpu_clk_domain
 238 eventq_index=0
 239 hit_latency=2
 240 sequential_access=false
 241 size=32768
 242
 243 [system.cpu.dstage2_mmu]
 244 type=ArmStage2MMU
 245 children=stage2_tlb
 246 eventq_index=0
 247 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 248 tlb=system.cpu.dtb
 249
 250 [system.cpu.dstage2_mmu.stage2_tlb]
 251 type=ArmTLB
 252 children=walker
 253 eventq_index=0
 254 is_stage2=true
 255 size=32
 256 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 257
 258 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 259 type=ArmTableWalker
 260 clk_domain=system.cpu_clk_domain
 261 eventq_index=0
 262 is_stage2=true
 263 num_squash_per_cycle=2
 264 sys=system
 265 port=system.cpu.toL2Bus.slave[5]
 266
 267 [system.cpu.dtb]
 268 type=ArmTLB
 269 children=walker
 270 eventq_index=0
 271 is_stage2=false
 272 size=64
 273 walker=system.cpu.dtb.walker
 274
 275 [system.cpu.dtb.walker]
 276 type=ArmTableWalker
 277 clk_domain=system.cpu_clk_domain
 278 eventq_index=0
 279 is_stage2=false
 280 num_squash_per_cycle=2
 281 sys=system
 282 port=system.cpu.toL2Bus.slave[3]
 283
 284 [system.cpu.fuPool]
 285 type=FUPool
 286 children=FUList0 FUList1 FUList2 FUList3 FUList4
 287 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 288 eventq_index=0
 289
 290 [system.cpu.fuPool.FUList0]
 291 type=FUDesc
 292 children=opList
 293 count=2
 294 eventq_index=0
 295 opList=system.cpu.fuPool.FUList0.opList
 296
 297 [system.cpu.fuPool.FUList0.opList]
 298 type=OpDesc
 299 eventq_index=0
 300 issueLat=1
 301 opClass=IntAlu
 302 opLat=1
 303
 304 [system.cpu.fuPool.FUList1]
 305 type=FUDesc
 306 children=opList0 opList1 opList2
 307 count=1
 308 eventq_index=0
 309 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 310
 311 [system.cpu.fuPool.FUList1.opList0]
 312 type=OpDesc
 313 eventq_index=0
 314 issueLat=1
 315 opClass=IntMult
 316 opLat=3
 317
 318 [system.cpu.fuPool.FUList1.opList1]
 319 type=OpDesc
 320 eventq_index=0
 321 issueLat=12
 322 opClass=IntDiv
 323 opLat=12
 324
 325 [system.cpu.fuPool.FUList1.opList2]
 326 type=OpDesc
 327 eventq_index=0
 328 issueLat=1
 329 opClass=IprAccess
 330 opLat=3
 331
 332 [system.cpu.fuPool.FUList2]
 333 type=FUDesc
 334 children=opList
 335 count=1
 336 eventq_index=0
 337 opList=system.cpu.fuPool.FUList2.opList
 338
 339 [system.cpu.fuPool.FUList2.opList]
 340 type=OpDesc
 341 eventq_index=0
 342 issueLat=1
 343 opClass=MemRead
 344 opLat=2
 345
 346 [system.cpu.fuPool.FUList3]
 347 type=FUDesc
 348 children=opList
 349 count=1
 350 eventq_index=0
 351 opList=system.cpu.fuPool.FUList3.opList
 352
 353 [system.cpu.fuPool.FUList3.opList]
 354 type=OpDesc
 355 eventq_index=0
 356 issueLat=1
 357 opClass=MemWrite
 358 opLat=2
 359
 360 [system.cpu.fuPool.FUList4]
 361 type=FUDesc
 362 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 363 count=2
 364 eventq_index=0
 365 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 366
 367 [system.cpu.fuPool.FUList4.opList00]
 368 type=OpDesc
 369 eventq_index=0
 370 issueLat=1
 371 opClass=SimdAdd
 372 opLat=4
 373
 374 [system.cpu.fuPool.FUList4.opList01]
 375 type=OpDesc
 376 eventq_index=0
 377 issueLat=1
 378 opClass=SimdAddAcc
 379 opLat=4
 380
 381 [system.cpu.fuPool.FUList4.opList02]
 382 type=OpDesc
 383 eventq_index=0
 384 issueLat=1
 385 opClass=SimdAlu
 386 opLat=4
 387
 388 [system.cpu.fuPool.FUList4.opList03]
 389 type=OpDesc
 390 eventq_index=0
 391 issueLat=1
 392 opClass=SimdCmp
 393 opLat=4
 394
 395 [system.cpu.fuPool.FUList4.opList04]
 396 type=OpDesc
 397 eventq_index=0
 398 issueLat=1
 399 opClass=SimdCvt
 400 opLat=3
 401
 402 [system.cpu.fuPool.FUList4.opList05]
 403 type=OpDesc
 404 eventq_index=0
 405 issueLat=1
 406 opClass=SimdMisc
 407 opLat=3
 408
 409 [system.cpu.fuPool.FUList4.opList06]
 410 type=OpDesc
 411 eventq_index=0
 412 issueLat=1
 413 opClass=SimdMult
 414 opLat=5
 415
 416 [system.cpu.fuPool.FUList4.opList07]
 417 type=OpDesc
 418 eventq_index=0
 419 issueLat=1
 420 opClass=SimdMultAcc
 421 opLat=5
 422
 423 [system.cpu.fuPool.FUList4.opList08]
 424 type=OpDesc
 425 eventq_index=0
 426 issueLat=1
 427 opClass=SimdShift
 428 opLat=3
 429
 430 [system.cpu.fuPool.FUList4.opList09]
 431 type=OpDesc
 432 eventq_index=0
 433 issueLat=1
 434 opClass=SimdShiftAcc
 435 opLat=3
 436
 437 [system.cpu.fuPool.FUList4.opList10]
 438 type=OpDesc
 439 eventq_index=0
 440 issueLat=1
 441 opClass=SimdSqrt
 442 opLat=9
 443
 444 [system.cpu.fuPool.FUList4.opList11]
 445 type=OpDesc
 446 eventq_index=0
 447 issueLat=1
 448 opClass=SimdFloatAdd
 449 opLat=5
 450
 451 [system.cpu.fuPool.FUList4.opList12]
 452 type=OpDesc
 453 eventq_index=0
 454 issueLat=1
 455 opClass=SimdFloatAlu
 456 opLat=5
 457
 458 [system.cpu.fuPool.FUList4.opList13]
 459 type=OpDesc
 460 eventq_index=0
 461 issueLat=1
 462 opClass=SimdFloatCmp
 463 opLat=3
 464
 465 [system.cpu.fuPool.FUList4.opList14]
 466 type=OpDesc
 467 eventq_index=0
 468 issueLat=1
 469 opClass=SimdFloatCvt
 470 opLat=3
 471
 472 [system.cpu.fuPool.FUList4.opList15]
 473 type=OpDesc
 474 eventq_index=0
 475 issueLat=1
 476 opClass=SimdFloatDiv
 477 opLat=3
 478
 479 [system.cpu.fuPool.FUList4.opList16]
 480 type=OpDesc
 481 eventq_index=0
 482 issueLat=1
 483 opClass=SimdFloatMisc
 484 opLat=3
 485
 486 [system.cpu.fuPool.FUList4.opList17]
 487 type=OpDesc
 488 eventq_index=0
 489 issueLat=1
 490 opClass=SimdFloatMult
 491 opLat=3
 492
 493 [system.cpu.fuPool.FUList4.opList18]
 494 type=OpDesc
 495 eventq_index=0
 496 issueLat=1
 497 opClass=SimdFloatMultAcc
 498 opLat=1
 499
 500 [system.cpu.fuPool.FUList4.opList19]
 501 type=OpDesc
 502 eventq_index=0
 503 issueLat=1
 504 opClass=SimdFloatSqrt
 505 opLat=9
 506
 507 [system.cpu.fuPool.FUList4.opList20]
 508 type=OpDesc
 509 eventq_index=0
 510 issueLat=1
 511 opClass=FloatAdd
 512 opLat=5
 513
 514 [system.cpu.fuPool.FUList4.opList21]
 515 type=OpDesc
 516 eventq_index=0
 517 issueLat=1
 518 opClass=FloatCmp
 519 opLat=5
 520
 521 [system.cpu.fuPool.FUList4.opList22]
 522 type=OpDesc
 523 eventq_index=0
 524 issueLat=1
 525 opClass=FloatCvt
 526 opLat=5
 527
 528 [system.cpu.fuPool.FUList4.opList23]
 529 type=OpDesc
 530 eventq_index=0
 531 issueLat=9
 532 opClass=FloatDiv
 533 opLat=9
 534
 535 [system.cpu.fuPool.FUList4.opList24]
 536 type=OpDesc
 537 eventq_index=0
 538 issueLat=33
 539 opClass=FloatSqrt
 540 opLat=33
 541
 542 [system.cpu.fuPool.FUList4.opList25]
 543 type=OpDesc
 544 eventq_index=0
 545 issueLat=1
 546 opClass=FloatMult
 547 opLat=4
 548
 549 [system.cpu.icache]
 550 type=BaseCache
 551 children=tags
 552 addr_ranges=0:18446744073709551615
 553 assoc=1
 554 clk_domain=system.cpu_clk_domain
 555 eventq_index=0
 556 forward_snoops=true
 557 hit_latency=2
 558 is_top_level=true
 559 max_miss_count=0
 560 mshrs=4
 561 prefetch_on_access=false
 562 prefetcher=Null
 563 response_latency=2
 564 sequential_access=false
 565 size=32768
 566 system=system
 567 tags=system.cpu.icache.tags
 568 tgts_per_mshr=20
 569 two_queue=false
 570 write_buffers=8
 571 cpu_side=system.cpu.icache_port
 572 mem_side=system.cpu.toL2Bus.slave[0]
 573
 574 [system.cpu.icache.tags]
 575 type=LRU
 576 assoc=1
 577 block_size=64
 578 clk_domain=system.cpu_clk_domain
 579 eventq_index=0
 580 hit_latency=2
 581 sequential_access=false
 582 size=32768
 583
 584 [system.cpu.interrupts]
 585 type=ArmInterrupts
 586 eventq_index=0
 587
 588 [system.cpu.isa]
 589 type=ArmISA
 590 eventq_index=0
 591 fpsid=1090793632
 592 id_aa64afr0_el1=0
 593 id_aa64afr1_el1=0
 594 id_aa64dfr0_el1=1052678
 595 id_aa64dfr1_el1=0
 596 id_aa64isar0_el1=0
 597 id_aa64isar1_el1=0
 598 id_aa64mmfr0_el1=15728642
 599 id_aa64mmfr1_el1=0
 600 id_aa64pfr0_el1=17
 601 id_aa64pfr1_el1=0
 602 id_isar0=34607377
 603 id_isar1=34677009
 604 id_isar2=555950401
 605 id_isar3=17899825
 606 id_isar4=268501314
 607 id_isar5=0
 608 id_mmfr0=270536963
 609 id_mmfr1=0
 610 id_mmfr2=19070976
 611 id_mmfr3=34611729
 612 id_pfr0=49
 613 id_pfr1=4113
 614 midr=1091551472
 615 system=system
 616
 617 [system.cpu.istage2_mmu]
 618 type=ArmStage2MMU
 619 children=stage2_tlb
 620 eventq_index=0
 621 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 622 tlb=system.cpu.itb
 623
 624 [system.cpu.istage2_mmu.stage2_tlb]
 625 type=ArmTLB
 626 children=walker
 627 eventq_index=0
 628 is_stage2=true
 629 size=32
 630 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 631
 632 [system.cpu.istage2_mmu.stage2_tlb.walker]
 633 type=ArmTableWalker
 634 clk_domain=system.cpu_clk_domain
 635 eventq_index=0
 636 is_stage2=true
 637 num_squash_per_cycle=2
 638 sys=system
 639 port=system.cpu.toL2Bus.slave[4]
 640
 641 [system.cpu.itb]
 642 type=ArmTLB
 643 children=walker
 644 eventq_index=0
 645 is_stage2=false
 646 size=64
 647 walker=system.cpu.itb.walker
 648
 649 [system.cpu.itb.walker]
 650 type=ArmTableWalker
 651 clk_domain=system.cpu_clk_domain
 652 eventq_index=0
 653 is_stage2=false
 654 num_squash_per_cycle=2
 655 sys=system
 656 port=system.cpu.toL2Bus.slave[2]
 657
 658 [system.cpu.l2cache]
 659 type=BaseCache
 660 children=tags
 661 addr_ranges=0:18446744073709551615
 662 assoc=8
 663 clk_domain=system.cpu_clk_domain
 664 eventq_index=0
 665 forward_snoops=true
 666 hit_latency=20
 667 is_top_level=false
 668 max_miss_count=0
 669 mshrs=20
 670 prefetch_on_access=false
 671 prefetcher=Null
 672 response_latency=20
 673 sequential_access=false
 674 size=4194304
 675 system=system
 676 tags=system.cpu.l2cache.tags
 677 tgts_per_mshr=12
 678 two_queue=false
 679 write_buffers=8
 680 cpu_side=system.cpu.toL2Bus.master[0]
 681 mem_side=system.membus.slave[1]
 682
 683 [system.cpu.l2cache.tags]
 684 type=LRU
 685 assoc=8
 686 block_size=64
 687 clk_domain=system.cpu_clk_domain
 688 eventq_index=0
 689 hit_latency=20
 690 sequential_access=false
 691 size=4194304
 692
 693 [system.cpu.toL2Bus]
 694 type=CoherentXBar
 695 clk_domain=system.cpu_clk_domain
 696 eventq_index=0
 697 header_cycles=1
 698 snoop_filter=Null
 699 system=system
 700 use_default_range=false
 701 width=32
 702 master=system.cpu.l2cache.cpu_side
 703 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 704
 705 [system.cpu.tracer]
 706 type=ExeTracer
 707 eventq_index=0
 708
 709 [system.cpu_clk_domain]
 710 type=SrcClockDomain
 711 clock=500
 712 domain_id=-1
 713 eventq_index=0
 714 init_perf_level=0
 715 voltage_domain=system.voltage_domain
 716
 717 [system.dvfs_handler]
 718 type=DVFSHandler
 719 domains=
 720 enable=false
 721 eventq_index=0
 722 sys_clk_domain=system.clk_domain
 723 transition_latency=100000000
 724
 725 [system.intrctrl]
 726 type=IntrControl
 727 eventq_index=0
 728 sys=system
 729
 730 [system.iobus]
 731 type=NoncoherentXBar
 732 clk_domain=system.clk_domain
 733 eventq_index=0
 734 header_cycles=1
 735 use_default_range=false
 736 width=8
 737 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
 738 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 739
 740 [system.iocache]
 741 type=BaseCache
 742 children=tags
 743 addr_ranges=0:134217727
 744 assoc=8
 745 clk_domain=system.clk_domain
 746 eventq_index=0
 747 forward_snoops=false
 748 hit_latency=50
 749 is_top_level=true
 750 max_miss_count=0
 751 mshrs=20
 752 prefetch_on_access=false
 753 prefetcher=Null
 754 response_latency=50
 755 sequential_access=false
 756 size=1024
 757 system=system
 758 tags=system.iocache.tags
 759 tgts_per_mshr=12
 760 two_queue=false
 761 write_buffers=8
 762 cpu_side=system.iobus.master[26]
 763 mem_side=system.membus.slave[2]
 764
 765 [system.iocache.tags]
 766 type=LRU
 767 assoc=8
 768 block_size=64
 769 clk_domain=system.clk_domain
 770 eventq_index=0
 771 hit_latency=50
 772 sequential_access=false
 773 size=1024
 774
 775 [system.membus]
 776 type=CoherentXBar
 777 children=badaddr_responder
 778 clk_domain=system.clk_domain
 779 eventq_index=0
 780 header_cycles=1
 781 snoop_filter=Null
 782 system=system
 783 use_default_range=false
 784 width=8
 785 default=system.membus.badaddr_responder.pio
 786 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 787 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 788
 789 [system.membus.badaddr_responder]
 790 type=IsaFake
 791 clk_domain=system.clk_domain
 792 eventq_index=0
 793 fake_mem=false
 794 pio_addr=0
 795 pio_latency=100000
 796 pio_size=8
 797 ret_bad_addr=true
 798 ret_data16=65535
 799 ret_data32=4294967295
 800 ret_data64=18446744073709551615
 801 ret_data8=255
 802 system=system
 803 update_data=false
 804 warn_access=warn
 805 pio=system.membus.default
 806
 807 [system.physmem]
 808 type=DRAMCtrl
 809 IDD0=0.075000
 810 IDD02=0.000000
 811 IDD2N=0.050000
 812 IDD2N2=0.000000
 813 IDD2P0=0.000000
 814 IDD2P02=0.000000
 815 IDD2P1=0.000000
 816 IDD2P12=0.000000
 817 IDD3N=0.057000
 818 IDD3N2=0.000000
 819 IDD3P0=0.000000
 820 IDD3P02=0.000000
 821 IDD3P1=0.000000
 822 IDD3P12=0.000000
 823 IDD4R=0.187000
 824 IDD4R2=0.000000
 825 IDD4W=0.165000
 826 IDD4W2=0.000000
 827 IDD5=0.220000
 828 IDD52=0.000000
 829 IDD6=0.000000
 830 IDD62=0.000000
 831 VDD=1.500000
 832 VDD2=0.000000
 833 activation_limit=4
 834 addr_mapping=RoRaBaChCo
 835 bank_groups_per_rank=0
 836 banks_per_rank=8
 837 burst_length=8
 838 channels=1
 839 clk_domain=system.clk_domain
 840 conf_table_reported=true
 841 device_bus_width=8
 842 device_rowbuffer_size=1024
 843 devices_per_rank=8
 844 dll=true
 845 eventq_index=0
 846 in_addr_map=true
 847 max_accesses_per_row=16
 848 mem_sched_policy=frfcfs
 849 min_writes_per_switch=16
 850 null=false
 851 page_policy=open_adaptive
 852 range=0:134217727
 853 ranks_per_channel=2
 854 read_buffer_size=32
 855 static_backend_latency=10000
 856 static_frontend_latency=10000
 857 tBURST=5000
 858 tCCD_L=0
 859 tCK=1250
 860 tCL=13750
 861 tCS=2500
 862 tRAS=35000
 863 tRCD=13750
 864 tREFI=7800000
 865 tRFC=260000
 866 tRP=13750
 867 tRRD=6000
 868 tRRD_L=0
 869 tRTP=7500
 870 tRTW=2500
 871 tWR=15000
 872 tWTR=7500
 873 tXAW=30000
 874 tXP=0
 875 tXPDLL=0
 876 tXS=0
 877 tXSDLL=0
 878 write_buffer_size=64
 879 write_high_thresh_perc=85
 880 write_low_thresh_perc=50
 881 port=system.membus.master[6]
 882
 883 [system.realview]
 884 type=RealView
 885 children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 886 eventq_index=0
 887 intrctrl=system.intrctrl
 888 pci_cfg_base=0
 889 pci_cfg_gen_offsets=false
 890 pci_io_base=0
 891 system=system
 892
 893 [system.realview.a9scu]
 894 type=A9SCU
 895 clk_domain=system.clk_domain
 896 eventq_index=0
 897 pio_addr=520093696
 898 pio_latency=100000
 899 system=system
 900 pio=system.membus.master[4]
 901
 902 [system.realview.aaci_fake]
 903 type=AmbaFake
 904 amba_id=0
 905 clk_domain=system.clk_domain
 906 eventq_index=0
 907 ignore_access=false
 908 pio_addr=268451840
 909 pio_latency=100000
 910 system=system
 911 pio=system.iobus.master[21]
 912
 913 [system.realview.cf_ctrl]
 914 type=IdeController
 915 BAR0=402653184
 916 BAR0LegacyIO=true
 917 BAR0Size=16
 918 BAR1=402653440
 919 BAR1LegacyIO=true
 920 BAR1Size=1
 921 BAR2=1
 922 BAR2LegacyIO=false
 923 BAR2Size=8
 924 BAR3=1
 925 BAR3LegacyIO=false
 926 BAR3Size=4
 927 BAR4=1
 928 BAR4LegacyIO=false
 929 BAR4Size=16
 930 BAR5=1
 931 BAR5LegacyIO=false
 932 BAR5Size=0
 933 BIST=0
 934 CacheLineSize=0
 935 CapabilityPtr=0
 936 CardbusCIS=0
 937 ClassCode=1
 938 Command=1
 939 DeviceID=28945
 940 ExpansionROM=0
 941 HeaderType=0
 942 InterruptLine=31
 943 InterruptPin=1
 944 LatencyTimer=0
 945 LegacyIOBase=0
 946 MSICAPBaseOffset=0
 947 MSICAPCapId=0
 948 MSICAPMaskBits=0
 949 MSICAPMsgAddr=0
 950 MSICAPMsgCtrl=0
 951 MSICAPMsgData=0
 952 MSICAPMsgUpperAddr=0
 953 MSICAPNextCapability=0
 954 MSICAPPendingBits=0
 955 MSIXCAPBaseOffset=0
 956 MSIXCAPCapId=0
 957 MSIXCAPNextCapability=0
 958 MSIXMsgCtrl=0
 959 MSIXPbaOffset=0
 960 MSIXTableOffset=0
 961 MaximumLatency=0
 962 MinimumGrant=0
 963 PMCAPBaseOffset=0
 964 PMCAPCapId=0
 965 PMCAPCapabilities=0
 966 PMCAPCtrlStatus=0
 967 PMCAPNextCapability=0
 968 PXCAPBaseOffset=0
 969 PXCAPCapId=0
 970 PXCAPCapabilities=0
 971 PXCAPDevCap2=0
 972 PXCAPDevCapabilities=0
 973 PXCAPDevCtrl=0
 974 PXCAPDevCtrl2=0
 975 PXCAPDevStatus=0
 976 PXCAPLinkCap=0
 977 PXCAPLinkCtrl=0
 978 PXCAPLinkStatus=0
 979 PXCAPNextCapability=0
 980 ProgIF=133
 981 Revision=0
 982 Status=640
 983 SubClassCode=1
 984 SubsystemID=0
 985 SubsystemVendorID=0
 986 VendorID=32902
 987 clk_domain=system.clk_domain
 988 config_latency=20000
 989 ctrl_offset=2
 990 disks=system.cf0
 991 eventq_index=0
 992 io_shift=1
 993 pci_bus=2
 994 pci_dev=7
 995 pci_func=0
 996 pio_latency=30000
 997 platform=system.realview
 998 system=system
 999 config=system.iobus.master[8]
1000 dma=system.iobus.slave[2]
1001 pio=system.iobus.master[7]
1002
1003 [system.realview.clcd]
1004 type=Pl111
1005 amba_id=1315089
1006 clk_domain=system.clk_domain
1007 enable_capture=true
1008 eventq_index=0
1009 gic=system.realview.gic
1010 int_num=55
1011 pio_addr=268566528
1012 pio_latency=10000
1013 pixel_clock=41667
1014 system=system
1015 vnc=system.vncserver
1016 dma=system.iobus.slave[1]
1017 pio=system.iobus.master[4]
1018
1019 [system.realview.dmac_fake]
1020 type=AmbaFake
1021 amba_id=0
1022 clk_domain=system.clk_domain
1023 eventq_index=0
1024 ignore_access=false
1025 pio_addr=268632064
1026 pio_latency=100000
1027 system=system
1028 pio=system.iobus.master[9]
1029
1030 [system.realview.energy_ctrl]
1031 type=EnergyCtrl
1032 clk_domain=system.clk_domain
1033 dvfs_handler=system.dvfs_handler
1034 eventq_index=0
1035 pio_addr=268496896
1036 pio_latency=100000
1037 system=system
1038 pio=system.iobus.master[25]
1039
1040 [system.realview.flash_fake]
1041 type=IsaFake
1042 clk_domain=system.clk_domain
1043 eventq_index=0
1044 fake_mem=true
1045 pio_addr=1073741824
1046 pio_latency=100000
1047 pio_size=536870912
1048 ret_bad_addr=false
1049 ret_data16=65535
1050 ret_data32=4294967295
1051 ret_data64=18446744073709551615
1052 ret_data8=255
1053 system=system
1054 update_data=false
1055 warn_access=
1056 pio=system.iobus.master[24]
1057
1058 [system.realview.gic]
1059 type=Pl390
1060 clk_domain=system.clk_domain
1061 cpu_addr=520093952
1062 cpu_pio_delay=10000
1063 dist_addr=520097792
1064 dist_pio_delay=10000
1065 eventq_index=0
1066 int_latency=10000
1067 it_lines=128
1068 msix_addr=0
1069 platform=system.realview
1070 system=system
1071 pio=system.membus.master[2]
1072
1073 [system.realview.gpio0_fake]
1074 type=AmbaFake
1075 amba_id=0
1076 clk_domain=system.clk_domain
1077 eventq_index=0
1078 ignore_access=false
1079 pio_addr=268513280
1080 pio_latency=100000
1081 system=system
1082 pio=system.iobus.master[16]
1083
1084 [system.realview.gpio1_fake]
1085 type=AmbaFake
1086 amba_id=0
1087 clk_domain=system.clk_domain
1088 eventq_index=0
1089 ignore_access=false
1090 pio_addr=268517376
1091 pio_latency=100000
1092 system=system
1093 pio=system.iobus.master[17]
1094
1095 [system.realview.gpio2_fake]
1096 type=AmbaFake
1097 amba_id=0
1098 clk_domain=system.clk_domain
1099 eventq_index=0
1100 ignore_access=false
1101 pio_addr=268521472
1102 pio_latency=100000
1103 system=system
1104 pio=system.iobus.master[18]
1105
1106 [system.realview.kmi0]
1107 type=Pl050
1108 amba_id=1314896
1109 clk_domain=system.clk_domain
1110 eventq_index=0
1111 gic=system.realview.gic
1112 int_delay=1000000
1113 int_num=52
1114 is_mouse=false
1115 pio_addr=268460032
1116 pio_latency=100000
1117 system=system
1118 vnc=system.vncserver
1119 pio=system.iobus.master[5]
1120
1121 [system.realview.kmi1]
1122 type=Pl050
1123 amba_id=1314896
1124 clk_domain=system.clk_domain
1125 eventq_index=0
1126 gic=system.realview.gic
1127 int_delay=1000000
1128 int_num=53
1129 is_mouse=true
1130 pio_addr=268464128
1131 pio_latency=100000
1132 system=system
1133 vnc=system.vncserver
1134 pio=system.iobus.master[6]
1135
1136 [system.realview.l2x0_fake]
1137 type=IsaFake
1138 clk_domain=system.clk_domain
1139 eventq_index=0
1140 fake_mem=false
1141 pio_addr=520101888
1142 pio_latency=100000
1143 pio_size=4095
1144 ret_bad_addr=false
1145 ret_data16=65535
1146 ret_data32=4294967295
1147 ret_data64=18446744073709551615
1148 ret_data8=255
1149 system=system
1150 update_data=false
1151 warn_access=
1152 pio=system.membus.master[3]
1153
1154 [system.realview.local_cpu_timer]
1155 type=CpuLocalTimer
1156 clk_domain=system.clk_domain
1157 eventq_index=0
1158 gic=system.realview.gic
1159 int_num_timer=29
1160 int_num_watchdog=30
1161 pio_addr=520095232
1162 pio_latency=100000
1163 system=system
1164 pio=system.membus.master[5]
1165
1166 [system.realview.mmc_fake]
1167 type=AmbaFake
1168 amba_id=0
1169 clk_domain=system.clk_domain
1170 eventq_index=0
1171 ignore_access=false
1172 pio_addr=268455936
1173 pio_latency=100000
1174 system=system
1175 pio=system.iobus.master[22]
1176
1177 [system.realview.nvmem]
1178 type=SimpleMemory
1179 bandwidth=73.000000
1180 clk_domain=system.clk_domain
1181 conf_table_reported=false
1182 eventq_index=0
1183 in_addr_map=true
1184 latency=30000
1185 latency_var=0
1186 null=false
1187 range=2147483648:2214592511
1188 port=system.membus.master[1]
1189
1190 [system.realview.realview_io]
1191 type=RealViewCtrl
1192 clk_domain=system.clk_domain
1193 eventq_index=0
1194 idreg=0
1195 pio_addr=268435456
1196 pio_latency=100000
1197 proc_id0=201326592
1198 proc_id1=201327138
1199 system=system
1200 pio=system.iobus.master[1]
1201
1202 [system.realview.rtc]
1203 type=PL031
1204 amba_id=3412017
1205 clk_domain=system.clk_domain
1206 eventq_index=0
1207 gic=system.realview.gic
1208 int_delay=100000
1209 int_num=42
1210 pio_addr=268529664
1211 pio_latency=100000
1212 system=system
1213 time=Thu Jan  1 00:00:00 2009
1214 pio=system.iobus.master[23]
1215
1216 [system.realview.sci_fake]
1217 type=AmbaFake
1218 amba_id=0
1219 clk_domain=system.clk_domain
1220 eventq_index=0
1221 ignore_access=false
1222 pio_addr=268492800
1223 pio_latency=100000
1224 system=system
1225 pio=system.iobus.master[20]
1226
1227 [system.realview.smc_fake]
1228 type=AmbaFake
1229 amba_id=0
1230 clk_domain=system.clk_domain
1231 eventq_index=0
1232 ignore_access=false
1233 pio_addr=269357056
1234 pio_latency=100000
1235 system=system
1236 pio=system.iobus.master[13]
1237
1238 [system.realview.sp810_fake]
1239 type=AmbaFake
1240 amba_id=0
1241 clk_domain=system.clk_domain
1242 eventq_index=0
1243 ignore_access=true
1244 pio_addr=268439552
1245 pio_latency=100000
1246 system=system
1247 pio=system.iobus.master[14]
1248
1249 [system.realview.ssp_fake]
1250 type=AmbaFake
1251 amba_id=0
1252 clk_domain=system.clk_domain
1253 eventq_index=0
1254 ignore_access=false
1255 pio_addr=268488704
1256 pio_latency=100000
1257 system=system
1258 pio=system.iobus.master[19]
1259
1260 [system.realview.timer0]
1261 type=Sp804
1262 amba_id=1316868
1263 clk_domain=system.clk_domain
1264 clock0=1000000
1265 clock1=1000000
1266 eventq_index=0
1267 gic=system.realview.gic
1268 int_num0=36
1269 int_num1=36
1270 pio_addr=268505088
1271 pio_latency=100000
1272 system=system
1273 pio=system.iobus.master[2]
1274
1275 [system.realview.timer1]
1276 type=Sp804
1277 amba_id=1316868
1278 clk_domain=system.clk_domain
1279 clock0=1000000
1280 clock1=1000000
1281 eventq_index=0
1282 gic=system.realview.gic
1283 int_num0=37
1284 int_num1=37
1285 pio_addr=268509184
1286 pio_latency=100000
1287 system=system
1288 pio=system.iobus.master[3]
1289
1290 [system.realview.uart]
1291 type=Pl011
1292 clk_domain=system.clk_domain
1293 end_on_eot=false
1294 eventq_index=0
1295 gic=system.realview.gic
1296 int_delay=100000
1297 int_num=44
1298 pio_addr=268472320
1299 pio_latency=100000
1300 platform=system.realview
1301 system=system
1302 terminal=system.terminal
1303 pio=system.iobus.master[0]
1304
1305 [system.realview.uart1_fake]
1306 type=AmbaFake
1307 amba_id=0
1308 clk_domain=system.clk_domain
1309 eventq_index=0
1310 ignore_access=false
1311 pio_addr=268476416
1312 pio_latency=100000
1313 system=system
1314 pio=system.iobus.master[10]
1315
1316 [system.realview.uart2_fake]
1317 type=AmbaFake
1318 amba_id=0
1319 clk_domain=system.clk_domain
1320 eventq_index=0
1321 ignore_access=false
1322 pio_addr=268480512
1323 pio_latency=100000
1324 system=system
1325 pio=system.iobus.master[11]
1326
1327 [system.realview.uart3_fake]
1328 type=AmbaFake
1329 amba_id=0
1330 clk_domain=system.clk_domain
1331 eventq_index=0
1332 ignore_access=false
1333 pio_addr=268484608
1334 pio_latency=100000
1335 system=system
1336 pio=system.iobus.master[12]
1337
1338 [system.realview.watchdog_fake]
1339 type=AmbaFake
1340 amba_id=0
1341 clk_domain=system.clk_domain
1342 eventq_index=0
1343 ignore_access=false
1344 pio_addr=268500992
1345 pio_latency=100000
1346 system=system
1347 pio=system.iobus.master[15]
1348
1349 [system.terminal]
1350 type=Terminal
1351 eventq_index=0
1352 intr_control=system.intrctrl
1353 number=0
1354 output=true
1355 port=3456
1356
1357 [system.vncserver]
1358 type=VncServer
1359 eventq_index=0
1360 frame_capture=false
1361 number=0
1362 port=5900
1363
1364 [system.voltage_domain]
1365 type=VoltageDomain
1366 eventq_index=0
1367 voltage=1.000000
1368