tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=DerivO3CPU
 115 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 LFSTSize=1024
 117 LQEntries=16
 118 LSQCheckLoads=true
 119 LSQDepCheckShift=0
 120 SQEntries=16
 121 SSITSize=1024
 122 activity=0
 123 backComSize=5
 124 branchPred=system.cpu.branchPred
 125 cacheStorePorts=200
 126 checker=Null
 127 clk_domain=system.cpu_clk_domain
 128 commitToDecodeDelay=1
 129 commitToFetchDelay=1
 130 commitToIEWDelay=1
 131 commitToRenameDelay=1
 132 commitWidth=8
 133 cpu_id=0
 134 decodeToFetchDelay=1
 135 decodeToRenameDelay=2
 136 decodeWidth=3
 137 default_p_state=UNDEFINED
 138 dispatchWidth=6
 139 do_checkpoint_insts=true
 140 do_quiesce=true
 141 do_statistics_insts=true
 142 dstage2_mmu=system.cpu.dstage2_mmu
 143 dtb=system.cpu.dtb
 144 eventq_index=0
 145 fetchBufferSize=16
 146 fetchQueueSize=32
 147 fetchToDecodeDelay=3
 148 fetchTrapLatency=1
 149 fetchWidth=3
 150 forwardComSize=5
 151 fuPool=system.cpu.fuPool
 152 function_trace=false
 153 function_trace_start=0
 154 iewToCommitDelay=1
 155 iewToDecodeDelay=1
 156 iewToFetchDelay=1
 157 iewToRenameDelay=1
 158 interrupts=system.cpu.interrupts
 159 isa=system.cpu.isa
 160 issueToExecuteDelay=1
 161 issueWidth=8
 162 istage2_mmu=system.cpu.istage2_mmu
 163 itb=system.cpu.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 needsTSO=false
 169 numIQEntries=32
 170 numPhysCCRegs=640
 171 numPhysFloatRegs=192
 172 numPhysIntRegs=128
 173 numROBEntries=40
 174 numRobs=1
 175 numThreads=1
 176 p_state_clk_gate_bins=20
 177 p_state_clk_gate_max=1000000000000
 178 p_state_clk_gate_min=1000
 179 power_model=Null
 180 profile=0
 181 progress_interval=0
 182 renameToDecodeDelay=1
 183 renameToFetchDelay=1
 184 renameToIEWDelay=1
 185 renameToROBDelay=1
 186 renameWidth=3
 187 simpoint_start_insts=
 188 smtCommitPolicy=RoundRobin
 189 smtFetchPolicy=SingleThread
 190 smtIQPolicy=Partitioned
 191 smtIQThreshold=100
 192 smtLSQPolicy=Partitioned
 193 smtLSQThreshold=100
 194 smtNumFetchingThreads=1
 195 smtROBPolicy=Partitioned
 196 smtROBThreshold=100
 197 socket_id=0
 198 squashWidth=8
 199 store_set_clear_period=250000
 200 switched_out=false
 201 syscallRetryLatency=10000
 202 system=system
 203 tracer=system.cpu.tracer
 204 trapLatency=13
 205 wbWidth=8
 206 workload=
 207 dcache_port=system.cpu.dcache.cpu_side
 208 icache_port=system.cpu.icache.cpu_side
 209
 210 [system.cpu.branchPred]
 211 type=BiModeBP
 212 BTBEntries=2048
 213 BTBTagSize=18
 214 RASSize=16
 215 choiceCtrBits=2
 216 choicePredictorSize=8192
 217 eventq_index=0
 218 globalCtrBits=2
 219 globalPredictorSize=8192
 220 indirectHashGHR=true
 221 indirectHashTargets=true
 222 indirectPathLength=3
 223 indirectSets=256
 224 indirectTagSize=16
 225 indirectWays=2
 226 instShiftAmt=2
 227 numThreads=1
 228 useIndirect=true
 229
 230 [system.cpu.dcache]
 231 type=Cache
 232 children=tags
 233 addr_ranges=0:18446744073709551615:0:0:0:0
 234 assoc=4
 235 clk_domain=system.cpu_clk_domain
 236 clusivity=mostly_incl
 237 data_latency=2
 238 default_p_state=UNDEFINED
 239 demand_mshr_reserve=1
 240 eventq_index=0
 241 is_read_only=false
 242 max_miss_count=0
 243 mshrs=4
 244 p_state_clk_gate_bins=20
 245 p_state_clk_gate_max=1000000000000
 246 p_state_clk_gate_min=1000
 247 power_model=Null
 248 prefetch_on_access=false
 249 prefetcher=Null
 250 response_latency=2
 251 sequential_access=false
 252 size=32768
 253 system=system
 254 tag_latency=2
 255 tags=system.cpu.dcache.tags
 256 tgts_per_mshr=20
 257 write_buffers=8
 258 writeback_clean=false
 259 cpu_side=system.cpu.dcache_port
 260 mem_side=system.cpu.toL2Bus.slave[1]
 261
 262 [system.cpu.dcache.tags]
 263 type=LRU
 264 assoc=4
 265 block_size=64
 266 clk_domain=system.cpu_clk_domain
 267 data_latency=2
 268 default_p_state=UNDEFINED
 269 eventq_index=0
 270 p_state_clk_gate_bins=20
 271 p_state_clk_gate_max=1000000000000
 272 p_state_clk_gate_min=1000
 273 power_model=Null
 274 sequential_access=false
 275 size=32768
 276 tag_latency=2
 277
 278 [system.cpu.dstage2_mmu]
 279 type=ArmStage2MMU
 280 children=stage2_tlb
 281 eventq_index=0
 282 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 283 sys=system
 284 tlb=system.cpu.dtb
 285
 286 [system.cpu.dstage2_mmu.stage2_tlb]
 287 type=ArmTLB
 288 children=walker
 289 eventq_index=0
 290 is_stage2=true
 291 size=32
 292 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 293
 294 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 295 type=ArmTableWalker
 296 clk_domain=system.cpu_clk_domain
 297 default_p_state=UNDEFINED
 298 eventq_index=0
 299 is_stage2=true
 300 num_squash_per_cycle=2
 301 p_state_clk_gate_bins=20
 302 p_state_clk_gate_max=1000000000000
 303 p_state_clk_gate_min=1000
 304 power_model=Null
 305 sys=system
 306
 307 [system.cpu.dtb]
 308 type=ArmTLB
 309 children=walker
 310 eventq_index=0
 311 is_stage2=false
 312 size=64
 313 walker=system.cpu.dtb.walker
 314
 315 [system.cpu.dtb.walker]
 316 type=ArmTableWalker
 317 clk_domain=system.cpu_clk_domain
 318 default_p_state=UNDEFINED
 319 eventq_index=0
 320 is_stage2=false
 321 num_squash_per_cycle=2
 322 p_state_clk_gate_bins=20
 323 p_state_clk_gate_max=1000000000000
 324 p_state_clk_gate_min=1000
 325 power_model=Null
 326 sys=system
 327 port=system.cpu.toL2Bus.slave[3]
 328
 329 [system.cpu.fuPool]
 330 type=FUPool
 331 children=FUList0 FUList1 FUList2 FUList3 FUList4
 332 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 333 eventq_index=0
 334
 335 [system.cpu.fuPool.FUList0]
 336 type=FUDesc
 337 children=opList
 338 count=2
 339 eventq_index=0
 340 opList=system.cpu.fuPool.FUList0.opList
 341
 342 [system.cpu.fuPool.FUList0.opList]
 343 type=OpDesc
 344 eventq_index=0
 345 opClass=IntAlu
 346 opLat=1
 347 pipelined=true
 348
 349 [system.cpu.fuPool.FUList1]
 350 type=FUDesc
 351 children=opList0 opList1 opList2
 352 count=1
 353 eventq_index=0
 354 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 355
 356 [system.cpu.fuPool.FUList1.opList0]
 357 type=OpDesc
 358 eventq_index=0
 359 opClass=IntMult
 360 opLat=3
 361 pipelined=true
 362
 363 [system.cpu.fuPool.FUList1.opList1]
 364 type=OpDesc
 365 eventq_index=0
 366 opClass=IntDiv
 367 opLat=12
 368 pipelined=false
 369
 370 [system.cpu.fuPool.FUList1.opList2]
 371 type=OpDesc
 372 eventq_index=0
 373 opClass=IprAccess
 374 opLat=3
 375 pipelined=true
 376
 377 [system.cpu.fuPool.FUList2]
 378 type=FUDesc
 379 children=opList0 opList1
 380 count=1
 381 eventq_index=0
 382 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
 383
 384 [system.cpu.fuPool.FUList2.opList0]
 385 type=OpDesc
 386 eventq_index=0
 387 opClass=MemRead
 388 opLat=2
 389 pipelined=true
 390
 391 [system.cpu.fuPool.FUList2.opList1]
 392 type=OpDesc
 393 eventq_index=0
 394 opClass=FloatMemRead
 395 opLat=2
 396 pipelined=true
 397
 398 [system.cpu.fuPool.FUList3]
 399 type=FUDesc
 400 children=opList0 opList1
 401 count=1
 402 eventq_index=0
 403 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
 404
 405 [system.cpu.fuPool.FUList3.opList0]
 406 type=OpDesc
 407 eventq_index=0
 408 opClass=MemWrite
 409 opLat=2
 410 pipelined=true
 411
 412 [system.cpu.fuPool.FUList3.opList1]
 413 type=OpDesc
 414 eventq_index=0
 415 opClass=FloatMemWrite
 416 opLat=2
 417 pipelined=true
 418
 419 [system.cpu.fuPool.FUList4]
 420 type=FUDesc
 421 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
 422 count=2
 423 eventq_index=0
 424 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
 425
 426 [system.cpu.fuPool.FUList4.opList00]
 427 type=OpDesc
 428 eventq_index=0
 429 opClass=SimdAdd
 430 opLat=4
 431 pipelined=true
 432
 433 [system.cpu.fuPool.FUList4.opList01]
 434 type=OpDesc
 435 eventq_index=0
 436 opClass=SimdAddAcc
 437 opLat=4
 438 pipelined=true
 439
 440 [system.cpu.fuPool.FUList4.opList02]
 441 type=OpDesc
 442 eventq_index=0
 443 opClass=SimdAlu
 444 opLat=4
 445 pipelined=true
 446
 447 [system.cpu.fuPool.FUList4.opList03]
 448 type=OpDesc
 449 eventq_index=0
 450 opClass=SimdCmp
 451 opLat=4
 452 pipelined=true
 453
 454 [system.cpu.fuPool.FUList4.opList04]
 455 type=OpDesc
 456 eventq_index=0
 457 opClass=SimdCvt
 458 opLat=3
 459 pipelined=true
 460
 461 [system.cpu.fuPool.FUList4.opList05]
 462 type=OpDesc
 463 eventq_index=0
 464 opClass=SimdMisc
 465 opLat=3
 466 pipelined=true
 467
 468 [system.cpu.fuPool.FUList4.opList06]
 469 type=OpDesc
 470 eventq_index=0
 471 opClass=SimdMult
 472 opLat=5
 473 pipelined=true
 474
 475 [system.cpu.fuPool.FUList4.opList07]
 476 type=OpDesc
 477 eventq_index=0
 478 opClass=SimdMultAcc
 479 opLat=5
 480 pipelined=true
 481
 482 [system.cpu.fuPool.FUList4.opList08]
 483 type=OpDesc
 484 eventq_index=0
 485 opClass=SimdShift
 486 opLat=3
 487 pipelined=true
 488
 489 [system.cpu.fuPool.FUList4.opList09]
 490 type=OpDesc
 491 eventq_index=0
 492 opClass=SimdShiftAcc
 493 opLat=3
 494 pipelined=true
 495
 496 [system.cpu.fuPool.FUList4.opList10]
 497 type=OpDesc
 498 eventq_index=0
 499 opClass=SimdSqrt
 500 opLat=9
 501 pipelined=true
 502
 503 [system.cpu.fuPool.FUList4.opList11]
 504 type=OpDesc
 505 eventq_index=0
 506 opClass=SimdFloatAdd
 507 opLat=5
 508 pipelined=true
 509
 510 [system.cpu.fuPool.FUList4.opList12]
 511 type=OpDesc
 512 eventq_index=0
 513 opClass=SimdFloatAlu
 514 opLat=5
 515 pipelined=true
 516
 517 [system.cpu.fuPool.FUList4.opList13]
 518 type=OpDesc
 519 eventq_index=0
 520 opClass=SimdFloatCmp
 521 opLat=3
 522 pipelined=true
 523
 524 [system.cpu.fuPool.FUList4.opList14]
 525 type=OpDesc
 526 eventq_index=0
 527 opClass=SimdFloatCvt
 528 opLat=3
 529 pipelined=true
 530
 531 [system.cpu.fuPool.FUList4.opList15]
 532 type=OpDesc
 533 eventq_index=0
 534 opClass=SimdFloatDiv
 535 opLat=3
 536 pipelined=true
 537
 538 [system.cpu.fuPool.FUList4.opList16]
 539 type=OpDesc
 540 eventq_index=0
 541 opClass=SimdFloatMisc
 542 opLat=3
 543 pipelined=true
 544
 545 [system.cpu.fuPool.FUList4.opList17]
 546 type=OpDesc
 547 eventq_index=0
 548 opClass=SimdFloatMult
 549 opLat=3
 550 pipelined=true
 551
 552 [system.cpu.fuPool.FUList4.opList18]
 553 type=OpDesc
 554 eventq_index=0
 555 opClass=SimdFloatMultAcc
 556 opLat=5
 557 pipelined=true
 558
 559 [system.cpu.fuPool.FUList4.opList19]
 560 type=OpDesc
 561 eventq_index=0
 562 opClass=SimdFloatSqrt
 563 opLat=9
 564 pipelined=true
 565
 566 [system.cpu.fuPool.FUList4.opList20]
 567 type=OpDesc
 568 eventq_index=0
 569 opClass=FloatAdd
 570 opLat=5
 571 pipelined=true
 572
 573 [system.cpu.fuPool.FUList4.opList21]
 574 type=OpDesc
 575 eventq_index=0
 576 opClass=FloatCmp
 577 opLat=5
 578 pipelined=true
 579
 580 [system.cpu.fuPool.FUList4.opList22]
 581 type=OpDesc
 582 eventq_index=0
 583 opClass=FloatCvt
 584 opLat=5
 585 pipelined=true
 586
 587 [system.cpu.fuPool.FUList4.opList23]
 588 type=OpDesc
 589 eventq_index=0
 590 opClass=FloatDiv
 591 opLat=9
 592 pipelined=false
 593
 594 [system.cpu.fuPool.FUList4.opList24]
 595 type=OpDesc
 596 eventq_index=0
 597 opClass=FloatSqrt
 598 opLat=33
 599 pipelined=false
 600
 601 [system.cpu.fuPool.FUList4.opList25]
 602 type=OpDesc
 603 eventq_index=0
 604 opClass=FloatMult
 605 opLat=4
 606 pipelined=true
 607
 608 [system.cpu.fuPool.FUList4.opList26]
 609 type=OpDesc
 610 eventq_index=0
 611 opClass=FloatMultAcc
 612 opLat=5
 613 pipelined=true
 614
 615 [system.cpu.fuPool.FUList4.opList27]
 616 type=OpDesc
 617 eventq_index=0
 618 opClass=FloatMisc
 619 opLat=3
 620 pipelined=true
 621
 622 [system.cpu.icache]
 623 type=Cache
 624 children=tags
 625 addr_ranges=0:18446744073709551615:0:0:0:0
 626 assoc=1
 627 clk_domain=system.cpu_clk_domain
 628 clusivity=mostly_incl
 629 data_latency=2
 630 default_p_state=UNDEFINED
 631 demand_mshr_reserve=1
 632 eventq_index=0
 633 is_read_only=true
 634 max_miss_count=0
 635 mshrs=4
 636 p_state_clk_gate_bins=20
 637 p_state_clk_gate_max=1000000000000
 638 p_state_clk_gate_min=1000
 639 power_model=Null
 640 prefetch_on_access=false
 641 prefetcher=Null
 642 response_latency=2
 643 sequential_access=false
 644 size=32768
 645 system=system
 646 tag_latency=2
 647 tags=system.cpu.icache.tags
 648 tgts_per_mshr=20
 649 write_buffers=8
 650 writeback_clean=true
 651 cpu_side=system.cpu.icache_port
 652 mem_side=system.cpu.toL2Bus.slave[0]
 653
 654 [system.cpu.icache.tags]
 655 type=LRU
 656 assoc=1
 657 block_size=64
 658 clk_domain=system.cpu_clk_domain
 659 data_latency=2
 660 default_p_state=UNDEFINED
 661 eventq_index=0
 662 p_state_clk_gate_bins=20
 663 p_state_clk_gate_max=1000000000000
 664 p_state_clk_gate_min=1000
 665 power_model=Null
 666 sequential_access=false
 667 size=32768
 668 tag_latency=2
 669
 670 [system.cpu.interrupts]
 671 type=ArmInterrupts
 672 eventq_index=0
 673
 674 [system.cpu.isa]
 675 type=ArmISA
 676 decoderFlavour=Generic
 677 eventq_index=0
 678 fpsid=1090793632
 679 id_aa64afr0_el1=0
 680 id_aa64afr1_el1=0
 681 id_aa64dfr0_el1=1052678
 682 id_aa64dfr1_el1=0
 683 id_aa64isar0_el1=0
 684 id_aa64isar1_el1=0
 685 id_aa64mmfr0_el1=15728642
 686 id_aa64mmfr1_el1=0
 687 id_isar0=34607377
 688 id_isar1=34677009
 689 id_isar2=555950401
 690 id_isar3=17899825
 691 id_isar4=268501314
 692 id_isar5=0
 693 id_mmfr0=270536963
 694 id_mmfr1=0
 695 id_mmfr2=19070976
 696 id_mmfr3=34611729
 697 midr=1091551472
 698 pmu=Null
 699 system=system
 700
 701 [system.cpu.istage2_mmu]
 702 type=ArmStage2MMU
 703 children=stage2_tlb
 704 eventq_index=0
 705 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 706 sys=system
 707 tlb=system.cpu.itb
 708
 709 [system.cpu.istage2_mmu.stage2_tlb]
 710 type=ArmTLB
 711 children=walker
 712 eventq_index=0
 713 is_stage2=true
 714 size=32
 715 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 716
 717 [system.cpu.istage2_mmu.stage2_tlb.walker]
 718 type=ArmTableWalker
 719 clk_domain=system.cpu_clk_domain
 720 default_p_state=UNDEFINED
 721 eventq_index=0
 722 is_stage2=true
 723 num_squash_per_cycle=2
 724 p_state_clk_gate_bins=20
 725 p_state_clk_gate_max=1000000000000
 726 p_state_clk_gate_min=1000
 727 power_model=Null
 728 sys=system
 729
 730 [system.cpu.itb]
 731 type=ArmTLB
 732 children=walker
 733 eventq_index=0
 734 is_stage2=false
 735 size=64
 736 walker=system.cpu.itb.walker
 737
 738 [system.cpu.itb.walker]
 739 type=ArmTableWalker
 740 clk_domain=system.cpu_clk_domain
 741 default_p_state=UNDEFINED
 742 eventq_index=0
 743 is_stage2=false
 744 num_squash_per_cycle=2
 745 p_state_clk_gate_bins=20
 746 p_state_clk_gate_max=1000000000000
 747 p_state_clk_gate_min=1000
 748 power_model=Null
 749 sys=system
 750 port=system.cpu.toL2Bus.slave[2]
 751
 752 [system.cpu.l2cache]
 753 type=Cache
 754 children=tags
 755 addr_ranges=0:18446744073709551615:0:0:0:0
 756 assoc=8
 757 clk_domain=system.cpu_clk_domain
 758 clusivity=mostly_incl
 759 data_latency=20
 760 default_p_state=UNDEFINED
 761 demand_mshr_reserve=1
 762 eventq_index=0
 763 is_read_only=false
 764 max_miss_count=0
 765 mshrs=20
 766 p_state_clk_gate_bins=20
 767 p_state_clk_gate_max=1000000000000
 768 p_state_clk_gate_min=1000
 769 power_model=Null
 770 prefetch_on_access=false
 771 prefetcher=Null
 772 response_latency=20
 773 sequential_access=false
 774 size=4194304
 775 system=system
 776 tag_latency=20
 777 tags=system.cpu.l2cache.tags
 778 tgts_per_mshr=12
 779 write_buffers=8
 780 writeback_clean=false
 781 cpu_side=system.cpu.toL2Bus.master[0]
 782 mem_side=system.membus.slave[2]
 783
 784 [system.cpu.l2cache.tags]
 785 type=LRU
 786 assoc=8
 787 block_size=64
 788 clk_domain=system.cpu_clk_domain
 789 data_latency=20
 790 default_p_state=UNDEFINED
 791 eventq_index=0
 792 p_state_clk_gate_bins=20
 793 p_state_clk_gate_max=1000000000000
 794 p_state_clk_gate_min=1000
 795 power_model=Null
 796 sequential_access=false
 797 size=4194304
 798 tag_latency=20
 799
 800 [system.cpu.toL2Bus]
 801 type=CoherentXBar
 802 children=snoop_filter
 803 clk_domain=system.cpu_clk_domain
 804 default_p_state=UNDEFINED
 805 eventq_index=0
 806 forward_latency=0
 807 frontend_latency=1
 808 p_state_clk_gate_bins=20
 809 p_state_clk_gate_max=1000000000000
 810 p_state_clk_gate_min=1000
 811 point_of_coherency=false
 812 power_model=Null
 813 response_latency=1
 814 snoop_filter=system.cpu.toL2Bus.snoop_filter
 815 snoop_response_latency=1
 816 system=system
 817 use_default_range=false
 818 width=32
 819 master=system.cpu.l2cache.cpu_side
 820 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 821
 822 [system.cpu.toL2Bus.snoop_filter]
 823 type=SnoopFilter
 824 eventq_index=0
 825 lookup_latency=0
 826 max_capacity=8388608
 827 system=system
 828
 829 [system.cpu.tracer]
 830 type=ExeTracer
 831 eventq_index=0
 832
 833 [system.cpu_clk_domain]
 834 type=SrcClockDomain
 835 clock=500
 836 domain_id=-1
 837 eventq_index=0
 838 init_perf_level=0
 839 voltage_domain=system.voltage_domain
 840
 841 [system.dvfs_handler]
 842 type=DVFSHandler
 843 domains=
 844 enable=false
 845 eventq_index=0
 846 sys_clk_domain=system.clk_domain
 847 transition_latency=100000000
 848
 849 [system.intrctrl]
 850 type=IntrControl
 851 eventq_index=0
 852 sys=system
 853
 854 [system.iobus]
 855 type=NoncoherentXBar
 856 clk_domain=system.clk_domain
 857 default_p_state=UNDEFINED
 858 eventq_index=0
 859 forward_latency=1
 860 frontend_latency=2
 861 p_state_clk_gate_bins=20
 862 p_state_clk_gate_max=1000000000000
 863 p_state_clk_gate_min=1000
 864 power_model=Null
 865 response_latency=2
 866 use_default_range=false
 867 width=16
 868 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 869 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 870
 871 [system.iocache]
 872 type=Cache
 873 children=tags
 874 addr_ranges=2147483648:2415919103:0:0:0:0
 875 assoc=8
 876 clk_domain=system.clk_domain
 877 clusivity=mostly_incl
 878 data_latency=50
 879 default_p_state=UNDEFINED
 880 demand_mshr_reserve=1
 881 eventq_index=0
 882 is_read_only=false
 883 max_miss_count=0
 884 mshrs=20
 885 p_state_clk_gate_bins=20
 886 p_state_clk_gate_max=1000000000000
 887 p_state_clk_gate_min=1000
 888 power_model=Null
 889 prefetch_on_access=false
 890 prefetcher=Null
 891 response_latency=50
 892 sequential_access=false
 893 size=1024
 894 system=system
 895 tag_latency=50
 896 tags=system.iocache.tags
 897 tgts_per_mshr=12
 898 write_buffers=8
 899 writeback_clean=false
 900 cpu_side=system.iobus.master[25]
 901 mem_side=system.membus.slave[3]
 902
 903 [system.iocache.tags]
 904 type=LRU
 905 assoc=8
 906 block_size=64
 907 clk_domain=system.clk_domain
 908 data_latency=50
 909 default_p_state=UNDEFINED
 910 eventq_index=0
 911 p_state_clk_gate_bins=20
 912 p_state_clk_gate_max=1000000000000
 913 p_state_clk_gate_min=1000
 914 power_model=Null
 915 sequential_access=false
 916 size=1024
 917 tag_latency=50
 918
 919 [system.membus]
 920 type=CoherentXBar
 921 children=badaddr_responder snoop_filter
 922 clk_domain=system.clk_domain
 923 default_p_state=UNDEFINED
 924 eventq_index=0
 925 forward_latency=4
 926 frontend_latency=3
 927 p_state_clk_gate_bins=20
 928 p_state_clk_gate_max=1000000000000
 929 p_state_clk_gate_min=1000
 930 point_of_coherency=true
 931 power_model=Null
 932 response_latency=2
 933 snoop_filter=system.membus.snoop_filter
 934 snoop_response_latency=4
 935 system=system
 936 use_default_range=false
 937 width=16
 938 default=system.membus.badaddr_responder.pio
 939 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 940 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 941
 942 [system.membus.badaddr_responder]
 943 type=IsaFake
 944 clk_domain=system.clk_domain
 945 default_p_state=UNDEFINED
 946 eventq_index=0
 947 fake_mem=false
 948 p_state_clk_gate_bins=20
 949 p_state_clk_gate_max=1000000000000
 950 p_state_clk_gate_min=1000
 951 pio_addr=0
 952 pio_latency=100000
 953 pio_size=8
 954 power_model=Null
 955 ret_bad_addr=true
 956 ret_data16=65535
 957 ret_data32=4294967295
 958 ret_data64=18446744073709551615
 959 ret_data8=255
 960 system=system
 961 update_data=false
 962 warn_access=warn
 963 pio=system.membus.default
 964
 965 [system.membus.snoop_filter]
 966 type=SnoopFilter
 967 eventq_index=0
 968 lookup_latency=1
 969 max_capacity=8388608
 970 system=system
 971
 972 [system.physmem]
 973 type=DRAMCtrl
 974 IDD0=0.055000
 975 IDD02=0.000000
 976 IDD2N=0.032000
 977 IDD2N2=0.000000
 978 IDD2P0=0.000000
 979 IDD2P02=0.000000
 980 IDD2P1=0.032000
 981 IDD2P12=0.000000
 982 IDD3N=0.038000
 983 IDD3N2=0.000000
 984 IDD3P0=0.000000
 985 IDD3P02=0.000000
 986 IDD3P1=0.038000
 987 IDD3P12=0.000000
 988 IDD4R=0.157000
 989 IDD4R2=0.000000
 990 IDD4W=0.125000
 991 IDD4W2=0.000000
 992 IDD5=0.235000
 993 IDD52=0.000000
 994 IDD6=0.020000
 995 IDD62=0.000000
 996 VDD=1.500000
 997 VDD2=0.000000
 998 activation_limit=4
 999 addr_mapping=RoRaBaCoCh
1000 bank_groups_per_rank=0
1001 banks_per_rank=8
1002 burst_length=8
1003 channels=1
1004 clk_domain=system.clk_domain
1005 conf_table_reported=true
1006 default_p_state=UNDEFINED
1007 device_bus_width=8
1008 device_rowbuffer_size=1024
1009 device_size=536870912
1010 devices_per_rank=8
1011 dll=true
1012 eventq_index=0
1013 in_addr_map=true
1014 kvm_map=true
1015 max_accesses_per_row=16
1016 mem_sched_policy=frfcfs
1017 min_writes_per_switch=16
1018 null=false
1019 p_state_clk_gate_bins=20
1020 p_state_clk_gate_max=1000000000000
1021 p_state_clk_gate_min=1000
1022 page_policy=open_adaptive
1023 power_model=Null
1024 range=2147483648:2415919103:0:0:0:0
1025 ranks_per_channel=2
1026 read_buffer_size=32
1027 static_backend_latency=10000
1028 static_frontend_latency=10000
1029 tBURST=5000
1030 tCCD_L=0
1031 tCK=1250
1032 tCL=13750
1033 tCS=2500
1034 tRAS=35000
1035 tRCD=13750
1036 tREFI=7800000
1037 tRFC=260000
1038 tRP=13750
1039 tRRD=6000
1040 tRRD_L=0
1041 tRTP=7500
1042 tRTW=2500
1043 tWR=15000
1044 tWTR=7500
1045 tXAW=30000
1046 tXP=6000
1047 tXPDLL=0
1048 tXS=270000
1049 tXSDLL=0
1050 write_buffer_size=64
1051 write_high_thresh_perc=85
1052 write_low_thresh_perc=50
1053 port=system.membus.master[5]
1054
1055 [system.realview]
1056 type=RealView
1057 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1058 eventq_index=0
1059 intrctrl=system.intrctrl
1060 system=system
1061
1062 [system.realview.aaci_fake]
1063 type=AmbaFake
1064 amba_id=0
1065 clk_domain=system.clk_domain
1066 default_p_state=UNDEFINED
1067 eventq_index=0
1068 ignore_access=false
1069 p_state_clk_gate_bins=20
1070 p_state_clk_gate_max=1000000000000
1071 p_state_clk_gate_min=1000
1072 pio_addr=470024192
1073 pio_latency=100000
1074 power_model=Null
1075 system=system
1076 pio=system.iobus.master[18]
1077
1078 [system.realview.cf_ctrl]
1079 type=IdeController
1080 BAR0=471465984
1081 BAR0LegacyIO=true
1082 BAR0Size=256
1083 BAR1=471466240
1084 BAR1LegacyIO=true
1085 BAR1Size=4096
1086 BAR2=1
1087 BAR2LegacyIO=false
1088 BAR2Size=8
1089 BAR3=1
1090 BAR3LegacyIO=false
1091 BAR3Size=4
1092 BAR4=1
1093 BAR4LegacyIO=false
1094 BAR4Size=16
1095 BAR5=1
1096 BAR5LegacyIO=false
1097 BAR5Size=0
1098 BIST=0
1099 CacheLineSize=0
1100 CapabilityPtr=0
1101 CardbusCIS=0
1102 ClassCode=1
1103 Command=1
1104 DeviceID=28945
1105 ExpansionROM=0
1106 HeaderType=0
1107 InterruptLine=31
1108 InterruptPin=1
1109 LatencyTimer=0
1110 LegacyIOBase=0
1111 MSICAPBaseOffset=0
1112 MSICAPCapId=0
1113 MSICAPMaskBits=0
1114 MSICAPMsgAddr=0
1115 MSICAPMsgCtrl=0
1116 MSICAPMsgData=0
1117 MSICAPMsgUpperAddr=0
1118 MSICAPNextCapability=0
1119 MSICAPPendingBits=0
1120 MSIXCAPBaseOffset=0
1121 MSIXCAPCapId=0
1122 MSIXCAPNextCapability=0
1123 MSIXMsgCtrl=0
1124 MSIXPbaOffset=0
1125 MSIXTableOffset=0
1126 MaximumLatency=0
1127 MinimumGrant=0
1128 PMCAPBaseOffset=0
1129 PMCAPCapId=0
1130 PMCAPCapabilities=0
1131 PMCAPCtrlStatus=0
1132 PMCAPNextCapability=0
1133 PXCAPBaseOffset=0
1134 PXCAPCapId=0
1135 PXCAPCapabilities=0
1136 PXCAPDevCap2=0
1137 PXCAPDevCapabilities=0
1138 PXCAPDevCtrl=0
1139 PXCAPDevCtrl2=0
1140 PXCAPDevStatus=0
1141 PXCAPLinkCap=0
1142 PXCAPLinkCtrl=0
1143 PXCAPLinkStatus=0
1144 PXCAPNextCapability=0
1145 ProgIF=133
1146 Revision=0
1147 Status=640
1148 SubClassCode=1
1149 SubsystemID=0
1150 SubsystemVendorID=0
1151 VendorID=32902
1152 clk_domain=system.clk_domain
1153 config_latency=20000
1154 ctrl_offset=2
1155 default_p_state=UNDEFINED
1156 disks=
1157 eventq_index=0
1158 host=system.realview.pci_host
1159 io_shift=2
1160 p_state_clk_gate_bins=20
1161 p_state_clk_gate_max=1000000000000
1162 p_state_clk_gate_min=1000
1163 pci_bus=2
1164 pci_dev=0
1165 pci_func=0
1166 pio_latency=30000
1167 power_model=Null
1168 system=system
1169 dma=system.iobus.slave[2]
1170 pio=system.iobus.master[9]
1171
1172 [system.realview.clcd]
1173 type=Pl111
1174 amba_id=1315089
1175 clk_domain=system.clk_domain
1176 default_p_state=UNDEFINED
1177 enable_capture=true
1178 eventq_index=0
1179 gic=system.realview.gic
1180 int_num=46
1181 p_state_clk_gate_bins=20
1182 p_state_clk_gate_max=1000000000000
1183 p_state_clk_gate_min=1000
1184 pio_addr=471793664
1185 pio_latency=10000
1186 pixel_clock=41667
1187 power_model=Null
1188 system=system
1189 vnc=system.vncserver
1190 dma=system.iobus.slave[1]
1191 pio=system.iobus.master[5]
1192
1193 [system.realview.dcc]
1194 type=SubSystem
1195 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1196 eventq_index=0
1197 thermal_domain=Null
1198
1199 [system.realview.dcc.osc_cpu]
1200 type=RealViewOsc
1201 dcc=0
1202 device=0
1203 eventq_index=0
1204 freq=16667
1205 parent=system.realview.realview_io
1206 position=0
1207 site=1
1208 voltage_domain=system.voltage_domain
1209
1210 [system.realview.dcc.osc_ddr]
1211 type=RealViewOsc
1212 dcc=0
1213 device=8
1214 eventq_index=0
1215 freq=25000
1216 parent=system.realview.realview_io
1217 position=0
1218 site=1
1219 voltage_domain=system.voltage_domain
1220
1221 [system.realview.dcc.osc_hsbm]
1222 type=RealViewOsc
1223 dcc=0
1224 device=4
1225 eventq_index=0
1226 freq=25000
1227 parent=system.realview.realview_io
1228 position=0
1229 site=1
1230 voltage_domain=system.voltage_domain
1231
1232 [system.realview.dcc.osc_pxl]
1233 type=RealViewOsc
1234 dcc=0
1235 device=5
1236 eventq_index=0
1237 freq=42105
1238 parent=system.realview.realview_io
1239 position=0
1240 site=1
1241 voltage_domain=system.voltage_domain
1242
1243 [system.realview.dcc.osc_smb]
1244 type=RealViewOsc
1245 dcc=0
1246 device=6
1247 eventq_index=0
1248 freq=20000
1249 parent=system.realview.realview_io
1250 position=0
1251 site=1
1252 voltage_domain=system.voltage_domain
1253
1254 [system.realview.dcc.osc_sys]
1255 type=RealViewOsc
1256 dcc=0
1257 device=7
1258 eventq_index=0
1259 freq=16667
1260 parent=system.realview.realview_io
1261 position=0
1262 site=1
1263 voltage_domain=system.voltage_domain
1264
1265 [system.realview.energy_ctrl]
1266 type=EnergyCtrl
1267 clk_domain=system.clk_domain
1268 default_p_state=UNDEFINED
1269 dvfs_handler=system.dvfs_handler
1270 eventq_index=0
1271 p_state_clk_gate_bins=20
1272 p_state_clk_gate_max=1000000000000
1273 p_state_clk_gate_min=1000
1274 pio_addr=470286336
1275 pio_latency=100000
1276 power_model=Null
1277 system=system
1278 pio=system.iobus.master[22]
1279
1280 [system.realview.ethernet]
1281 type=IGbE
1282 BAR0=0
1283 BAR0LegacyIO=false
1284 BAR0Size=131072
1285 BAR1=0
1286 BAR1LegacyIO=false
1287 BAR1Size=0
1288 BAR2=0
1289 BAR2LegacyIO=false
1290 BAR2Size=0
1291 BAR3=0
1292 BAR3LegacyIO=false
1293 BAR3Size=0
1294 BAR4=0
1295 BAR4LegacyIO=false
1296 BAR4Size=0
1297 BAR5=0
1298 BAR5LegacyIO=false
1299 BAR5Size=0
1300 BIST=0
1301 CacheLineSize=0
1302 CapabilityPtr=0
1303 CardbusCIS=0
1304 ClassCode=2
1305 Command=0
1306 DeviceID=4213
1307 ExpansionROM=0
1308 HeaderType=0
1309 InterruptLine=1
1310 InterruptPin=1
1311 LatencyTimer=0
1312 LegacyIOBase=0
1313 MSICAPBaseOffset=0
1314 MSICAPCapId=0
1315 MSICAPMaskBits=0
1316 MSICAPMsgAddr=0
1317 MSICAPMsgCtrl=0
1318 MSICAPMsgData=0
1319 MSICAPMsgUpperAddr=0
1320 MSICAPNextCapability=0
1321 MSICAPPendingBits=0
1322 MSIXCAPBaseOffset=0
1323 MSIXCAPCapId=0
1324 MSIXCAPNextCapability=0
1325 MSIXMsgCtrl=0
1326 MSIXPbaOffset=0
1327 MSIXTableOffset=0
1328 MaximumLatency=0
1329 MinimumGrant=255
1330 PMCAPBaseOffset=0
1331 PMCAPCapId=0
1332 PMCAPCapabilities=0
1333 PMCAPCtrlStatus=0
1334 PMCAPNextCapability=0
1335 PXCAPBaseOffset=0
1336 PXCAPCapId=0
1337 PXCAPCapabilities=0
1338 PXCAPDevCap2=0
1339 PXCAPDevCapabilities=0
1340 PXCAPDevCtrl=0
1341 PXCAPDevCtrl2=0
1342 PXCAPDevStatus=0
1343 PXCAPLinkCap=0
1344 PXCAPLinkCtrl=0
1345 PXCAPLinkStatus=0
1346 PXCAPNextCapability=0
1347 ProgIF=0
1348 Revision=0
1349 Status=0
1350 SubClassCode=0
1351 SubsystemID=4104
1352 SubsystemVendorID=32902
1353 VendorID=32902
1354 clk_domain=system.clk_domain
1355 config_latency=20000
1356 default_p_state=UNDEFINED
1357 eventq_index=0
1358 fetch_comp_delay=10000
1359 fetch_delay=10000
1360 hardware_address=00:90:00:00:00:01
1361 host=system.realview.pci_host
1362 p_state_clk_gate_bins=20
1363 p_state_clk_gate_max=1000000000000
1364 p_state_clk_gate_min=1000
1365 pci_bus=0
1366 pci_dev=0
1367 pci_func=0
1368 phy_epid=896
1369 phy_pid=680
1370 pio_latency=30000
1371 power_model=Null
1372 rx_desc_cache_size=64
1373 rx_fifo_size=393216
1374 rx_write_delay=0
1375 system=system
1376 tx_desc_cache_size=64
1377 tx_fifo_size=393216
1378 tx_read_delay=0
1379 wb_comp_delay=10000
1380 wb_delay=10000
1381 dma=system.iobus.slave[4]
1382 pio=system.iobus.master[24]
1383
1384 [system.realview.generic_timer]
1385 type=GenericTimer
1386 eventq_index=0
1387 gic=system.realview.gic
1388 int_phys=29
1389 int_virt=27
1390 system=system
1391
1392 [system.realview.gic]
1393 type=Pl390
1394 clk_domain=system.clk_domain
1395 cpu_addr=738205696
1396 cpu_pio_delay=10000
1397 default_p_state=UNDEFINED
1398 dist_addr=738201600
1399 dist_pio_delay=10000
1400 eventq_index=0
1401 gem5_extensions=false
1402 int_latency=10000
1403 it_lines=128
1404 p_state_clk_gate_bins=20
1405 p_state_clk_gate_max=1000000000000
1406 p_state_clk_gate_min=1000
1407 platform=system.realview
1408 power_model=Null
1409 system=system
1410 pio=system.membus.master[2]
1411
1412 [system.realview.hdlcd]
1413 type=HDLcd
1414 amba_id=1314816
1415 clk_domain=system.clk_domain
1416 default_p_state=UNDEFINED
1417 enable_capture=true
1418 eventq_index=0
1419 gic=system.realview.gic
1420 int_num=117
1421 p_state_clk_gate_bins=20
1422 p_state_clk_gate_max=1000000000000
1423 p_state_clk_gate_min=1000
1424 pio_addr=721420288
1425 pio_latency=10000
1426 pixel_buffer_size=2048
1427 pixel_chunk=32
1428 power_model=Null
1429 pxl_clk=system.realview.dcc.osc_pxl
1430 system=system
1431 vnc=system.vncserver
1432 workaround_dma_line_count=true
1433 workaround_swap_rb=true
1434 dma=system.membus.slave[0]
1435 pio=system.iobus.master[6]
1436
1437 [system.realview.ide]
1438 type=IdeController
1439 BAR0=1
1440 BAR0LegacyIO=false
1441 BAR0Size=8
1442 BAR1=1
1443 BAR1LegacyIO=false
1444 BAR1Size=4
1445 BAR2=1
1446 BAR2LegacyIO=false
1447 BAR2Size=8
1448 BAR3=1
1449 BAR3LegacyIO=false
1450 BAR3Size=4
1451 BAR4=1
1452 BAR4LegacyIO=false
1453 BAR4Size=16
1454 BAR5=1
1455 BAR5LegacyIO=false
1456 BAR5Size=0
1457 BIST=0
1458 CacheLineSize=0
1459 CapabilityPtr=0
1460 CardbusCIS=0
1461 ClassCode=1
1462 Command=0
1463 DeviceID=28945
1464 ExpansionROM=0
1465 HeaderType=0
1466 InterruptLine=2
1467 InterruptPin=2
1468 LatencyTimer=0
1469 LegacyIOBase=0
1470 MSICAPBaseOffset=0
1471 MSICAPCapId=0
1472 MSICAPMaskBits=0
1473 MSICAPMsgAddr=0
1474 MSICAPMsgCtrl=0
1475 MSICAPMsgData=0
1476 MSICAPMsgUpperAddr=0
1477 MSICAPNextCapability=0
1478 MSICAPPendingBits=0
1479 MSIXCAPBaseOffset=0
1480 MSIXCAPCapId=0
1481 MSIXCAPNextCapability=0
1482 MSIXMsgCtrl=0
1483 MSIXPbaOffset=0
1484 MSIXTableOffset=0
1485 MaximumLatency=0
1486 MinimumGrant=0
1487 PMCAPBaseOffset=0
1488 PMCAPCapId=0
1489 PMCAPCapabilities=0
1490 PMCAPCtrlStatus=0
1491 PMCAPNextCapability=0
1492 PXCAPBaseOffset=0
1493 PXCAPCapId=0
1494 PXCAPCapabilities=0
1495 PXCAPDevCap2=0
1496 PXCAPDevCapabilities=0
1497 PXCAPDevCtrl=0
1498 PXCAPDevCtrl2=0
1499 PXCAPDevStatus=0
1500 PXCAPLinkCap=0
1501 PXCAPLinkCtrl=0
1502 PXCAPLinkStatus=0
1503 PXCAPNextCapability=0
1504 ProgIF=133
1505 Revision=0
1506 Status=640
1507 SubClassCode=1
1508 SubsystemID=0
1509 SubsystemVendorID=0
1510 VendorID=32902
1511 clk_domain=system.clk_domain
1512 config_latency=20000
1513 ctrl_offset=0
1514 default_p_state=UNDEFINED
1515 disks=system.cf0
1516 eventq_index=0
1517 host=system.realview.pci_host
1518 io_shift=0
1519 p_state_clk_gate_bins=20
1520 p_state_clk_gate_max=1000000000000
1521 p_state_clk_gate_min=1000
1522 pci_bus=0
1523 pci_dev=1
1524 pci_func=0
1525 pio_latency=30000
1526 power_model=Null
1527 system=system
1528 dma=system.iobus.slave[3]
1529 pio=system.iobus.master[23]
1530
1531 [system.realview.kmi0]
1532 type=Pl050
1533 amba_id=1314896
1534 clk_domain=system.clk_domain
1535 default_p_state=UNDEFINED
1536 eventq_index=0
1537 gic=system.realview.gic
1538 int_delay=1000000
1539 int_num=44
1540 is_mouse=false
1541 p_state_clk_gate_bins=20
1542 p_state_clk_gate_max=1000000000000
1543 p_state_clk_gate_min=1000
1544 pio_addr=470155264
1545 pio_latency=100000
1546 power_model=Null
1547 system=system
1548 vnc=system.vncserver
1549 pio=system.iobus.master[7]
1550
1551 [system.realview.kmi1]
1552 type=Pl050
1553 amba_id=1314896
1554 clk_domain=system.clk_domain
1555 default_p_state=UNDEFINED
1556 eventq_index=0
1557 gic=system.realview.gic
1558 int_delay=1000000
1559 int_num=45
1560 is_mouse=true
1561 p_state_clk_gate_bins=20
1562 p_state_clk_gate_max=1000000000000
1563 p_state_clk_gate_min=1000
1564 pio_addr=470220800
1565 pio_latency=100000
1566 power_model=Null
1567 system=system
1568 vnc=system.vncserver
1569 pio=system.iobus.master[8]
1570
1571 [system.realview.l2x0_fake]
1572 type=IsaFake
1573 clk_domain=system.clk_domain
1574 default_p_state=UNDEFINED
1575 eventq_index=0
1576 fake_mem=false
1577 p_state_clk_gate_bins=20
1578 p_state_clk_gate_max=1000000000000
1579 p_state_clk_gate_min=1000
1580 pio_addr=739246080
1581 pio_latency=100000
1582 pio_size=4095
1583 power_model=Null
1584 ret_bad_addr=false
1585 ret_data16=65535
1586 ret_data32=4294967295
1587 ret_data64=18446744073709551615
1588 ret_data8=255
1589 system=system
1590 update_data=false
1591 warn_access=
1592 pio=system.iobus.master[12]
1593
1594 [system.realview.lan_fake]
1595 type=IsaFake
1596 clk_domain=system.clk_domain
1597 default_p_state=UNDEFINED
1598 eventq_index=0
1599 fake_mem=false
1600 p_state_clk_gate_bins=20
1601 p_state_clk_gate_max=1000000000000
1602 p_state_clk_gate_min=1000
1603 pio_addr=436207616
1604 pio_latency=100000
1605 pio_size=65535
1606 power_model=Null
1607 ret_bad_addr=false
1608 ret_data16=65535
1609 ret_data32=4294967295
1610 ret_data64=18446744073709551615
1611 ret_data8=255
1612 system=system
1613 update_data=false
1614 warn_access=
1615 pio=system.iobus.master[19]
1616
1617 [system.realview.local_cpu_timer]
1618 type=CpuLocalTimer
1619 clk_domain=system.clk_domain
1620 default_p_state=UNDEFINED
1621 eventq_index=0
1622 gic=system.realview.gic
1623 int_num_timer=29
1624 int_num_watchdog=30
1625 p_state_clk_gate_bins=20
1626 p_state_clk_gate_max=1000000000000
1627 p_state_clk_gate_min=1000
1628 pio_addr=738721792
1629 pio_latency=100000
1630 power_model=Null
1631 system=system
1632 pio=system.membus.master[4]
1633
1634 [system.realview.mcc]
1635 type=SubSystem
1636 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1637 eventq_index=0
1638 thermal_domain=Null
1639
1640 [system.realview.mcc.osc_clcd]
1641 type=RealViewOsc
1642 dcc=0
1643 device=1
1644 eventq_index=0
1645 freq=42105
1646 parent=system.realview.realview_io
1647 position=0
1648 site=0
1649 voltage_domain=system.voltage_domain
1650
1651 [system.realview.mcc.osc_mcc]
1652 type=RealViewOsc
1653 dcc=0
1654 device=0
1655 eventq_index=0
1656 freq=20000
1657 parent=system.realview.realview_io
1658 position=0
1659 site=0
1660 voltage_domain=system.voltage_domain
1661
1662 [system.realview.mcc.osc_peripheral]
1663 type=RealViewOsc
1664 dcc=0
1665 device=2
1666 eventq_index=0
1667 freq=41667
1668 parent=system.realview.realview_io
1669 position=0
1670 site=0
1671 voltage_domain=system.voltage_domain
1672
1673 [system.realview.mcc.osc_system_bus]
1674 type=RealViewOsc
1675 dcc=0
1676 device=4
1677 eventq_index=0
1678 freq=41667
1679 parent=system.realview.realview_io
1680 position=0
1681 site=0
1682 voltage_domain=system.voltage_domain
1683
1684 [system.realview.mcc.temp_crtl]
1685 type=RealViewTemperatureSensor
1686 dcc=0
1687 device=0
1688 eventq_index=0
1689 parent=system.realview.realview_io
1690 position=0
1691 site=0
1692 system=system
1693
1694 [system.realview.mmc_fake]
1695 type=AmbaFake
1696 amba_id=0
1697 clk_domain=system.clk_domain
1698 default_p_state=UNDEFINED
1699 eventq_index=0
1700 ignore_access=false
1701 p_state_clk_gate_bins=20
1702 p_state_clk_gate_max=1000000000000
1703 p_state_clk_gate_min=1000
1704 pio_addr=470089728
1705 pio_latency=100000
1706 power_model=Null
1707 system=system
1708 pio=system.iobus.master[21]
1709
1710 [system.realview.nvmem]
1711 type=SimpleMemory
1712 bandwidth=73.000000
1713 clk_domain=system.clk_domain
1714 conf_table_reported=false
1715 default_p_state=UNDEFINED
1716 eventq_index=0
1717 in_addr_map=true
1718 kvm_map=true
1719 latency=30000
1720 latency_var=0
1721 null=false
1722 p_state_clk_gate_bins=20
1723 p_state_clk_gate_max=1000000000000
1724 p_state_clk_gate_min=1000
1725 power_model=Null
1726 range=0:67108863:0:0:0:0
1727 port=system.membus.master[1]
1728
1729 [system.realview.pci_host]
1730 type=GenericPciHost
1731 clk_domain=system.clk_domain
1732 conf_base=805306368
1733 conf_device_bits=16
1734 conf_size=268435456
1735 default_p_state=UNDEFINED
1736 eventq_index=0
1737 p_state_clk_gate_bins=20
1738 p_state_clk_gate_max=1000000000000
1739 p_state_clk_gate_min=1000
1740 pci_dma_base=0
1741 pci_mem_base=0
1742 pci_pio_base=0
1743 platform=system.realview
1744 power_model=Null
1745 system=system
1746 pio=system.iobus.master[2]
1747
1748 [system.realview.realview_io]
1749 type=RealViewCtrl
1750 clk_domain=system.clk_domain
1751 default_p_state=UNDEFINED
1752 eventq_index=0
1753 idreg=35979264
1754 p_state_clk_gate_bins=20
1755 p_state_clk_gate_max=1000000000000
1756 p_state_clk_gate_min=1000
1757 pio_addr=469827584
1758 pio_latency=100000
1759 power_model=Null
1760 proc_id0=335544320
1761 proc_id1=335544320
1762 system=system
1763 pio=system.iobus.master[1]
1764
1765 [system.realview.rtc]
1766 type=PL031
1767 amba_id=3412017
1768 clk_domain=system.clk_domain
1769 default_p_state=UNDEFINED
1770 eventq_index=0
1771 gic=system.realview.gic
1772 int_delay=100000
1773 int_num=36
1774 p_state_clk_gate_bins=20
1775 p_state_clk_gate_max=1000000000000
1776 p_state_clk_gate_min=1000
1777 pio_addr=471269376
1778 pio_latency=100000
1779 power_model=Null
1780 system=system
1781 time=Thu Jan  1 00:00:00 2009
1782 pio=system.iobus.master[10]
1783
1784 [system.realview.sp810_fake]
1785 type=AmbaFake
1786 amba_id=0
1787 clk_domain=system.clk_domain
1788 default_p_state=UNDEFINED
1789 eventq_index=0
1790 ignore_access=true
1791 p_state_clk_gate_bins=20
1792 p_state_clk_gate_max=1000000000000
1793 p_state_clk_gate_min=1000
1794 pio_addr=469893120
1795 pio_latency=100000
1796 power_model=Null
1797 system=system
1798 pio=system.iobus.master[16]
1799
1800 [system.realview.timer0]
1801 type=Sp804
1802 amba_id=1316868
1803 clk_domain=system.clk_domain
1804 clock0=1000000
1805 clock1=1000000
1806 default_p_state=UNDEFINED
1807 eventq_index=0
1808 gic=system.realview.gic
1809 int_num0=34
1810 int_num1=34
1811 p_state_clk_gate_bins=20
1812 p_state_clk_gate_max=1000000000000
1813 p_state_clk_gate_min=1000
1814 pio_addr=470876160
1815 pio_latency=100000
1816 power_model=Null
1817 system=system
1818 pio=system.iobus.master[3]
1819
1820 [system.realview.timer1]
1821 type=Sp804
1822 amba_id=1316868
1823 clk_domain=system.clk_domain
1824 clock0=1000000
1825 clock1=1000000
1826 default_p_state=UNDEFINED
1827 eventq_index=0
1828 gic=system.realview.gic
1829 int_num0=35
1830 int_num1=35
1831 p_state_clk_gate_bins=20
1832 p_state_clk_gate_max=1000000000000
1833 p_state_clk_gate_min=1000
1834 pio_addr=470941696
1835 pio_latency=100000
1836 power_model=Null
1837 system=system
1838 pio=system.iobus.master[4]
1839
1840 [system.realview.uart]
1841 type=Pl011
1842 clk_domain=system.clk_domain
1843 default_p_state=UNDEFINED
1844 end_on_eot=false
1845 eventq_index=0
1846 gic=system.realview.gic
1847 int_delay=100000
1848 int_num=37
1849 p_state_clk_gate_bins=20
1850 p_state_clk_gate_max=1000000000000
1851 p_state_clk_gate_min=1000
1852 pio_addr=470351872
1853 pio_latency=100000
1854 platform=system.realview
1855 power_model=Null
1856 system=system
1857 terminal=system.terminal
1858 pio=system.iobus.master[0]
1859
1860 [system.realview.uart1_fake]
1861 type=AmbaFake
1862 amba_id=0
1863 clk_domain=system.clk_domain
1864 default_p_state=UNDEFINED
1865 eventq_index=0
1866 ignore_access=false
1867 p_state_clk_gate_bins=20
1868 p_state_clk_gate_max=1000000000000
1869 p_state_clk_gate_min=1000
1870 pio_addr=470417408
1871 pio_latency=100000
1872 power_model=Null
1873 system=system
1874 pio=system.iobus.master[13]
1875
1876 [system.realview.uart2_fake]
1877 type=AmbaFake
1878 amba_id=0
1879 clk_domain=system.clk_domain
1880 default_p_state=UNDEFINED
1881 eventq_index=0
1882 ignore_access=false
1883 p_state_clk_gate_bins=20
1884 p_state_clk_gate_max=1000000000000
1885 p_state_clk_gate_min=1000
1886 pio_addr=470482944
1887 pio_latency=100000
1888 power_model=Null
1889 system=system
1890 pio=system.iobus.master[14]
1891
1892 [system.realview.uart3_fake]
1893 type=AmbaFake
1894 amba_id=0
1895 clk_domain=system.clk_domain
1896 default_p_state=UNDEFINED
1897 eventq_index=0
1898 ignore_access=false
1899 p_state_clk_gate_bins=20
1900 p_state_clk_gate_max=1000000000000
1901 p_state_clk_gate_min=1000
1902 pio_addr=470548480
1903 pio_latency=100000
1904 power_model=Null
1905 system=system
1906 pio=system.iobus.master[15]
1907
1908 [system.realview.usb_fake]
1909 type=IsaFake
1910 clk_domain=system.clk_domain
1911 default_p_state=UNDEFINED
1912 eventq_index=0
1913 fake_mem=false
1914 p_state_clk_gate_bins=20
1915 p_state_clk_gate_max=1000000000000
1916 p_state_clk_gate_min=1000
1917 pio_addr=452984832
1918 pio_latency=100000
1919 pio_size=131071
1920 power_model=Null
1921 ret_bad_addr=false
1922 ret_data16=65535
1923 ret_data32=4294967295
1924 ret_data64=18446744073709551615
1925 ret_data8=255
1926 system=system
1927 update_data=false
1928 warn_access=
1929 pio=system.iobus.master[20]
1930
1931 [system.realview.vgic]
1932 type=VGic
1933 clk_domain=system.clk_domain
1934 default_p_state=UNDEFINED
1935 eventq_index=0
1936 gic=system.realview.gic
1937 hv_addr=738213888
1938 p_state_clk_gate_bins=20
1939 p_state_clk_gate_max=1000000000000
1940 p_state_clk_gate_min=1000
1941 pio_delay=10000
1942 platform=system.realview
1943 power_model=Null
1944 ppint=25
1945 system=system
1946 vcpu_addr=738222080
1947 pio=system.membus.master[3]
1948
1949 [system.realview.vram]
1950 type=SimpleMemory
1951 bandwidth=73.000000
1952 clk_domain=system.clk_domain
1953 conf_table_reported=false
1954 default_p_state=UNDEFINED
1955 eventq_index=0
1956 in_addr_map=true
1957 kvm_map=true
1958 latency=30000
1959 latency_var=0
1960 null=false
1961 p_state_clk_gate_bins=20
1962 p_state_clk_gate_max=1000000000000
1963 p_state_clk_gate_min=1000
1964 power_model=Null
1965 range=402653184:436207615:0:0:0:0
1966 port=system.iobus.master[11]
1967
1968 [system.realview.watchdog_fake]
1969 type=AmbaFake
1970 amba_id=0
1971 clk_domain=system.clk_domain
1972 default_p_state=UNDEFINED
1973 eventq_index=0
1974 ignore_access=false
1975 p_state_clk_gate_bins=20
1976 p_state_clk_gate_max=1000000000000
1977 p_state_clk_gate_min=1000
1978 pio_addr=470745088
1979 pio_latency=100000
1980 power_model=Null
1981 system=system
1982 pio=system.iobus.master[17]
1983
1984 [system.terminal]
1985 type=Terminal
1986 eventq_index=0
1987 intr_control=system.intrctrl
1988 number=0
1989 output=true
1990 port=3456
1991
1992 [system.vncserver]
1993 type=VncServer
1994 eventq_index=0
1995 frame_capture=false
1996 number=0
1997 port=5900
1998
1999 [system.voltage_domain]
2000 type=VoltageDomain
2001 eventq_index=0
2002 voltage=1.000000
2003