tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
  12 atags_addr=256
  13 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 clock=1000
  16 dtb_filename=False
  17 early_kernel_symbols=false
  18 enable_context_switch_stats_dump=false
  19 flags_addr=268435504
  20 gic_cpu_addr=520093952
  21 init_param=0
  22 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  23 load_addr_mask=268435455
  24 machine_type=RealView_PBX
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.realview.nvmem system.physmem
  28 multi_proc=true
  29 num_work_ids=16
  30 readfile=tests/halt.sh
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.bridge]
  42 type=Bridge
  43 clock=1000
  44 delay=50000
  45 ranges=268435456:520093695 1073741824:1610612735
  46 req_size=16
  47 resp_size=16
  48 master=system.iobus.slave[0]
  49 slave=system.membus.master[0]
  50
  51 [system.cf0]
  52 type=IdeDisk
  53 children=image
  54 delay=1000000
  55 driveID=master
  56 image=system.cf0.image
  57
  58 [system.cf0.image]
  59 type=CowDiskImage
  60 children=child
  61 child=system.cf0.image.child
  62 image_file=
  63 read_only=false
  64 table_size=65536
  65
  66 [system.cf0.image.child]
  67 type=RawDiskImage
  68 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  69 read_only=true
  70
  71 [system.cpu]
  72 type=DerivO3CPU
  73 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  74 LFSTSize=1024
  75 LQEntries=32
  76 LSQCheckLoads=true
  77 LSQDepCheckShift=4
  78 SQEntries=32
  79 SSITSize=1024
  80 activity=0
  81 backComSize=5
  82 branchPred=system.cpu.branchPred
  83 cachePorts=200
  84 checker=Null
  85 clock=500
  86 commitToDecodeDelay=1
  87 commitToFetchDelay=1
  88 commitToIEWDelay=1
  89 commitToRenameDelay=1
  90 commitWidth=8
  91 cpu_id=0
  92 decodeToFetchDelay=1
  93 decodeToRenameDelay=1
  94 decodeWidth=8
  95 dispatchWidth=8
  96 do_checkpoint_insts=true
  97 do_quiesce=true
  98 do_statistics_insts=true
  99 dtb=system.cpu.dtb
 100 fetchToDecodeDelay=1
 101 fetchTrapLatency=1
 102 fetchWidth=8
 103 forwardComSize=5
 104 fuPool=system.cpu.fuPool
 105 function_trace=false
 106 function_trace_start=0
 107 iewToCommitDelay=1
 108 iewToDecodeDelay=1
 109 iewToFetchDelay=1
 110 iewToRenameDelay=1
 111 interrupts=system.cpu.interrupts
 112 isa=system.cpu.isa
 113 issueToExecuteDelay=1
 114 issueWidth=8
 115 itb=system.cpu.itb
 116 max_insts_all_threads=0
 117 max_insts_any_thread=0
 118 max_loads_all_threads=0
 119 max_loads_any_thread=0
 120 needsTSO=false
 121 numIQEntries=64
 122 numPhysFloatRegs=256
 123 numPhysIntRegs=256
 124 numROBEntries=192
 125 numRobs=1
 126 numThreads=1
 127 profile=0
 128 progress_interval=0
 129 renameToDecodeDelay=1
 130 renameToFetchDelay=1
 131 renameToIEWDelay=2
 132 renameToROBDelay=1
 133 renameWidth=8
 134 smtCommitPolicy=RoundRobin
 135 smtFetchPolicy=SingleThread
 136 smtIQPolicy=Partitioned
 137 smtIQThreshold=100
 138 smtLSQPolicy=Partitioned
 139 smtLSQThreshold=100
 140 smtNumFetchingThreads=1
 141 smtROBPolicy=Partitioned
 142 smtROBThreshold=100
 143 squashWidth=8
 144 store_set_clear_period=250000
 145 switched_out=false
 146 system=system
 147 tracer=system.cpu.tracer
 148 trapLatency=13
 149 wbDepth=1
 150 wbWidth=8
 151 workload=
 152 dcache_port=system.cpu.dcache.cpu_side
 153 icache_port=system.cpu.icache.cpu_side
 154
 155 [system.cpu.branchPred]
 156 type=BranchPredictor
 157 BTBEntries=4096
 158 BTBTagSize=16
 159 RASSize=16
 160 choiceCtrBits=2
 161 choicePredictorSize=8192
 162 globalCtrBits=2
 163 globalHistoryBits=13
 164 globalPredictorSize=8192
 165 instShiftAmt=2
 166 localCtrBits=2
 167 localHistoryBits=11
 168 localHistoryTableSize=2048
 169 localPredictorSize=2048
 170 numThreads=1
 171 predType=tournament
 172
 173 [system.cpu.dcache]
 174 type=BaseCache
 175 addr_ranges=0:18446744073709551615
 176 assoc=4
 177 block_size=64
 178 clock=500
 179 forward_snoops=true
 180 hit_latency=2
 181 is_top_level=true
 182 max_miss_count=0
 183 mshrs=4
 184 prefetch_on_access=false
 185 prefetcher=Null
 186 response_latency=2
 187 size=32768
 188 system=system
 189 tgts_per_mshr=20
 190 two_queue=false
 191 write_buffers=8
 192 cpu_side=system.cpu.dcache_port
 193 mem_side=system.cpu.toL2Bus.slave[1]
 194
 195 [system.cpu.dtb]
 196 type=ArmTLB
 197 children=walker
 198 size=64
 199 walker=system.cpu.dtb.walker
 200
 201 [system.cpu.dtb.walker]
 202 type=ArmTableWalker
 203 clock=500
 204 num_squash_per_cycle=2
 205 sys=system
 206 port=system.cpu.toL2Bus.slave[3]
 207
 208 [system.cpu.fuPool]
 209 type=FUPool
 210 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 211 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 212
 213 [system.cpu.fuPool.FUList0]
 214 type=FUDesc
 215 children=opList
 216 count=6
 217 opList=system.cpu.fuPool.FUList0.opList
 218
 219 [system.cpu.fuPool.FUList0.opList]
 220 type=OpDesc
 221 issueLat=1
 222 opClass=IntAlu
 223 opLat=1
 224
 225 [system.cpu.fuPool.FUList1]
 226 type=FUDesc
 227 children=opList0 opList1
 228 count=2
 229 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 230
 231 [system.cpu.fuPool.FUList1.opList0]
 232 type=OpDesc
 233 issueLat=1
 234 opClass=IntMult
 235 opLat=3
 236
 237 [system.cpu.fuPool.FUList1.opList1]
 238 type=OpDesc
 239 issueLat=19
 240 opClass=IntDiv
 241 opLat=20
 242
 243 [system.cpu.fuPool.FUList2]
 244 type=FUDesc
 245 children=opList0 opList1 opList2
 246 count=4
 247 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 248
 249 [system.cpu.fuPool.FUList2.opList0]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=FloatAdd
 253 opLat=2
 254
 255 [system.cpu.fuPool.FUList2.opList1]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=FloatCmp
 259 opLat=2
 260
 261 [system.cpu.fuPool.FUList2.opList2]
 262 type=OpDesc
 263 issueLat=1
 264 opClass=FloatCvt
 265 opLat=2
 266
 267 [system.cpu.fuPool.FUList3]
 268 type=FUDesc
 269 children=opList0 opList1 opList2
 270 count=2
 271 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 272
 273 [system.cpu.fuPool.FUList3.opList0]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=FloatMult
 277 opLat=4
 278
 279 [system.cpu.fuPool.FUList3.opList1]
 280 type=OpDesc
 281 issueLat=12
 282 opClass=FloatDiv
 283 opLat=12
 284
 285 [system.cpu.fuPool.FUList3.opList2]
 286 type=OpDesc
 287 issueLat=24
 288 opClass=FloatSqrt
 289 opLat=24
 290
 291 [system.cpu.fuPool.FUList4]
 292 type=FUDesc
 293 children=opList
 294 count=0
 295 opList=system.cpu.fuPool.FUList4.opList
 296
 297 [system.cpu.fuPool.FUList4.opList]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=MemRead
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5]
 304 type=FUDesc
 305 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 306 count=4
 307 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 308
 309 [system.cpu.fuPool.FUList5.opList00]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdAdd
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList01]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdAddAcc
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList02]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdAlu
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList03]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdCmp
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList04]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdCvt
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList05]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdMisc
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList06]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdMult
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList07]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdMultAcc
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList08]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdShift
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList09]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdShiftAcc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList10]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdSqrt
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList11]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatAdd
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList12]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=SimdFloatAlu
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList13]
 388 type=OpDesc
 389 issueLat=1
 390 opClass=SimdFloatCmp
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList14]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=SimdFloatCvt
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList5.opList15]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=SimdFloatDiv
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList5.opList16]
 406 type=OpDesc
 407 issueLat=1
 408 opClass=SimdFloatMisc
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList17]
 412 type=OpDesc
 413 issueLat=1
 414 opClass=SimdFloatMult
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList5.opList18]
 418 type=OpDesc
 419 issueLat=1
 420 opClass=SimdFloatMultAcc
 421 opLat=1
 422
 423 [system.cpu.fuPool.FUList5.opList19]
 424 type=OpDesc
 425 issueLat=1
 426 opClass=SimdFloatSqrt
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList6]
 430 type=FUDesc
 431 children=opList
 432 count=0
 433 opList=system.cpu.fuPool.FUList6.opList
 434
 435 [system.cpu.fuPool.FUList6.opList]
 436 type=OpDesc
 437 issueLat=1
 438 opClass=MemWrite
 439 opLat=1
 440
 441 [system.cpu.fuPool.FUList7]
 442 type=FUDesc
 443 children=opList0 opList1
 444 count=4
 445 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 446
 447 [system.cpu.fuPool.FUList7.opList0]
 448 type=OpDesc
 449 issueLat=1
 450 opClass=MemRead
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList7.opList1]
 454 type=OpDesc
 455 issueLat=1
 456 opClass=MemWrite
 457 opLat=1
 458
 459 [system.cpu.fuPool.FUList8]
 460 type=FUDesc
 461 children=opList
 462 count=1
 463 opList=system.cpu.fuPool.FUList8.opList
 464
 465 [system.cpu.fuPool.FUList8.opList]
 466 type=OpDesc
 467 issueLat=3
 468 opClass=IprAccess
 469 opLat=3
 470
 471 [system.cpu.icache]
 472 type=BaseCache
 473 addr_ranges=0:18446744073709551615
 474 assoc=1
 475 block_size=64
 476 clock=500
 477 forward_snoops=true
 478 hit_latency=2
 479 is_top_level=true
 480 max_miss_count=0
 481 mshrs=4
 482 prefetch_on_access=false
 483 prefetcher=Null
 484 response_latency=2
 485 size=32768
 486 system=system
 487 tgts_per_mshr=20
 488 two_queue=false
 489 write_buffers=8
 490 cpu_side=system.cpu.icache_port
 491 mem_side=system.cpu.toL2Bus.slave[0]
 492
 493 [system.cpu.interrupts]
 494 type=ArmInterrupts
 495
 496 [system.cpu.isa]
 497 type=ArmISA
 498 fpsid=1090793632
 499 id_isar0=34607377
 500 id_isar1=34677009
 501 id_isar2=555950401
 502 id_isar3=17899825
 503 id_isar4=268501314
 504 id_isar5=0
 505 id_mmfr0=3
 506 id_mmfr1=0
 507 id_mmfr2=19070976
 508 id_mmfr3=4027589137
 509 id_pfr0=49
 510 id_pfr1=1
 511 midr=890224640
 512
 513 [system.cpu.itb]
 514 type=ArmTLB
 515 children=walker
 516 size=64
 517 walker=system.cpu.itb.walker
 518
 519 [system.cpu.itb.walker]
 520 type=ArmTableWalker
 521 clock=500
 522 num_squash_per_cycle=2
 523 sys=system
 524 port=system.cpu.toL2Bus.slave[2]
 525
 526 [system.cpu.l2cache]
 527 type=BaseCache
 528 addr_ranges=0:18446744073709551615
 529 assoc=8
 530 block_size=64
 531 clock=500
 532 forward_snoops=true
 533 hit_latency=20
 534 is_top_level=false
 535 max_miss_count=0
 536 mshrs=20
 537 prefetch_on_access=false
 538 prefetcher=Null
 539 response_latency=20
 540 size=4194304
 541 system=system
 542 tgts_per_mshr=12
 543 two_queue=false
 544 write_buffers=8
 545 cpu_side=system.cpu.toL2Bus.master[0]
 546 mem_side=system.membus.slave[1]
 547
 548 [system.cpu.toL2Bus]
 549 type=CoherentBus
 550 block_size=64
 551 clock=500
 552 header_cycles=1
 553 system=system
 554 use_default_range=false
 555 width=32
 556 master=system.cpu.l2cache.cpu_side
 557 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 558
 559 [system.cpu.tracer]
 560 type=ExeTracer
 561
 562 [system.intrctrl]
 563 type=IntrControl
 564 sys=system
 565
 566 [system.iobus]
 567 type=NoncoherentBus
 568 block_size=64
 569 clock=1000
 570 header_cycles=1
 571 use_default_range=false
 572 width=8
 573 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 574 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 575
 576 [system.iocache]
 577 type=BaseCache
 578 addr_ranges=0:134217727
 579 assoc=8
 580 block_size=64
 581 clock=1000
 582 forward_snoops=false
 583 hit_latency=50
 584 is_top_level=true
 585 max_miss_count=0
 586 mshrs=20
 587 prefetch_on_access=false
 588 prefetcher=Null
 589 response_latency=50
 590 size=1024
 591 system=system
 592 tgts_per_mshr=12
 593 two_queue=false
 594 write_buffers=8
 595 cpu_side=system.iobus.master[25]
 596 mem_side=system.membus.slave[2]
 597
 598 [system.membus]
 599 type=CoherentBus
 600 children=badaddr_responder
 601 block_size=64
 602 clock=1000
 603 header_cycles=1
 604 system=system
 605 use_default_range=false
 606 width=8
 607 default=system.membus.badaddr_responder.pio
 608 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 609 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 610
 611 [system.membus.badaddr_responder]
 612 type=IsaFake
 613 clock=1000
 614 fake_mem=false
 615 pio_addr=0
 616 pio_latency=100000
 617 pio_size=8
 618 ret_bad_addr=true
 619 ret_data16=65535
 620 ret_data32=4294967295
 621 ret_data64=18446744073709551615
 622 ret_data8=255
 623 system=system
 624 update_data=false
 625 warn_access=warn
 626 pio=system.membus.default
 627
 628 [system.physmem]
 629 type=SimpleDRAM
 630 activation_limit=4
 631 addr_mapping=openmap
 632 banks_per_rank=8
 633 channels=1
 634 clock=1000
 635 conf_table_reported=true
 636 in_addr_map=true
 637 lines_per_rowbuffer=32
 638 mem_sched_policy=frfcfs
 639 null=false
 640 page_policy=open
 641 range=0:134217727
 642 ranks_per_channel=2
 643 read_buffer_size=32
 644 tBURST=5000
 645 tCL=13750
 646 tRCD=13750
 647 tREFI=7800000
 648 tRFC=300000
 649 tRP=13750
 650 tWTR=7500
 651 tXAW=40000
 652 write_buffer_size=32
 653 write_thresh_perc=70
 654 zero=false
 655 port=system.membus.master[2]
 656
 657 [system.realview]
 658 type=RealView
 659 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 660 intrctrl=system.intrctrl
 661 max_mem_size=268435456
 662 mem_start_addr=0
 663 pci_cfg_base=0
 664 system=system
 665
 666 [system.realview.a9scu]
 667 type=A9SCU
 668 clock=1000
 669 pio_addr=520093696
 670 pio_latency=100000
 671 system=system
 672 pio=system.membus.master[5]
 673
 674 [system.realview.aaci_fake]
 675 type=AmbaFake
 676 amba_id=0
 677 clock=1000
 678 ignore_access=false
 679 pio_addr=268451840
 680 pio_latency=100000
 681 system=system
 682 pio=system.iobus.master[21]
 683
 684 [system.realview.cf_ctrl]
 685 type=IdeController
 686 BAR0=402653184
 687 BAR0LegacyIO=true
 688 BAR0Size=16
 689 BAR1=402653440
 690 BAR1LegacyIO=true
 691 BAR1Size=1
 692 BAR2=1
 693 BAR2LegacyIO=false
 694 BAR2Size=8
 695 BAR3=1
 696 BAR3LegacyIO=false
 697 BAR3Size=4
 698 BAR4=1
 699 BAR4LegacyIO=false
 700 BAR4Size=16
 701 BAR5=1
 702 BAR5LegacyIO=false
 703 BAR5Size=0
 704 BIST=0
 705 CacheLineSize=0
 706 CardbusCIS=0
 707 ClassCode=1
 708 Command=1
 709 DeviceID=28945
 710 ExpansionROM=0
 711 HeaderType=0
 712 InterruptLine=31
 713 InterruptPin=1
 714 LatencyTimer=0
 715 MaximumLatency=0
 716 MinimumGrant=0
 717 ProgIF=133
 718 Revision=0
 719 Status=640
 720 SubClassCode=1
 721 SubsystemID=0
 722 SubsystemVendorID=0
 723 VendorID=32902
 724 clock=1000
 725 config_latency=20000
 726 ctrl_offset=2
 727 disks=system.cf0
 728 io_shift=1
 729 pci_bus=2
 730 pci_dev=7
 731 pci_func=0
 732 pio_latency=30000
 733 platform=system.realview
 734 system=system
 735 config=system.iobus.master[8]
 736 dma=system.iobus.slave[2]
 737 pio=system.iobus.master[7]
 738
 739 [system.realview.clcd]
 740 type=Pl111
 741 amba_id=1315089
 742 clock=1000
 743 gic=system.realview.gic
 744 int_num=55
 745 pio_addr=268566528
 746 pio_latency=10000
 747 pixel_clock=41667
 748 system=system
 749 vnc=system.vncserver
 750 dma=system.iobus.slave[1]
 751 pio=system.iobus.master[4]
 752
 753 [system.realview.dmac_fake]
 754 type=AmbaFake
 755 amba_id=0
 756 clock=1000
 757 ignore_access=false
 758 pio_addr=268632064
 759 pio_latency=100000
 760 system=system
 761 pio=system.iobus.master[9]
 762
 763 [system.realview.flash_fake]
 764 type=IsaFake
 765 clock=1000
 766 fake_mem=true
 767 pio_addr=1073741824
 768 pio_latency=100000
 769 pio_size=536870912
 770 ret_bad_addr=false
 771 ret_data16=65535
 772 ret_data32=4294967295
 773 ret_data64=18446744073709551615
 774 ret_data8=255
 775 system=system
 776 update_data=false
 777 warn_access=
 778 pio=system.iobus.master[24]
 779
 780 [system.realview.gic]
 781 type=Pl390
 782 clock=1000
 783 cpu_addr=520093952
 784 cpu_pio_delay=10000
 785 dist_addr=520097792
 786 dist_pio_delay=10000
 787 int_latency=10000
 788 it_lines=128
 789 platform=system.realview
 790 system=system
 791 pio=system.membus.master[3]
 792
 793 [system.realview.gpio0_fake]
 794 type=AmbaFake
 795 amba_id=0
 796 clock=1000
 797 ignore_access=false
 798 pio_addr=268513280
 799 pio_latency=100000
 800 system=system
 801 pio=system.iobus.master[16]
 802
 803 [system.realview.gpio1_fake]
 804 type=AmbaFake
 805 amba_id=0
 806 clock=1000
 807 ignore_access=false
 808 pio_addr=268517376
 809 pio_latency=100000
 810 system=system
 811 pio=system.iobus.master[17]
 812
 813 [system.realview.gpio2_fake]
 814 type=AmbaFake
 815 amba_id=0
 816 clock=1000
 817 ignore_access=false
 818 pio_addr=268521472
 819 pio_latency=100000
 820 system=system
 821 pio=system.iobus.master[18]
 822
 823 [system.realview.kmi0]
 824 type=Pl050
 825 amba_id=1314896
 826 clock=1000
 827 gic=system.realview.gic
 828 int_delay=1000000
 829 int_num=52
 830 is_mouse=false
 831 pio_addr=268460032
 832 pio_latency=100000
 833 system=system
 834 vnc=system.vncserver
 835 pio=system.iobus.master[5]
 836
 837 [system.realview.kmi1]
 838 type=Pl050
 839 amba_id=1314896
 840 clock=1000
 841 gic=system.realview.gic
 842 int_delay=1000000
 843 int_num=53
 844 is_mouse=true
 845 pio_addr=268464128
 846 pio_latency=100000
 847 system=system
 848 vnc=system.vncserver
 849 pio=system.iobus.master[6]
 850
 851 [system.realview.l2x0_fake]
 852 type=IsaFake
 853 clock=1000
 854 fake_mem=false
 855 pio_addr=520101888
 856 pio_latency=100000
 857 pio_size=4095
 858 ret_bad_addr=false
 859 ret_data16=65535
 860 ret_data32=4294967295
 861 ret_data64=18446744073709551615
 862 ret_data8=255
 863 system=system
 864 update_data=false
 865 warn_access=
 866 pio=system.membus.master[4]
 867
 868 [system.realview.local_cpu_timer]
 869 type=CpuLocalTimer
 870 clock=1000
 871 gic=system.realview.gic
 872 int_num_timer=29
 873 int_num_watchdog=30
 874 pio_addr=520095232
 875 pio_latency=100000
 876 system=system
 877 pio=system.membus.master[6]
 878
 879 [system.realview.mmc_fake]
 880 type=AmbaFake
 881 amba_id=0
 882 clock=1000
 883 ignore_access=false
 884 pio_addr=268455936
 885 pio_latency=100000
 886 system=system
 887 pio=system.iobus.master[22]
 888
 889 [system.realview.nvmem]
 890 type=SimpleMemory
 891 bandwidth=73.000000
 892 clock=1000
 893 conf_table_reported=false
 894 in_addr_map=true
 895 latency=30000
 896 latency_var=0
 897 null=false
 898 range=2147483648:2214592511
 899 zero=true
 900 port=system.membus.master[1]
 901
 902 [system.realview.realview_io]
 903 type=RealViewCtrl
 904 clock=1000
 905 idreg=0
 906 pio_addr=268435456
 907 pio_latency=100000
 908 proc_id0=201326592
 909 proc_id1=201327138
 910 system=system
 911 pio=system.iobus.master[1]
 912
 913 [system.realview.rtc]
 914 type=PL031
 915 amba_id=3412017
 916 clock=1000
 917 gic=system.realview.gic
 918 int_delay=100000
 919 int_num=42
 920 pio_addr=268529664
 921 pio_latency=100000
 922 system=system
 923 time=Thu Jan  1 00:00:00 2009
 924 pio=system.iobus.master[23]
 925
 926 [system.realview.sci_fake]
 927 type=AmbaFake
 928 amba_id=0
 929 clock=1000
 930 ignore_access=false
 931 pio_addr=268492800
 932 pio_latency=100000
 933 system=system
 934 pio=system.iobus.master[20]
 935
 936 [system.realview.smc_fake]
 937 type=AmbaFake
 938 amba_id=0
 939 clock=1000
 940 ignore_access=false
 941 pio_addr=269357056
 942 pio_latency=100000
 943 system=system
 944 pio=system.iobus.master[13]
 945
 946 [system.realview.sp810_fake]
 947 type=AmbaFake
 948 amba_id=0
 949 clock=1000
 950 ignore_access=true
 951 pio_addr=268439552
 952 pio_latency=100000
 953 system=system
 954 pio=system.iobus.master[14]
 955
 956 [system.realview.ssp_fake]
 957 type=AmbaFake
 958 amba_id=0
 959 clock=1000
 960 ignore_access=false
 961 pio_addr=268488704
 962 pio_latency=100000
 963 system=system
 964 pio=system.iobus.master[19]
 965
 966 [system.realview.timer0]
 967 type=Sp804
 968 amba_id=1316868
 969 clock=1000
 970 clock0=1000000
 971 clock1=1000000
 972 gic=system.realview.gic
 973 int_num0=36
 974 int_num1=36
 975 pio_addr=268505088
 976 pio_latency=100000
 977 system=system
 978 pio=system.iobus.master[2]
 979
 980 [system.realview.timer1]
 981 type=Sp804
 982 amba_id=1316868
 983 clock=1000
 984 clock0=1000000
 985 clock1=1000000
 986 gic=system.realview.gic
 987 int_num0=37
 988 int_num1=37
 989 pio_addr=268509184
 990 pio_latency=100000
 991 system=system
 992 pio=system.iobus.master[3]
 993
 994 [system.realview.uart]
 995 type=Pl011
 996 clock=1000
 997 end_on_eot=false
 998 gic=system.realview.gic
 999 int_delay=100000
1000 int_num=44
1001 pio_addr=268472320
1002 pio_latency=100000
1003 platform=system.realview
1004 system=system
1005 terminal=system.terminal
1006 pio=system.iobus.master[0]
1007
1008 [system.realview.uart1_fake]
1009 type=AmbaFake
1010 amba_id=0
1011 clock=1000
1012 ignore_access=false
1013 pio_addr=268476416
1014 pio_latency=100000
1015 system=system
1016 pio=system.iobus.master[10]
1017
1018 [system.realview.uart2_fake]
1019 type=AmbaFake
1020 amba_id=0
1021 clock=1000
1022 ignore_access=false
1023 pio_addr=268480512
1024 pio_latency=100000
1025 system=system
1026 pio=system.iobus.master[11]
1027
1028 [system.realview.uart3_fake]
1029 type=AmbaFake
1030 amba_id=0
1031 clock=1000
1032 ignore_access=false
1033 pio_addr=268484608
1034 pio_latency=100000
1035 system=system
1036 pio=system.iobus.master[12]
1037
1038 [system.realview.watchdog_fake]
1039 type=AmbaFake
1040 amba_id=0
1041 clock=1000
1042 ignore_access=false
1043 pio_addr=268500992
1044 pio_latency=100000
1045 system=system
1046 pio=system.iobus.master[15]
1047
1048 [system.terminal]
1049 type=Terminal
1050 intr_control=system.intrctrl
1051 number=0
1052 output=true
1053 port=3456
1054
1055 [system.vncserver]
1056 type=VncServer
1057 frame_capture=false
1058 number=0
1059 port=5900
1060