tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
  12 atags_addr=256
  13 boot_loader=/dist/m5/system/binaries/boot.arm
  14 boot_loader_mem=system.realview.nvmem
  15 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  16 flags_addr=268435504
  17 gic_cpu_addr=520093952
  18 init_param=0
  19 kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  20 load_addr_mask=268435455
  21 machine_type=RealView_PBX
  22 mem_mode=timing
  23 memories=system.physmem system.realview.nvmem
  24 midr_regval=890224640
  25 num_work_ids=16
  26 physmem=system.physmem
  27 readfile=tests/halt.sh
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.bridge]
  39 type=Bridge
  40 delay=50000
  41 nack_delay=4000
  42 ranges=268435456:520093695 1073741824:1610612735
  43 req_size=16
  44 resp_size=16
  45 write_ack=false
  46 master=system.iobus.slave[0]
  47 slave=system.membus.master[0]
  48
  49 [system.cf0]
  50 type=IdeDisk
  51 children=image
  52 delay=1000000
  53 driveID=master
  54 image=system.cf0.image
  55
  56 [system.cf0.image]
  57 type=CowDiskImage
  58 children=child
  59 child=system.cf0.image.child
  60 image_file=
  61 read_only=false
  62 table_size=65536
  63
  64 [system.cf0.image.child]
  65 type=RawDiskImage
  66 image_file=/dist/m5/system/disks/linux-arm-ael.img
  67 read_only=true
  68
  69 [system.cpu]
  70 type=DerivO3CPU
  71 children=dcache dtb fuPool icache interrupts itb tracer
  72 BTBEntries=4096
  73 BTBTagSize=16
  74 LFSTSize=1024
  75 LQEntries=32
  76 LSQCheckLoads=true
  77 LSQDepCheckShift=4
  78 RASSize=16
  79 SQEntries=32
  80 SSITSize=1024
  81 activity=0
  82 backComSize=5
  83 cachePorts=200
  84 checker=Null
  85 choiceCtrBits=2
  86 choicePredictorSize=8192
  87 clock=500
  88 commitToDecodeDelay=1
  89 commitToFetchDelay=1
  90 commitToIEWDelay=1
  91 commitToRenameDelay=1
  92 commitWidth=8
  93 cpu_id=0
  94 decodeToFetchDelay=1
  95 decodeToRenameDelay=1
  96 decodeWidth=8
  97 defer_registration=false
  98 dispatchWidth=8
  99 do_checkpoint_insts=true
 100 do_quiesce=true
 101 do_statistics_insts=true
 102 dtb=system.cpu.dtb
 103 fetchToDecodeDelay=1
 104 fetchTrapLatency=1
 105 fetchWidth=8
 106 forwardComSize=5
 107 fuPool=system.cpu.fuPool
 108 function_trace=false
 109 function_trace_start=0
 110 globalCtrBits=2
 111 globalHistoryBits=13
 112 globalPredictorSize=8192
 113 iewToCommitDelay=1
 114 iewToDecodeDelay=1
 115 iewToFetchDelay=1
 116 iewToRenameDelay=1
 117 instShiftAmt=2
 118 interrupts=system.cpu.interrupts
 119 issueToExecuteDelay=1
 120 issueWidth=8
 121 itb=system.cpu.itb
 122 localCtrBits=2
 123 localHistoryBits=11
 124 localHistoryTableSize=2048
 125 localPredictorSize=2048
 126 max_insts_all_threads=0
 127 max_insts_any_thread=0
 128 max_loads_all_threads=0
 129 max_loads_any_thread=0
 130 needsTSO=false
 131 numIQEntries=64
 132 numPhysFloatRegs=256
 133 numPhysIntRegs=256
 134 numROBEntries=192
 135 numRobs=1
 136 numThreads=1
 137 phase=0
 138 predType=tournament
 139 profile=0
 140 progress_interval=0
 141 renameToDecodeDelay=1
 142 renameToFetchDelay=1
 143 renameToIEWDelay=2
 144 renameToROBDelay=1
 145 renameWidth=8
 146 smtCommitPolicy=RoundRobin
 147 smtFetchPolicy=SingleThread
 148 smtIQPolicy=Partitioned
 149 smtIQThreshold=100
 150 smtLSQPolicy=Partitioned
 151 smtLSQThreshold=100
 152 smtNumFetchingThreads=1
 153 smtROBPolicy=Partitioned
 154 smtROBThreshold=100
 155 squashWidth=8
 156 store_set_clear_period=250000
 157 system=system
 158 tracer=system.cpu.tracer
 159 trapLatency=13
 160 wbDepth=1
 161 wbWidth=8
 162 workload=
 163 dcache_port=system.cpu.dcache.cpu_side
 164 icache_port=system.cpu.icache.cpu_side
 165
 166 [system.cpu.dcache]
 167 type=BaseCache
 168 addr_ranges=0:18446744073709551615
 169 assoc=4
 170 block_size=64
 171 forward_snoops=true
 172 hash_delay=1
 173 is_top_level=true
 174 latency=1000
 175 max_miss_count=0
 176 mshrs=4
 177 prefetch_on_access=false
 178 prefetcher=Null
 179 prioritizeRequests=false
 180 repl=Null
 181 size=32768
 182 subblock_size=0
 183 system=system
 184 tgts_per_mshr=20
 185 trace_addr=0
 186 two_queue=false
 187 write_buffers=8
 188 cpu_side=system.cpu.dcache_port
 189 mem_side=system.toL2Bus.slave[1]
 190
 191 [system.cpu.dtb]
 192 type=ArmTLB
 193 children=walker
 194 size=64
 195 walker=system.cpu.dtb.walker
 196
 197 [system.cpu.dtb.walker]
 198 type=ArmTableWalker
 199 max_backoff=100000
 200 min_backoff=0
 201 sys=system
 202 port=system.toL2Bus.slave[3]
 203
 204 [system.cpu.fuPool]
 205 type=FUPool
 206 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 207 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 208
 209 [system.cpu.fuPool.FUList0]
 210 type=FUDesc
 211 children=opList
 212 count=6
 213 opList=system.cpu.fuPool.FUList0.opList
 214
 215 [system.cpu.fuPool.FUList0.opList]
 216 type=OpDesc
 217 issueLat=1
 218 opClass=IntAlu
 219 opLat=1
 220
 221 [system.cpu.fuPool.FUList1]
 222 type=FUDesc
 223 children=opList0 opList1
 224 count=2
 225 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 226
 227 [system.cpu.fuPool.FUList1.opList0]
 228 type=OpDesc
 229 issueLat=1
 230 opClass=IntMult
 231 opLat=3
 232
 233 [system.cpu.fuPool.FUList1.opList1]
 234 type=OpDesc
 235 issueLat=19
 236 opClass=IntDiv
 237 opLat=20
 238
 239 [system.cpu.fuPool.FUList2]
 240 type=FUDesc
 241 children=opList0 opList1 opList2
 242 count=4
 243 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 244
 245 [system.cpu.fuPool.FUList2.opList0]
 246 type=OpDesc
 247 issueLat=1
 248 opClass=FloatAdd
 249 opLat=2
 250
 251 [system.cpu.fuPool.FUList2.opList1]
 252 type=OpDesc
 253 issueLat=1
 254 opClass=FloatCmp
 255 opLat=2
 256
 257 [system.cpu.fuPool.FUList2.opList2]
 258 type=OpDesc
 259 issueLat=1
 260 opClass=FloatCvt
 261 opLat=2
 262
 263 [system.cpu.fuPool.FUList3]
 264 type=FUDesc
 265 children=opList0 opList1 opList2
 266 count=2
 267 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 268
 269 [system.cpu.fuPool.FUList3.opList0]
 270 type=OpDesc
 271 issueLat=1
 272 opClass=FloatMult
 273 opLat=4
 274
 275 [system.cpu.fuPool.FUList3.opList1]
 276 type=OpDesc
 277 issueLat=12
 278 opClass=FloatDiv
 279 opLat=12
 280
 281 [system.cpu.fuPool.FUList3.opList2]
 282 type=OpDesc
 283 issueLat=24
 284 opClass=FloatSqrt
 285 opLat=24
 286
 287 [system.cpu.fuPool.FUList4]
 288 type=FUDesc
 289 children=opList
 290 count=0
 291 opList=system.cpu.fuPool.FUList4.opList
 292
 293 [system.cpu.fuPool.FUList4.opList]
 294 type=OpDesc
 295 issueLat=1
 296 opClass=MemRead
 297 opLat=1
 298
 299 [system.cpu.fuPool.FUList5]
 300 type=FUDesc
 301 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 302 count=4
 303 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 304
 305 [system.cpu.fuPool.FUList5.opList00]
 306 type=OpDesc
 307 issueLat=1
 308 opClass=SimdAdd
 309 opLat=1
 310
 311 [system.cpu.fuPool.FUList5.opList01]
 312 type=OpDesc
 313 issueLat=1
 314 opClass=SimdAddAcc
 315 opLat=1
 316
 317 [system.cpu.fuPool.FUList5.opList02]
 318 type=OpDesc
 319 issueLat=1
 320 opClass=SimdAlu
 321 opLat=1
 322
 323 [system.cpu.fuPool.FUList5.opList03]
 324 type=OpDesc
 325 issueLat=1
 326 opClass=SimdCmp
 327 opLat=1
 328
 329 [system.cpu.fuPool.FUList5.opList04]
 330 type=OpDesc
 331 issueLat=1
 332 opClass=SimdCvt
 333 opLat=1
 334
 335 [system.cpu.fuPool.FUList5.opList05]
 336 type=OpDesc
 337 issueLat=1
 338 opClass=SimdMisc
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5.opList06]
 342 type=OpDesc
 343 issueLat=1
 344 opClass=SimdMult
 345 opLat=1
 346
 347 [system.cpu.fuPool.FUList5.opList07]
 348 type=OpDesc
 349 issueLat=1
 350 opClass=SimdMultAcc
 351 opLat=1
 352
 353 [system.cpu.fuPool.FUList5.opList08]
 354 type=OpDesc
 355 issueLat=1
 356 opClass=SimdShift
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList09]
 360 type=OpDesc
 361 issueLat=1
 362 opClass=SimdShiftAcc
 363 opLat=1
 364
 365 [system.cpu.fuPool.FUList5.opList10]
 366 type=OpDesc
 367 issueLat=1
 368 opClass=SimdSqrt
 369 opLat=1
 370
 371 [system.cpu.fuPool.FUList5.opList11]
 372 type=OpDesc
 373 issueLat=1
 374 opClass=SimdFloatAdd
 375 opLat=1
 376
 377 [system.cpu.fuPool.FUList5.opList12]
 378 type=OpDesc
 379 issueLat=1
 380 opClass=SimdFloatAlu
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList13]
 384 type=OpDesc
 385 issueLat=1
 386 opClass=SimdFloatCmp
 387 opLat=1
 388
 389 [system.cpu.fuPool.FUList5.opList14]
 390 type=OpDesc
 391 issueLat=1
 392 opClass=SimdFloatCvt
 393 opLat=1
 394
 395 [system.cpu.fuPool.FUList5.opList15]
 396 type=OpDesc
 397 issueLat=1
 398 opClass=SimdFloatDiv
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList5.opList16]
 402 type=OpDesc
 403 issueLat=1
 404 opClass=SimdFloatMisc
 405 opLat=1
 406
 407 [system.cpu.fuPool.FUList5.opList17]
 408 type=OpDesc
 409 issueLat=1
 410 opClass=SimdFloatMult
 411 opLat=1
 412
 413 [system.cpu.fuPool.FUList5.opList18]
 414 type=OpDesc
 415 issueLat=1
 416 opClass=SimdFloatMultAcc
 417 opLat=1
 418
 419 [system.cpu.fuPool.FUList5.opList19]
 420 type=OpDesc
 421 issueLat=1
 422 opClass=SimdFloatSqrt
 423 opLat=1
 424
 425 [system.cpu.fuPool.FUList6]
 426 type=FUDesc
 427 children=opList
 428 count=0
 429 opList=system.cpu.fuPool.FUList6.opList
 430
 431 [system.cpu.fuPool.FUList6.opList]
 432 type=OpDesc
 433 issueLat=1
 434 opClass=MemWrite
 435 opLat=1
 436
 437 [system.cpu.fuPool.FUList7]
 438 type=FUDesc
 439 children=opList0 opList1
 440 count=4
 441 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 442
 443 [system.cpu.fuPool.FUList7.opList0]
 444 type=OpDesc
 445 issueLat=1
 446 opClass=MemRead
 447 opLat=1
 448
 449 [system.cpu.fuPool.FUList7.opList1]
 450 type=OpDesc
 451 issueLat=1
 452 opClass=MemWrite
 453 opLat=1
 454
 455 [system.cpu.fuPool.FUList8]
 456 type=FUDesc
 457 children=opList
 458 count=1
 459 opList=system.cpu.fuPool.FUList8.opList
 460
 461 [system.cpu.fuPool.FUList8.opList]
 462 type=OpDesc
 463 issueLat=3
 464 opClass=IprAccess
 465 opLat=3
 466
 467 [system.cpu.icache]
 468 type=BaseCache
 469 addr_ranges=0:18446744073709551615
 470 assoc=1
 471 block_size=64
 472 forward_snoops=true
 473 hash_delay=1
 474 is_top_level=true
 475 latency=1000
 476 max_miss_count=0
 477 mshrs=4
 478 prefetch_on_access=false
 479 prefetcher=Null
 480 prioritizeRequests=false
 481 repl=Null
 482 size=32768
 483 subblock_size=0
 484 system=system
 485 tgts_per_mshr=20
 486 trace_addr=0
 487 two_queue=false
 488 write_buffers=8
 489 cpu_side=system.cpu.icache_port
 490 mem_side=system.toL2Bus.slave[0]
 491
 492 [system.cpu.interrupts]
 493 type=ArmInterrupts
 494
 495 [system.cpu.itb]
 496 type=ArmTLB
 497 children=walker
 498 size=64
 499 walker=system.cpu.itb.walker
 500
 501 [system.cpu.itb.walker]
 502 type=ArmTableWalker
 503 max_backoff=100000
 504 min_backoff=0
 505 sys=system
 506 port=system.toL2Bus.slave[2]
 507
 508 [system.cpu.tracer]
 509 type=ExeTracer
 510
 511 [system.intrctrl]
 512 type=IntrControl
 513 sys=system
 514
 515 [system.iobus]
 516 type=Bus
 517 block_size=64
 518 bus_id=0
 519 clock=1000
 520 header_cycles=1
 521 use_default_range=false
 522 width=64
 523 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 524 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 525
 526 [system.iocache]
 527 type=BaseCache
 528 addr_ranges=0:268435455
 529 assoc=8
 530 block_size=64
 531 forward_snoops=false
 532 hash_delay=1
 533 is_top_level=false
 534 latency=50000
 535 max_miss_count=0
 536 mshrs=20
 537 prefetch_on_access=false
 538 prefetcher=Null
 539 prioritizeRequests=false
 540 repl=Null
 541 size=1024
 542 subblock_size=0
 543 system=system
 544 tgts_per_mshr=12
 545 trace_addr=0
 546 two_queue=false
 547 write_buffers=8
 548 cpu_side=system.iobus.master[25]
 549 mem_side=system.membus.slave[1]
 550
 551 [system.l2c]
 552 type=BaseCache
 553 addr_ranges=0:18446744073709551615
 554 assoc=8
 555 block_size=64
 556 forward_snoops=true
 557 hash_delay=1
 558 is_top_level=false
 559 latency=10000
 560 max_miss_count=0
 561 mshrs=92
 562 prefetch_on_access=false
 563 prefetcher=Null
 564 prioritizeRequests=false
 565 repl=Null
 566 size=4194304
 567 subblock_size=0
 568 system=system
 569 tgts_per_mshr=16
 570 trace_addr=0
 571 two_queue=false
 572 write_buffers=8
 573 cpu_side=system.toL2Bus.master[0]
 574 mem_side=system.membus.slave[2]
 575
 576 [system.membus]
 577 type=Bus
 578 children=badaddr_responder
 579 block_size=64
 580 bus_id=1
 581 clock=1000
 582 header_cycles=1
 583 use_default_range=false
 584 width=64
 585 default=system.membus.badaddr_responder.pio
 586 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 587 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 588
 589 [system.membus.badaddr_responder]
 590 type=IsaFake
 591 fake_mem=false
 592 pio_addr=0
 593 pio_latency=1000
 594 pio_size=8
 595 ret_bad_addr=true
 596 ret_data16=65535
 597 ret_data32=4294967295
 598 ret_data64=18446744073709551615
 599 ret_data8=255
 600 system=system
 601 update_data=false
 602 warn_access=warn
 603 pio=system.membus.default
 604
 605 [system.physmem]
 606 type=PhysicalMemory
 607 file=
 608 latency=30000
 609 latency_var=0
 610 null=false
 611 range=0:134217727
 612 zero=false
 613 port=system.membus.master[2]
 614
 615 [system.realview]
 616 type=RealView
 617 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 618 intrctrl=system.intrctrl
 619 max_mem_size=268435456
 620 mem_start_addr=0
 621 pci_cfg_base=0
 622 system=system
 623
 624 [system.realview.a9scu]
 625 type=A9SCU
 626 pio_addr=520093696
 627 pio_latency=1000
 628 system=system
 629 pio=system.membus.master[5]
 630
 631 [system.realview.aaci_fake]
 632 type=AmbaFake
 633 amba_id=0
 634 ignore_access=false
 635 pio_addr=268451840
 636 pio_latency=1000
 637 system=system
 638 pio=system.iobus.master[21]
 639
 640 [system.realview.cf_ctrl]
 641 type=IdeController
 642 BAR0=402653184
 643 BAR0LegacyIO=true
 644 BAR0Size=16
 645 BAR1=402653440
 646 BAR1LegacyIO=true
 647 BAR1Size=1
 648 BAR2=1
 649 BAR2LegacyIO=false
 650 BAR2Size=8
 651 BAR3=1
 652 BAR3LegacyIO=false
 653 BAR3Size=4
 654 BAR4=1
 655 BAR4LegacyIO=false
 656 BAR4Size=16
 657 BAR5=1
 658 BAR5LegacyIO=false
 659 BAR5Size=0
 660 BIST=0
 661 CacheLineSize=0
 662 CardbusCIS=0
 663 ClassCode=1
 664 Command=1
 665 DeviceID=28945
 666 ExpansionROM=0
 667 HeaderType=0
 668 InterruptLine=31
 669 InterruptPin=1
 670 LatencyTimer=0
 671 MaximumLatency=0
 672 MinimumGrant=0
 673 ProgIF=133
 674 Revision=0
 675 Status=640
 676 SubClassCode=1
 677 SubsystemID=0
 678 SubsystemVendorID=0
 679 VendorID=32902
 680 config_latency=20000
 681 ctrl_offset=2
 682 disks=system.cf0
 683 io_shift=1
 684 max_backoff_delay=10000000
 685 min_backoff_delay=4000
 686 pci_bus=2
 687 pci_dev=7
 688 pci_func=0
 689 pio_latency=1000
 690 platform=system.realview
 691 system=system
 692 config=system.iobus.master[8]
 693 dma=system.iobus.slave[2]
 694 pio=system.iobus.master[7]
 695
 696 [system.realview.clcd]
 697 type=Pl111
 698 amba_id=1315089
 699 clock=41667
 700 gic=system.realview.gic
 701 int_num=55
 702 max_backoff_delay=10000000
 703 min_backoff_delay=4000
 704 pio_addr=268566528
 705 pio_latency=10000
 706 system=system
 707 vnc=system.vncserver
 708 dma=system.iobus.slave[1]
 709 pio=system.iobus.master[4]
 710
 711 [system.realview.dmac_fake]
 712 type=AmbaFake
 713 amba_id=0
 714 ignore_access=false
 715 pio_addr=268632064
 716 pio_latency=1000
 717 system=system
 718 pio=system.iobus.master[9]
 719
 720 [system.realview.flash_fake]
 721 type=IsaFake
 722 fake_mem=true
 723 pio_addr=1073741824
 724 pio_latency=1000
 725 pio_size=536870912
 726 ret_bad_addr=false
 727 ret_data16=65535
 728 ret_data32=4294967295
 729 ret_data64=18446744073709551615
 730 ret_data8=255
 731 system=system
 732 update_data=false
 733 warn_access=
 734 pio=system.iobus.master[24]
 735
 736 [system.realview.gic]
 737 type=Gic
 738 cpu_addr=520093952
 739 cpu_pio_delay=10000
 740 dist_addr=520097792
 741 dist_pio_delay=10000
 742 int_latency=10000
 743 it_lines=128
 744 platform=system.realview
 745 system=system
 746 pio=system.membus.master[3]
 747
 748 [system.realview.gpio0_fake]
 749 type=AmbaFake
 750 amba_id=0
 751 ignore_access=false
 752 pio_addr=268513280
 753 pio_latency=1000
 754 system=system
 755 pio=system.iobus.master[16]
 756
 757 [system.realview.gpio1_fake]
 758 type=AmbaFake
 759 amba_id=0
 760 ignore_access=false
 761 pio_addr=268517376
 762 pio_latency=1000
 763 system=system
 764 pio=system.iobus.master[17]
 765
 766 [system.realview.gpio2_fake]
 767 type=AmbaFake
 768 amba_id=0
 769 ignore_access=false
 770 pio_addr=268521472
 771 pio_latency=1000
 772 system=system
 773 pio=system.iobus.master[18]
 774
 775 [system.realview.kmi0]
 776 type=Pl050
 777 amba_id=1314896
 778 gic=system.realview.gic
 779 int_delay=1000000
 780 int_num=52
 781 is_mouse=false
 782 pio_addr=268460032
 783 pio_latency=1000
 784 system=system
 785 vnc=system.vncserver
 786 pio=system.iobus.master[5]
 787
 788 [system.realview.kmi1]
 789 type=Pl050
 790 amba_id=1314896
 791 gic=system.realview.gic
 792 int_delay=1000000
 793 int_num=53
 794 is_mouse=true
 795 pio_addr=268464128
 796 pio_latency=1000
 797 system=system
 798 vnc=system.vncserver
 799 pio=system.iobus.master[6]
 800
 801 [system.realview.l2x0_fake]
 802 type=IsaFake
 803 fake_mem=false
 804 pio_addr=520101888
 805 pio_latency=1000
 806 pio_size=4095
 807 ret_bad_addr=false
 808 ret_data16=65535
 809 ret_data32=4294967295
 810 ret_data64=18446744073709551615
 811 ret_data8=255
 812 system=system
 813 update_data=false
 814 warn_access=
 815 pio=system.membus.master[4]
 816
 817 [system.realview.local_cpu_timer]
 818 type=CpuLocalTimer
 819 clock=1000
 820 gic=system.realview.gic
 821 int_num_timer=29
 822 int_num_watchdog=30
 823 pio_addr=520095232
 824 pio_latency=1000
 825 system=system
 826 pio=system.membus.master[6]
 827
 828 [system.realview.mmc_fake]
 829 type=AmbaFake
 830 amba_id=0
 831 ignore_access=false
 832 pio_addr=268455936
 833 pio_latency=1000
 834 system=system
 835 pio=system.iobus.master[22]
 836
 837 [system.realview.nvmem]
 838 type=PhysicalMemory
 839 file=
 840 latency=30000
 841 latency_var=0
 842 null=false
 843 range=2147483648:2214592511
 844 zero=true
 845 port=system.membus.master[1]
 846
 847 [system.realview.realview_io]
 848 type=RealViewCtrl
 849 idreg=0
 850 pio_addr=268435456
 851 pio_latency=1000
 852 proc_id0=201326592
 853 proc_id1=201327138
 854 system=system
 855 pio=system.iobus.master[1]
 856
 857 [system.realview.rtc_fake]
 858 type=AmbaFake
 859 amba_id=266289
 860 ignore_access=false
 861 pio_addr=268529664
 862 pio_latency=1000
 863 system=system
 864 pio=system.iobus.master[23]
 865
 866 [system.realview.sci_fake]
 867 type=AmbaFake
 868 amba_id=0
 869 ignore_access=false
 870 pio_addr=268492800
 871 pio_latency=1000
 872 system=system
 873 pio=system.iobus.master[20]
 874
 875 [system.realview.smc_fake]
 876 type=AmbaFake
 877 amba_id=0
 878 ignore_access=false
 879 pio_addr=269357056
 880 pio_latency=1000
 881 system=system
 882 pio=system.iobus.master[13]
 883
 884 [system.realview.sp810_fake]
 885 type=AmbaFake
 886 amba_id=0
 887 ignore_access=true
 888 pio_addr=268439552
 889 pio_latency=1000
 890 system=system
 891 pio=system.iobus.master[14]
 892
 893 [system.realview.ssp_fake]
 894 type=AmbaFake
 895 amba_id=0
 896 ignore_access=false
 897 pio_addr=268488704
 898 pio_latency=1000
 899 system=system
 900 pio=system.iobus.master[19]
 901
 902 [system.realview.timer0]
 903 type=Sp804
 904 amba_id=1316868
 905 clock0=1000000
 906 clock1=1000000
 907 gic=system.realview.gic
 908 int_num0=36
 909 int_num1=36
 910 pio_addr=268505088
 911 pio_latency=1000
 912 system=system
 913 pio=system.iobus.master[2]
 914
 915 [system.realview.timer1]
 916 type=Sp804
 917 amba_id=1316868
 918 clock0=1000000
 919 clock1=1000000
 920 gic=system.realview.gic
 921 int_num0=37
 922 int_num1=37
 923 pio_addr=268509184
 924 pio_latency=1000
 925 system=system
 926 pio=system.iobus.master[3]
 927
 928 [system.realview.uart]
 929 type=Pl011
 930 end_on_eot=false
 931 gic=system.realview.gic
 932 int_delay=100000
 933 int_num=44
 934 pio_addr=268472320
 935 pio_latency=1000
 936 platform=system.realview
 937 system=system
 938 terminal=system.terminal
 939 pio=system.iobus.master[0]
 940
 941 [system.realview.uart1_fake]
 942 type=AmbaFake
 943 amba_id=0
 944 ignore_access=false
 945 pio_addr=268476416
 946 pio_latency=1000
 947 system=system
 948 pio=system.iobus.master[10]
 949
 950 [system.realview.uart2_fake]
 951 type=AmbaFake
 952 amba_id=0
 953 ignore_access=false
 954 pio_addr=268480512
 955 pio_latency=1000
 956 system=system
 957 pio=system.iobus.master[11]
 958
 959 [system.realview.uart3_fake]
 960 type=AmbaFake
 961 amba_id=0
 962 ignore_access=false
 963 pio_addr=268484608
 964 pio_latency=1000
 965 system=system
 966 pio=system.iobus.master[12]
 967
 968 [system.realview.watchdog_fake]
 969 type=AmbaFake
 970 amba_id=0
 971 ignore_access=false
 972 pio_addr=268500992
 973 pio_latency=1000
 974 system=system
 975 pio=system.iobus.master[15]
 976
 977 [system.terminal]
 978 type=Terminal
 979 intr_control=system.intrctrl
 980 number=0
 981 output=true
 982 port=3456
 983
 984 [system.toL2Bus]
 985 type=Bus
 986 block_size=64
 987 bus_id=0
 988 clock=1000
 989 header_cycles=1
 990 use_default_range=false
 991 width=64
 992 master=system.l2c.cpu_side
 993 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 994
 995 [system.vncserver]
 996 type=VncServer
 997 frame_capture=false
 998 number=0
 999 port=5900
1000