tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
  12 atags_addr=256
  13 boot_loader=/dist/m5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 flags_addr=268435504
  16 gic_cpu_addr=520093952
  17 init_param=0
  18 kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  19 load_addr_mask=268435455
  20 machine_type=RealView_PBX
  21 mem_mode=timing
  22 memories=system.physmem system.realview.nvmem
  23 midr_regval=890224640
  24 num_work_ids=16
  25 readfile=tests/halt.sh
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[0]
  35
  36 [system.bridge]
  37 type=Bridge
  38 delay=50000
  39 nack_delay=4000
  40 ranges=268435456:520093695 1073741824:1610612735
  41 req_size=16
  42 resp_size=16
  43 write_ack=false
  44 master=system.iobus.slave[0]
  45 slave=system.membus.master[0]
  46
  47 [system.cf0]
  48 type=IdeDisk
  49 children=image
  50 delay=1000000
  51 driveID=master
  52 image=system.cf0.image
  53
  54 [system.cf0.image]
  55 type=CowDiskImage
  56 children=child
  57 child=system.cf0.image.child
  58 image_file=
  59 read_only=false
  60 table_size=65536
  61
  62 [system.cf0.image.child]
  63 type=RawDiskImage
  64 image_file=/dist/m5/system/disks/linux-arm-ael.img
  65 read_only=true
  66
  67 [system.cpu]
  68 type=DerivO3CPU
  69 children=dcache dtb fuPool icache interrupts itb tracer
  70 BTBEntries=4096
  71 BTBTagSize=16
  72 LFSTSize=1024
  73 LQEntries=32
  74 LSQCheckLoads=true
  75 LSQDepCheckShift=4
  76 RASSize=16
  77 SQEntries=32
  78 SSITSize=1024
  79 activity=0
  80 backComSize=5
  81 cachePorts=200
  82 checker=Null
  83 choiceCtrBits=2
  84 choicePredictorSize=8192
  85 clock=500
  86 commitToDecodeDelay=1
  87 commitToFetchDelay=1
  88 commitToIEWDelay=1
  89 commitToRenameDelay=1
  90 commitWidth=8
  91 cpu_id=0
  92 decodeToFetchDelay=1
  93 decodeToRenameDelay=1
  94 decodeWidth=8
  95 defer_registration=false
  96 dispatchWidth=8
  97 do_checkpoint_insts=true
  98 do_quiesce=true
  99 do_statistics_insts=true
 100 dtb=system.cpu.dtb
 101 fetchToDecodeDelay=1
 102 fetchTrapLatency=1
 103 fetchWidth=8
 104 forwardComSize=5
 105 fuPool=system.cpu.fuPool
 106 function_trace=false
 107 function_trace_start=0
 108 globalCtrBits=2
 109 globalHistoryBits=13
 110 globalPredictorSize=8192
 111 iewToCommitDelay=1
 112 iewToDecodeDelay=1
 113 iewToFetchDelay=1
 114 iewToRenameDelay=1
 115 instShiftAmt=2
 116 interrupts=system.cpu.interrupts
 117 issueToExecuteDelay=1
 118 issueWidth=8
 119 itb=system.cpu.itb
 120 localCtrBits=2
 121 localHistoryBits=11
 122 localHistoryTableSize=2048
 123 localPredictorSize=2048
 124 max_insts_all_threads=0
 125 max_insts_any_thread=0
 126 max_loads_all_threads=0
 127 max_loads_any_thread=0
 128 needsTSO=false
 129 numIQEntries=64
 130 numPhysFloatRegs=256
 131 numPhysIntRegs=256
 132 numROBEntries=192
 133 numRobs=1
 134 numThreads=1
 135 phase=0
 136 predType=tournament
 137 profile=0
 138 progress_interval=0
 139 renameToDecodeDelay=1
 140 renameToFetchDelay=1
 141 renameToIEWDelay=2
 142 renameToROBDelay=1
 143 renameWidth=8
 144 smtCommitPolicy=RoundRobin
 145 smtFetchPolicy=SingleThread
 146 smtIQPolicy=Partitioned
 147 smtIQThreshold=100
 148 smtLSQPolicy=Partitioned
 149 smtLSQThreshold=100
 150 smtNumFetchingThreads=1
 151 smtROBPolicy=Partitioned
 152 smtROBThreshold=100
 153 squashWidth=8
 154 store_set_clear_period=250000
 155 system=system
 156 tracer=system.cpu.tracer
 157 trapLatency=13
 158 wbDepth=1
 159 wbWidth=8
 160 workload=
 161 dcache_port=system.cpu.dcache.cpu_side
 162 icache_port=system.cpu.icache.cpu_side
 163
 164 [system.cpu.dcache]
 165 type=BaseCache
 166 addr_ranges=0:18446744073709551615
 167 assoc=4
 168 block_size=64
 169 forward_snoops=true
 170 hash_delay=1
 171 is_top_level=true
 172 latency=1000
 173 max_miss_count=0
 174 mshrs=4
 175 prefetch_on_access=false
 176 prefetcher=Null
 177 prioritizeRequests=false
 178 repl=Null
 179 size=32768
 180 subblock_size=0
 181 system=system
 182 tgts_per_mshr=20
 183 trace_addr=0
 184 two_queue=false
 185 write_buffers=8
 186 cpu_side=system.cpu.dcache_port
 187 mem_side=system.toL2Bus.slave[1]
 188
 189 [system.cpu.dtb]
 190 type=ArmTLB
 191 children=walker
 192 size=64
 193 walker=system.cpu.dtb.walker
 194
 195 [system.cpu.dtb.walker]
 196 type=ArmTableWalker
 197 max_backoff=100000
 198 min_backoff=0
 199 sys=system
 200 port=system.toL2Bus.slave[3]
 201
 202 [system.cpu.fuPool]
 203 type=FUPool
 204 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 205 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 206
 207 [system.cpu.fuPool.FUList0]
 208 type=FUDesc
 209 children=opList
 210 count=6
 211 opList=system.cpu.fuPool.FUList0.opList
 212
 213 [system.cpu.fuPool.FUList0.opList]
 214 type=OpDesc
 215 issueLat=1
 216 opClass=IntAlu
 217 opLat=1
 218
 219 [system.cpu.fuPool.FUList1]
 220 type=FUDesc
 221 children=opList0 opList1
 222 count=2
 223 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 224
 225 [system.cpu.fuPool.FUList1.opList0]
 226 type=OpDesc
 227 issueLat=1
 228 opClass=IntMult
 229 opLat=3
 230
 231 [system.cpu.fuPool.FUList1.opList1]
 232 type=OpDesc
 233 issueLat=19
 234 opClass=IntDiv
 235 opLat=20
 236
 237 [system.cpu.fuPool.FUList2]
 238 type=FUDesc
 239 children=opList0 opList1 opList2
 240 count=4
 241 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 242
 243 [system.cpu.fuPool.FUList2.opList0]
 244 type=OpDesc
 245 issueLat=1
 246 opClass=FloatAdd
 247 opLat=2
 248
 249 [system.cpu.fuPool.FUList2.opList1]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=FloatCmp
 253 opLat=2
 254
 255 [system.cpu.fuPool.FUList2.opList2]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=FloatCvt
 259 opLat=2
 260
 261 [system.cpu.fuPool.FUList3]
 262 type=FUDesc
 263 children=opList0 opList1 opList2
 264 count=2
 265 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 266
 267 [system.cpu.fuPool.FUList3.opList0]
 268 type=OpDesc
 269 issueLat=1
 270 opClass=FloatMult
 271 opLat=4
 272
 273 [system.cpu.fuPool.FUList3.opList1]
 274 type=OpDesc
 275 issueLat=12
 276 opClass=FloatDiv
 277 opLat=12
 278
 279 [system.cpu.fuPool.FUList3.opList2]
 280 type=OpDesc
 281 issueLat=24
 282 opClass=FloatSqrt
 283 opLat=24
 284
 285 [system.cpu.fuPool.FUList4]
 286 type=FUDesc
 287 children=opList
 288 count=0
 289 opList=system.cpu.fuPool.FUList4.opList
 290
 291 [system.cpu.fuPool.FUList4.opList]
 292 type=OpDesc
 293 issueLat=1
 294 opClass=MemRead
 295 opLat=1
 296
 297 [system.cpu.fuPool.FUList5]
 298 type=FUDesc
 299 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 300 count=4
 301 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 302
 303 [system.cpu.fuPool.FUList5.opList00]
 304 type=OpDesc
 305 issueLat=1
 306 opClass=SimdAdd
 307 opLat=1
 308
 309 [system.cpu.fuPool.FUList5.opList01]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdAddAcc
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList02]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdAlu
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList03]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdCmp
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList04]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdCvt
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList05]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdMisc
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList06]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdMult
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList07]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdMultAcc
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList08]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdShift
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList09]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdShiftAcc
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList10]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdSqrt
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList11]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdFloatAdd
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList12]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatAlu
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList13]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=SimdFloatCmp
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList14]
 388 type=OpDesc
 389 issueLat=1
 390 opClass=SimdFloatCvt
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList15]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=SimdFloatDiv
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList5.opList16]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=SimdFloatMisc
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList5.opList17]
 406 type=OpDesc
 407 issueLat=1
 408 opClass=SimdFloatMult
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList18]
 412 type=OpDesc
 413 issueLat=1
 414 opClass=SimdFloatMultAcc
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList5.opList19]
 418 type=OpDesc
 419 issueLat=1
 420 opClass=SimdFloatSqrt
 421 opLat=1
 422
 423 [system.cpu.fuPool.FUList6]
 424 type=FUDesc
 425 children=opList
 426 count=0
 427 opList=system.cpu.fuPool.FUList6.opList
 428
 429 [system.cpu.fuPool.FUList6.opList]
 430 type=OpDesc
 431 issueLat=1
 432 opClass=MemWrite
 433 opLat=1
 434
 435 [system.cpu.fuPool.FUList7]
 436 type=FUDesc
 437 children=opList0 opList1
 438 count=4
 439 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 440
 441 [system.cpu.fuPool.FUList7.opList0]
 442 type=OpDesc
 443 issueLat=1
 444 opClass=MemRead
 445 opLat=1
 446
 447 [system.cpu.fuPool.FUList7.opList1]
 448 type=OpDesc
 449 issueLat=1
 450 opClass=MemWrite
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList8]
 454 type=FUDesc
 455 children=opList
 456 count=1
 457 opList=system.cpu.fuPool.FUList8.opList
 458
 459 [system.cpu.fuPool.FUList8.opList]
 460 type=OpDesc
 461 issueLat=3
 462 opClass=IprAccess
 463 opLat=3
 464
 465 [system.cpu.icache]
 466 type=BaseCache
 467 addr_ranges=0:18446744073709551615
 468 assoc=1
 469 block_size=64
 470 forward_snoops=true
 471 hash_delay=1
 472 is_top_level=true
 473 latency=1000
 474 max_miss_count=0
 475 mshrs=4
 476 prefetch_on_access=false
 477 prefetcher=Null
 478 prioritizeRequests=false
 479 repl=Null
 480 size=32768
 481 subblock_size=0
 482 system=system
 483 tgts_per_mshr=20
 484 trace_addr=0
 485 two_queue=false
 486 write_buffers=8
 487 cpu_side=system.cpu.icache_port
 488 mem_side=system.toL2Bus.slave[0]
 489
 490 [system.cpu.interrupts]
 491 type=ArmInterrupts
 492
 493 [system.cpu.itb]
 494 type=ArmTLB
 495 children=walker
 496 size=64
 497 walker=system.cpu.itb.walker
 498
 499 [system.cpu.itb.walker]
 500 type=ArmTableWalker
 501 max_backoff=100000
 502 min_backoff=0
 503 sys=system
 504 port=system.toL2Bus.slave[2]
 505
 506 [system.cpu.tracer]
 507 type=ExeTracer
 508
 509 [system.intrctrl]
 510 type=IntrControl
 511 sys=system
 512
 513 [system.iobus]
 514 type=Bus
 515 block_size=64
 516 bus_id=0
 517 clock=1000
 518 header_cycles=1
 519 use_default_range=false
 520 width=64
 521 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 522 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 523
 524 [system.iocache]
 525 type=BaseCache
 526 addr_ranges=0:268435455
 527 assoc=8
 528 block_size=64
 529 forward_snoops=false
 530 hash_delay=1
 531 is_top_level=false
 532 latency=50000
 533 max_miss_count=0
 534 mshrs=20
 535 prefetch_on_access=false
 536 prefetcher=Null
 537 prioritizeRequests=false
 538 repl=Null
 539 size=1024
 540 subblock_size=0
 541 system=system
 542 tgts_per_mshr=12
 543 trace_addr=0
 544 two_queue=false
 545 write_buffers=8
 546 cpu_side=system.iobus.master[25]
 547 mem_side=system.membus.slave[1]
 548
 549 [system.l2c]
 550 type=BaseCache
 551 addr_ranges=0:18446744073709551615
 552 assoc=8
 553 block_size=64
 554 forward_snoops=true
 555 hash_delay=1
 556 is_top_level=false
 557 latency=10000
 558 max_miss_count=0
 559 mshrs=92
 560 prefetch_on_access=false
 561 prefetcher=Null
 562 prioritizeRequests=false
 563 repl=Null
 564 size=4194304
 565 subblock_size=0
 566 system=system
 567 tgts_per_mshr=16
 568 trace_addr=0
 569 two_queue=false
 570 write_buffers=8
 571 cpu_side=system.toL2Bus.master[0]
 572 mem_side=system.membus.slave[2]
 573
 574 [system.membus]
 575 type=Bus
 576 children=badaddr_responder
 577 block_size=64
 578 bus_id=1
 579 clock=1000
 580 header_cycles=1
 581 use_default_range=false
 582 width=64
 583 default=system.membus.badaddr_responder.pio
 584 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 585 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 586
 587 [system.membus.badaddr_responder]
 588 type=IsaFake
 589 fake_mem=false
 590 pio_addr=0
 591 pio_latency=1000
 592 pio_size=8
 593 ret_bad_addr=true
 594 ret_data16=65535
 595 ret_data32=4294967295
 596 ret_data64=18446744073709551615
 597 ret_data8=255
 598 system=system
 599 update_data=false
 600 warn_access=warn
 601 pio=system.membus.default
 602
 603 [system.physmem]
 604 type=SimpleMemory
 605 conf_table_reported=true
 606 file=
 607 in_addr_map=true
 608 latency=30000
 609 latency_var=0
 610 null=false
 611 range=0:134217727
 612 zero=false
 613 port=system.membus.master[2]
 614
 615 [system.realview]
 616 type=RealView
 617 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 618 intrctrl=system.intrctrl
 619 max_mem_size=268435456
 620 mem_start_addr=0
 621 pci_cfg_base=0
 622 system=system
 623
 624 [system.realview.a9scu]
 625 type=A9SCU
 626 pio_addr=520093696
 627 pio_latency=1000
 628 system=system
 629 pio=system.membus.master[5]
 630
 631 [system.realview.aaci_fake]
 632 type=AmbaFake
 633 amba_id=0
 634 ignore_access=false
 635 pio_addr=268451840
 636 pio_latency=1000
 637 system=system
 638 pio=system.iobus.master[21]
 639
 640 [system.realview.cf_ctrl]
 641 type=IdeController
 642 BAR0=402653184
 643 BAR0LegacyIO=true
 644 BAR0Size=16
 645 BAR1=402653440
 646 BAR1LegacyIO=true
 647 BAR1Size=1
 648 BAR2=1
 649 BAR2LegacyIO=false
 650 BAR2Size=8
 651 BAR3=1
 652 BAR3LegacyIO=false
 653 BAR3Size=4
 654 BAR4=1
 655 BAR4LegacyIO=false
 656 BAR4Size=16
 657 BAR5=1
 658 BAR5LegacyIO=false
 659 BAR5Size=0
 660 BIST=0
 661 CacheLineSize=0
 662 CardbusCIS=0
 663 ClassCode=1
 664 Command=1
 665 DeviceID=28945
 666 ExpansionROM=0
 667 HeaderType=0
 668 InterruptLine=31
 669 InterruptPin=1
 670 LatencyTimer=0
 671 MaximumLatency=0
 672 MinimumGrant=0
 673 ProgIF=133
 674 Revision=0
 675 Status=640
 676 SubClassCode=1
 677 SubsystemID=0
 678 SubsystemVendorID=0
 679 VendorID=32902
 680 config_latency=20000
 681 ctrl_offset=2
 682 disks=system.cf0
 683 io_shift=1
 684 max_backoff_delay=10000000
 685 min_backoff_delay=4000
 686 pci_bus=2
 687 pci_dev=7
 688 pci_func=0
 689 pio_latency=1000
 690 platform=system.realview
 691 system=system
 692 config=system.iobus.master[8]
 693 dma=system.iobus.slave[2]
 694 pio=system.iobus.master[7]
 695
 696 [system.realview.clcd]
 697 type=Pl111
 698 amba_id=1315089
 699 clock=41667
 700 gic=system.realview.gic
 701 int_num=55
 702 max_backoff_delay=10000000
 703 min_backoff_delay=4000
 704 pio_addr=268566528
 705 pio_latency=10000
 706 system=system
 707 vnc=system.vncserver
 708 dma=system.iobus.slave[1]
 709 pio=system.iobus.master[4]
 710
 711 [system.realview.dmac_fake]
 712 type=AmbaFake
 713 amba_id=0
 714 ignore_access=false
 715 pio_addr=268632064
 716 pio_latency=1000
 717 system=system
 718 pio=system.iobus.master[9]
 719
 720 [system.realview.flash_fake]
 721 type=IsaFake
 722 fake_mem=true
 723 pio_addr=1073741824
 724 pio_latency=1000
 725 pio_size=536870912
 726 ret_bad_addr=false
 727 ret_data16=65535
 728 ret_data32=4294967295
 729 ret_data64=18446744073709551615
 730 ret_data8=255
 731 system=system
 732 update_data=false
 733 warn_access=
 734 pio=system.iobus.master[24]
 735
 736 [system.realview.gic]
 737 type=Gic
 738 cpu_addr=520093952
 739 cpu_pio_delay=10000
 740 dist_addr=520097792
 741 dist_pio_delay=10000
 742 int_latency=10000
 743 it_lines=128
 744 platform=system.realview
 745 system=system
 746 pio=system.membus.master[3]
 747
 748 [system.realview.gpio0_fake]
 749 type=AmbaFake
 750 amba_id=0
 751 ignore_access=false
 752 pio_addr=268513280
 753 pio_latency=1000
 754 system=system
 755 pio=system.iobus.master[16]
 756
 757 [system.realview.gpio1_fake]
 758 type=AmbaFake
 759 amba_id=0
 760 ignore_access=false
 761 pio_addr=268517376
 762 pio_latency=1000
 763 system=system
 764 pio=system.iobus.master[17]
 765
 766 [system.realview.gpio2_fake]
 767 type=AmbaFake
 768 amba_id=0
 769 ignore_access=false
 770 pio_addr=268521472
 771 pio_latency=1000
 772 system=system
 773 pio=system.iobus.master[18]
 774
 775 [system.realview.kmi0]
 776 type=Pl050
 777 amba_id=1314896
 778 gic=system.realview.gic
 779 int_delay=1000000
 780 int_num=52
 781 is_mouse=false
 782 pio_addr=268460032
 783 pio_latency=1000
 784 system=system
 785 vnc=system.vncserver
 786 pio=system.iobus.master[5]
 787
 788 [system.realview.kmi1]
 789 type=Pl050
 790 amba_id=1314896
 791 gic=system.realview.gic
 792 int_delay=1000000
 793 int_num=53
 794 is_mouse=true
 795 pio_addr=268464128
 796 pio_latency=1000
 797 system=system
 798 vnc=system.vncserver
 799 pio=system.iobus.master[6]
 800
 801 [system.realview.l2x0_fake]
 802 type=IsaFake
 803 fake_mem=false
 804 pio_addr=520101888
 805 pio_latency=1000
 806 pio_size=4095
 807 ret_bad_addr=false
 808 ret_data16=65535
 809 ret_data32=4294967295
 810 ret_data64=18446744073709551615
 811 ret_data8=255
 812 system=system
 813 update_data=false
 814 warn_access=
 815 pio=system.membus.master[4]
 816
 817 [system.realview.local_cpu_timer]
 818 type=CpuLocalTimer
 819 clock=1000
 820 gic=system.realview.gic
 821 int_num_timer=29
 822 int_num_watchdog=30
 823 pio_addr=520095232
 824 pio_latency=1000
 825 system=system
 826 pio=system.membus.master[6]
 827
 828 [system.realview.mmc_fake]
 829 type=AmbaFake
 830 amba_id=0
 831 ignore_access=false
 832 pio_addr=268455936
 833 pio_latency=1000
 834 system=system
 835 pio=system.iobus.master[22]
 836
 837 [system.realview.nvmem]
 838 type=SimpleMemory
 839 conf_table_reported=false
 840 file=
 841 in_addr_map=true
 842 latency=30000
 843 latency_var=0
 844 null=false
 845 range=2147483648:2214592511
 846 zero=true
 847 port=system.membus.master[1]
 848
 849 [system.realview.realview_io]
 850 type=RealViewCtrl
 851 idreg=0
 852 pio_addr=268435456
 853 pio_latency=1000
 854 proc_id0=201326592
 855 proc_id1=201327138
 856 system=system
 857 pio=system.iobus.master[1]
 858
 859 [system.realview.rtc]
 860 type=PL031
 861 amba_id=3412017
 862 gic=system.realview.gic
 863 int_delay=100000
 864 int_num=42
 865 pio_addr=268529664
 866 pio_latency=1000
 867 system=system
 868 time=Thu Jan  1 00:00:00 2009
 869 pio=system.iobus.master[23]
 870
 871 [system.realview.sci_fake]
 872 type=AmbaFake
 873 amba_id=0
 874 ignore_access=false
 875 pio_addr=268492800
 876 pio_latency=1000
 877 system=system
 878 pio=system.iobus.master[20]
 879
 880 [system.realview.smc_fake]
 881 type=AmbaFake
 882 amba_id=0
 883 ignore_access=false
 884 pio_addr=269357056
 885 pio_latency=1000
 886 system=system
 887 pio=system.iobus.master[13]
 888
 889 [system.realview.sp810_fake]
 890 type=AmbaFake
 891 amba_id=0
 892 ignore_access=true
 893 pio_addr=268439552
 894 pio_latency=1000
 895 system=system
 896 pio=system.iobus.master[14]
 897
 898 [system.realview.ssp_fake]
 899 type=AmbaFake
 900 amba_id=0
 901 ignore_access=false
 902 pio_addr=268488704
 903 pio_latency=1000
 904 system=system
 905 pio=system.iobus.master[19]
 906
 907 [system.realview.timer0]
 908 type=Sp804
 909 amba_id=1316868
 910 clock0=1000000
 911 clock1=1000000
 912 gic=system.realview.gic
 913 int_num0=36
 914 int_num1=36
 915 pio_addr=268505088
 916 pio_latency=1000
 917 system=system
 918 pio=system.iobus.master[2]
 919
 920 [system.realview.timer1]
 921 type=Sp804
 922 amba_id=1316868
 923 clock0=1000000
 924 clock1=1000000
 925 gic=system.realview.gic
 926 int_num0=37
 927 int_num1=37
 928 pio_addr=268509184
 929 pio_latency=1000
 930 system=system
 931 pio=system.iobus.master[3]
 932
 933 [system.realview.uart]
 934 type=Pl011
 935 end_on_eot=false
 936 gic=system.realview.gic
 937 int_delay=100000
 938 int_num=44
 939 pio_addr=268472320
 940 pio_latency=1000
 941 platform=system.realview
 942 system=system
 943 terminal=system.terminal
 944 pio=system.iobus.master[0]
 945
 946 [system.realview.uart1_fake]
 947 type=AmbaFake
 948 amba_id=0
 949 ignore_access=false
 950 pio_addr=268476416
 951 pio_latency=1000
 952 system=system
 953 pio=system.iobus.master[10]
 954
 955 [system.realview.uart2_fake]
 956 type=AmbaFake
 957 amba_id=0
 958 ignore_access=false
 959 pio_addr=268480512
 960 pio_latency=1000
 961 system=system
 962 pio=system.iobus.master[11]
 963
 964 [system.realview.uart3_fake]
 965 type=AmbaFake
 966 amba_id=0
 967 ignore_access=false
 968 pio_addr=268484608
 969 pio_latency=1000
 970 system=system
 971 pio=system.iobus.master[12]
 972
 973 [system.realview.watchdog_fake]
 974 type=AmbaFake
 975 amba_id=0
 976 ignore_access=false
 977 pio_addr=268500992
 978 pio_latency=1000
 979 system=system
 980 pio=system.iobus.master[15]
 981
 982 [system.terminal]
 983 type=Terminal
 984 intr_control=system.intrctrl
 985 number=0
 986 output=true
 987 port=3456
 988
 989 [system.toL2Bus]
 990 type=Bus
 991 block_size=64
 992 bus_id=0
 993 clock=1000
 994 header_cycles=1
 995 use_default_range=false
 996 width=64
 997 master=system.l2c.cpu_side
 998 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 999
1000 [system.vncserver]
1001 type=VncServer
1002 frame_capture=false
1003 number=0
1004 port=5900
1005