tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
  12 boot_loader=/dist/m5/system/binaries/boot.arm
  13 boot_loader_mem=system.nvmem
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 flags_addr=268435504
  16 gic_cpu_addr=520093952
  17 init_param=0
  18 kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  19 load_addr_mask=268435455
  20 machine_type=RealView_PBX
  21 mem_mode=timing
  22 memories=system.nvmem system.physmem
  23 midr_regval=890224640
  24 num_work_ids=16
  25 physmem=system.physmem
  26 readfile=tests/halt.sh
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.port[7]
  36
  37 [system.bridge]
  38 type=Bridge
  39 delay=50000
  40 nack_delay=4000
  41 ranges=268435456:520093695 1073741824:18446744073709551615
  42 req_size=16
  43 resp_size=16
  44 write_ack=false
  45 master=system.iobus.port[0]
  46 slave=system.membus.port[0]
  47
  48 [system.cf0]
  49 type=IdeDisk
  50 children=image
  51 delay=1000000
  52 driveID=master
  53 image=system.cf0.image
  54
  55 [system.cf0.image]
  56 type=CowDiskImage
  57 children=child
  58 child=system.cf0.image.child
  59 image_file=
  60 read_only=false
  61 table_size=65536
  62
  63 [system.cf0.image.child]
  64 type=RawDiskImage
  65 image_file=/dist/m5/system/disks/linux-arm-ael.img
  66 read_only=true
  67
  68 [system.cpu]
  69 type=DerivO3CPU
  70 children=dcache dtb fuPool icache interrupts itb tracer
  71 BTBEntries=4096
  72 BTBTagSize=16
  73 LFSTSize=1024
  74 LQEntries=32
  75 LSQCheckLoads=true
  76 LSQDepCheckShift=4
  77 RASSize=16
  78 SQEntries=32
  79 SSITSize=1024
  80 activity=0
  81 backComSize=5
  82 cachePorts=200
  83 checker=Null
  84 choiceCtrBits=2
  85 choicePredictorSize=8192
  86 clock=500
  87 commitToDecodeDelay=1
  88 commitToFetchDelay=1
  89 commitToIEWDelay=1
  90 commitToRenameDelay=1
  91 commitWidth=8
  92 cpu_id=0
  93 decodeToFetchDelay=1
  94 decodeToRenameDelay=1
  95 decodeWidth=8
  96 defer_registration=false
  97 dispatchWidth=8
  98 do_checkpoint_insts=true
  99 do_quiesce=true
 100 do_statistics_insts=true
 101 dtb=system.cpu.dtb
 102 fetchToDecodeDelay=1
 103 fetchTrapLatency=1
 104 fetchWidth=8
 105 forwardComSize=5
 106 fuPool=system.cpu.fuPool
 107 function_trace=false
 108 function_trace_start=0
 109 globalCtrBits=2
 110 globalHistoryBits=13
 111 globalPredictorSize=8192
 112 iewToCommitDelay=1
 113 iewToDecodeDelay=1
 114 iewToFetchDelay=1
 115 iewToRenameDelay=1
 116 instShiftAmt=2
 117 interrupts=system.cpu.interrupts
 118 issueToExecuteDelay=1
 119 issueWidth=8
 120 itb=system.cpu.itb
 121 localCtrBits=2
 122 localHistoryBits=11
 123 localHistoryTableSize=2048
 124 localPredictorSize=2048
 125 max_insts_all_threads=0
 126 max_insts_any_thread=0
 127 max_loads_all_threads=0
 128 max_loads_any_thread=0
 129 needsTSO=false
 130 numIQEntries=64
 131 numPhysFloatRegs=256
 132 numPhysIntRegs=256
 133 numROBEntries=192
 134 numRobs=1
 135 numThreads=1
 136 phase=0
 137 predType=tournament
 138 profile=0
 139 progress_interval=0
 140 renameToDecodeDelay=1
 141 renameToFetchDelay=1
 142 renameToIEWDelay=2
 143 renameToROBDelay=1
 144 renameWidth=8
 145 smtCommitPolicy=RoundRobin
 146 smtFetchPolicy=SingleThread
 147 smtIQPolicy=Partitioned
 148 smtIQThreshold=100
 149 smtLSQPolicy=Partitioned
 150 smtLSQThreshold=100
 151 smtNumFetchingThreads=1
 152 smtROBPolicy=Partitioned
 153 smtROBThreshold=100
 154 squashWidth=8
 155 store_set_clear_period=250000
 156 system=system
 157 tracer=system.cpu.tracer
 158 trapLatency=13
 159 wbDepth=1
 160 wbWidth=8
 161 workload=
 162 dcache_port=system.cpu.dcache.cpu_side
 163 icache_port=system.cpu.icache.cpu_side
 164
 165 [system.cpu.dcache]
 166 type=BaseCache
 167 addr_range=0:18446744073709551615
 168 assoc=4
 169 block_size=64
 170 forward_snoops=true
 171 hash_delay=1
 172 is_top_level=true
 173 latency=1000
 174 max_miss_count=0
 175 mshrs=4
 176 prefetch_on_access=false
 177 prefetcher=Null
 178 prioritizeRequests=false
 179 repl=Null
 180 size=32768
 181 subblock_size=0
 182 system=system
 183 tgts_per_mshr=20
 184 trace_addr=0
 185 two_queue=false
 186 write_buffers=8
 187 cpu_side=system.cpu.dcache_port
 188 mem_side=system.toL2Bus.port[2]
 189
 190 [system.cpu.dtb]
 191 type=ArmTLB
 192 children=walker
 193 size=64
 194 walker=system.cpu.dtb.walker
 195
 196 [system.cpu.dtb.walker]
 197 type=ArmTableWalker
 198 max_backoff=100000
 199 min_backoff=0
 200 sys=system
 201 port=system.toL2Bus.port[4]
 202
 203 [system.cpu.fuPool]
 204 type=FUPool
 205 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 206 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 207
 208 [system.cpu.fuPool.FUList0]
 209 type=FUDesc
 210 children=opList
 211 count=6
 212 opList=system.cpu.fuPool.FUList0.opList
 213
 214 [system.cpu.fuPool.FUList0.opList]
 215 type=OpDesc
 216 issueLat=1
 217 opClass=IntAlu
 218 opLat=1
 219
 220 [system.cpu.fuPool.FUList1]
 221 type=FUDesc
 222 children=opList0 opList1
 223 count=2
 224 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 225
 226 [system.cpu.fuPool.FUList1.opList0]
 227 type=OpDesc
 228 issueLat=1
 229 opClass=IntMult
 230 opLat=3
 231
 232 [system.cpu.fuPool.FUList1.opList1]
 233 type=OpDesc
 234 issueLat=19
 235 opClass=IntDiv
 236 opLat=20
 237
 238 [system.cpu.fuPool.FUList2]
 239 type=FUDesc
 240 children=opList0 opList1 opList2
 241 count=4
 242 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 243
 244 [system.cpu.fuPool.FUList2.opList0]
 245 type=OpDesc
 246 issueLat=1
 247 opClass=FloatAdd
 248 opLat=2
 249
 250 [system.cpu.fuPool.FUList2.opList1]
 251 type=OpDesc
 252 issueLat=1
 253 opClass=FloatCmp
 254 opLat=2
 255
 256 [system.cpu.fuPool.FUList2.opList2]
 257 type=OpDesc
 258 issueLat=1
 259 opClass=FloatCvt
 260 opLat=2
 261
 262 [system.cpu.fuPool.FUList3]
 263 type=FUDesc
 264 children=opList0 opList1 opList2
 265 count=2
 266 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 267
 268 [system.cpu.fuPool.FUList3.opList0]
 269 type=OpDesc
 270 issueLat=1
 271 opClass=FloatMult
 272 opLat=4
 273
 274 [system.cpu.fuPool.FUList3.opList1]
 275 type=OpDesc
 276 issueLat=12
 277 opClass=FloatDiv
 278 opLat=12
 279
 280 [system.cpu.fuPool.FUList3.opList2]
 281 type=OpDesc
 282 issueLat=24
 283 opClass=FloatSqrt
 284 opLat=24
 285
 286 [system.cpu.fuPool.FUList4]
 287 type=FUDesc
 288 children=opList
 289 count=0
 290 opList=system.cpu.fuPool.FUList4.opList
 291
 292 [system.cpu.fuPool.FUList4.opList]
 293 type=OpDesc
 294 issueLat=1
 295 opClass=MemRead
 296 opLat=1
 297
 298 [system.cpu.fuPool.FUList5]
 299 type=FUDesc
 300 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 301 count=4
 302 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 303
 304 [system.cpu.fuPool.FUList5.opList00]
 305 type=OpDesc
 306 issueLat=1
 307 opClass=SimdAdd
 308 opLat=1
 309
 310 [system.cpu.fuPool.FUList5.opList01]
 311 type=OpDesc
 312 issueLat=1
 313 opClass=SimdAddAcc
 314 opLat=1
 315
 316 [system.cpu.fuPool.FUList5.opList02]
 317 type=OpDesc
 318 issueLat=1
 319 opClass=SimdAlu
 320 opLat=1
 321
 322 [system.cpu.fuPool.FUList5.opList03]
 323 type=OpDesc
 324 issueLat=1
 325 opClass=SimdCmp
 326 opLat=1
 327
 328 [system.cpu.fuPool.FUList5.opList04]
 329 type=OpDesc
 330 issueLat=1
 331 opClass=SimdCvt
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList05]
 335 type=OpDesc
 336 issueLat=1
 337 opClass=SimdMisc
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList06]
 341 type=OpDesc
 342 issueLat=1
 343 opClass=SimdMult
 344 opLat=1
 345
 346 [system.cpu.fuPool.FUList5.opList07]
 347 type=OpDesc
 348 issueLat=1
 349 opClass=SimdMultAcc
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList08]
 353 type=OpDesc
 354 issueLat=1
 355 opClass=SimdShift
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList09]
 359 type=OpDesc
 360 issueLat=1
 361 opClass=SimdShiftAcc
 362 opLat=1
 363
 364 [system.cpu.fuPool.FUList5.opList10]
 365 type=OpDesc
 366 issueLat=1
 367 opClass=SimdSqrt
 368 opLat=1
 369
 370 [system.cpu.fuPool.FUList5.opList11]
 371 type=OpDesc
 372 issueLat=1
 373 opClass=SimdFloatAdd
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList5.opList12]
 377 type=OpDesc
 378 issueLat=1
 379 opClass=SimdFloatAlu
 380 opLat=1
 381
 382 [system.cpu.fuPool.FUList5.opList13]
 383 type=OpDesc
 384 issueLat=1
 385 opClass=SimdFloatCmp
 386 opLat=1
 387
 388 [system.cpu.fuPool.FUList5.opList14]
 389 type=OpDesc
 390 issueLat=1
 391 opClass=SimdFloatCvt
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList5.opList15]
 395 type=OpDesc
 396 issueLat=1
 397 opClass=SimdFloatDiv
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList5.opList16]
 401 type=OpDesc
 402 issueLat=1
 403 opClass=SimdFloatMisc
 404 opLat=1
 405
 406 [system.cpu.fuPool.FUList5.opList17]
 407 type=OpDesc
 408 issueLat=1
 409 opClass=SimdFloatMult
 410 opLat=1
 411
 412 [system.cpu.fuPool.FUList5.opList18]
 413 type=OpDesc
 414 issueLat=1
 415 opClass=SimdFloatMultAcc
 416 opLat=1
 417
 418 [system.cpu.fuPool.FUList5.opList19]
 419 type=OpDesc
 420 issueLat=1
 421 opClass=SimdFloatSqrt
 422 opLat=1
 423
 424 [system.cpu.fuPool.FUList6]
 425 type=FUDesc
 426 children=opList
 427 count=0
 428 opList=system.cpu.fuPool.FUList6.opList
 429
 430 [system.cpu.fuPool.FUList6.opList]
 431 type=OpDesc
 432 issueLat=1
 433 opClass=MemWrite
 434 opLat=1
 435
 436 [system.cpu.fuPool.FUList7]
 437 type=FUDesc
 438 children=opList0 opList1
 439 count=4
 440 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 441
 442 [system.cpu.fuPool.FUList7.opList0]
 443 type=OpDesc
 444 issueLat=1
 445 opClass=MemRead
 446 opLat=1
 447
 448 [system.cpu.fuPool.FUList7.opList1]
 449 type=OpDesc
 450 issueLat=1
 451 opClass=MemWrite
 452 opLat=1
 453
 454 [system.cpu.fuPool.FUList8]
 455 type=FUDesc
 456 children=opList
 457 count=1
 458 opList=system.cpu.fuPool.FUList8.opList
 459
 460 [system.cpu.fuPool.FUList8.opList]
 461 type=OpDesc
 462 issueLat=3
 463 opClass=IprAccess
 464 opLat=3
 465
 466 [system.cpu.icache]
 467 type=BaseCache
 468 addr_range=0:18446744073709551615
 469 assoc=1
 470 block_size=64
 471 forward_snoops=true
 472 hash_delay=1
 473 is_top_level=true
 474 latency=1000
 475 max_miss_count=0
 476 mshrs=4
 477 prefetch_on_access=false
 478 prefetcher=Null
 479 prioritizeRequests=false
 480 repl=Null
 481 size=32768
 482 subblock_size=0
 483 system=system
 484 tgts_per_mshr=20
 485 trace_addr=0
 486 two_queue=false
 487 write_buffers=8
 488 cpu_side=system.cpu.icache_port
 489 mem_side=system.toL2Bus.port[1]
 490
 491 [system.cpu.interrupts]
 492 type=ArmInterrupts
 493
 494 [system.cpu.itb]
 495 type=ArmTLB
 496 children=walker
 497 size=64
 498 walker=system.cpu.itb.walker
 499
 500 [system.cpu.itb.walker]
 501 type=ArmTableWalker
 502 max_backoff=100000
 503 min_backoff=0
 504 sys=system
 505 port=system.toL2Bus.port[3]
 506
 507 [system.cpu.tracer]
 508 type=ExeTracer
 509
 510 [system.intrctrl]
 511 type=IntrControl
 512 sys=system
 513
 514 [system.iobus]
 515 type=Bus
 516 block_size=64
 517 bus_id=0
 518 clock=1000
 519 header_cycles=1
 520 use_default_range=false
 521 width=64
 522 port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 523
 524 [system.iocache]
 525 type=BaseCache
 526 addr_range=0:268435455
 527 assoc=8
 528 block_size=64
 529 forward_snoops=false
 530 hash_delay=1
 531 is_top_level=false
 532 latency=50000
 533 max_miss_count=0
 534 mshrs=20
 535 prefetch_on_access=false
 536 prefetcher=Null
 537 prioritizeRequests=false
 538 repl=Null
 539 size=1024
 540 subblock_size=0
 541 system=system
 542 tgts_per_mshr=12
 543 trace_addr=0
 544 two_queue=false
 545 write_buffers=8
 546 cpu_side=system.iobus.port[28]
 547 mem_side=system.membus.port[8]
 548
 549 [system.l2c]
 550 type=BaseCache
 551 addr_range=0:18446744073709551615
 552 assoc=8
 553 block_size=64
 554 forward_snoops=true
 555 hash_delay=1
 556 is_top_level=false
 557 latency=10000
 558 max_miss_count=0
 559 mshrs=92
 560 prefetch_on_access=false
 561 prefetcher=Null
 562 prioritizeRequests=false
 563 repl=Null
 564 size=4194304
 565 subblock_size=0
 566 system=system
 567 tgts_per_mshr=16
 568 trace_addr=0
 569 two_queue=false
 570 write_buffers=8
 571 cpu_side=system.toL2Bus.port[0]
 572 mem_side=system.membus.port[9]
 573
 574 [system.membus]
 575 type=Bus
 576 children=badaddr_responder
 577 block_size=64
 578 bus_id=1
 579 clock=1000
 580 header_cycles=1
 581 use_default_range=false
 582 width=64
 583 default=system.membus.badaddr_responder.pio
 584 port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 585
 586 [system.membus.badaddr_responder]
 587 type=IsaFake
 588 fake_mem=false
 589 pio_addr=0
 590 pio_latency=1000
 591 pio_size=8
 592 ret_bad_addr=true
 593 ret_data16=65535
 594 ret_data32=4294967295
 595 ret_data64=18446744073709551615
 596 ret_data8=255
 597 system=system
 598 update_data=false
 599 warn_access=warn
 600 pio=system.membus.default
 601
 602 [system.nvmem]
 603 type=PhysicalMemory
 604 file=
 605 latency=30000
 606 latency_var=0
 607 null=false
 608 range=2147483648:2214592511
 609 zero=true
 610 port=system.membus.port[1]
 611
 612 [system.physmem]
 613 type=PhysicalMemory
 614 file=
 615 latency=30000
 616 latency_var=0
 617 null=false
 618 range=0:134217727
 619 zero=true
 620 port=system.membus.port[2]
 621
 622 [system.realview]
 623 type=RealView
 624 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 625 intrctrl=system.intrctrl
 626 pci_cfg_base=0
 627 system=system
 628
 629 [system.realview.a9scu]
 630 type=A9SCU
 631 pio_addr=520093696
 632 pio_latency=1000
 633 system=system
 634 pio=system.membus.port[5]
 635
 636 [system.realview.aaci_fake]
 637 type=AmbaFake
 638 amba_id=0
 639 ignore_access=false
 640 pio_addr=268451840
 641 pio_latency=1000
 642 system=system
 643 pio=system.iobus.port[24]
 644
 645 [system.realview.cf_ctrl]
 646 type=IdeController
 647 BAR0=402653184
 648 BAR0LegacyIO=true
 649 BAR0Size=16
 650 BAR1=402653440
 651 BAR1LegacyIO=true
 652 BAR1Size=1
 653 BAR2=1
 654 BAR2LegacyIO=false
 655 BAR2Size=8
 656 BAR3=1
 657 BAR3LegacyIO=false
 658 BAR3Size=4
 659 BAR4=1
 660 BAR4LegacyIO=false
 661 BAR4Size=16
 662 BAR5=1
 663 BAR5LegacyIO=false
 664 BAR5Size=0
 665 BIST=0
 666 CacheLineSize=0
 667 CardbusCIS=0
 668 ClassCode=1
 669 Command=1
 670 DeviceID=28945
 671 ExpansionROM=0
 672 HeaderType=0
 673 InterruptLine=31
 674 InterruptPin=1
 675 LatencyTimer=0
 676 MaximumLatency=0
 677 MinimumGrant=0
 678 ProgIF=133
 679 Revision=0
 680 Status=640
 681 SubClassCode=1
 682 SubsystemID=0
 683 SubsystemVendorID=0
 684 VendorID=32902
 685 config_latency=20000
 686 ctrl_offset=2
 687 disks=system.cf0
 688 io_shift=1
 689 max_backoff_delay=10000000
 690 min_backoff_delay=4000
 691 pci_bus=2
 692 pci_dev=7
 693 pci_func=0
 694 pio_latency=1000
 695 platform=system.realview
 696 system=system
 697 config=system.iobus.port[10]
 698 dma=system.iobus.port[11]
 699 pio=system.iobus.port[9]
 700
 701 [system.realview.clcd]
 702 type=Pl111
 703 amba_id=1315089
 704 clock=41667
 705 gic=system.realview.gic
 706 int_num=55
 707 max_backoff_delay=10000000
 708 min_backoff_delay=4000
 709 pio_addr=268566528
 710 pio_latency=10000
 711 system=system
 712 vnc=system.vncserver
 713 dma=system.iobus.port[6]
 714 pio=system.iobus.port[5]
 715
 716 [system.realview.dmac_fake]
 717 type=AmbaFake
 718 amba_id=0
 719 ignore_access=false
 720 pio_addr=268632064
 721 pio_latency=1000
 722 system=system
 723 pio=system.iobus.port[12]
 724
 725 [system.realview.flash_fake]
 726 type=IsaFake
 727 fake_mem=true
 728 pio_addr=1073741824
 729 pio_latency=1000
 730 pio_size=536870912
 731 ret_bad_addr=false
 732 ret_data16=65535
 733 ret_data32=4294967295
 734 ret_data64=18446744073709551615
 735 ret_data8=255
 736 system=system
 737 update_data=false
 738 warn_access=
 739 pio=system.iobus.port[27]
 740
 741 [system.realview.gic]
 742 type=Gic
 743 cpu_addr=520093952
 744 cpu_pio_delay=10000
 745 dist_addr=520097792
 746 dist_pio_delay=10000
 747 int_latency=10000
 748 it_lines=128
 749 platform=system.realview
 750 system=system
 751 pio=system.membus.port[3]
 752
 753 [system.realview.gpio0_fake]
 754 type=AmbaFake
 755 amba_id=0
 756 ignore_access=false
 757 pio_addr=268513280
 758 pio_latency=1000
 759 system=system
 760 pio=system.iobus.port[19]
 761
 762 [system.realview.gpio1_fake]
 763 type=AmbaFake
 764 amba_id=0
 765 ignore_access=false
 766 pio_addr=268517376
 767 pio_latency=1000
 768 system=system
 769 pio=system.iobus.port[20]
 770
 771 [system.realview.gpio2_fake]
 772 type=AmbaFake
 773 amba_id=0
 774 ignore_access=false
 775 pio_addr=268521472
 776 pio_latency=1000
 777 system=system
 778 pio=system.iobus.port[21]
 779
 780 [system.realview.kmi0]
 781 type=Pl050
 782 amba_id=1314896
 783 gic=system.realview.gic
 784 int_delay=1000000
 785 int_num=52
 786 is_mouse=false
 787 pio_addr=268460032
 788 pio_latency=1000
 789 system=system
 790 vnc=system.vncserver
 791 pio=system.iobus.port[7]
 792
 793 [system.realview.kmi1]
 794 type=Pl050
 795 amba_id=1314896
 796 gic=system.realview.gic
 797 int_delay=1000000
 798 int_num=53
 799 is_mouse=true
 800 pio_addr=268464128
 801 pio_latency=1000
 802 system=system
 803 vnc=system.vncserver
 804 pio=system.iobus.port[8]
 805
 806 [system.realview.l2x0_fake]
 807 type=IsaFake
 808 fake_mem=false
 809 pio_addr=520101888
 810 pio_latency=1000
 811 pio_size=4095
 812 ret_bad_addr=false
 813 ret_data16=65535
 814 ret_data32=4294967295
 815 ret_data64=18446744073709551615
 816 ret_data8=255
 817 system=system
 818 update_data=false
 819 warn_access=
 820 pio=system.membus.port[4]
 821
 822 [system.realview.local_cpu_timer]
 823 type=CpuLocalTimer
 824 clock=1000
 825 gic=system.realview.gic
 826 int_num_timer=29
 827 int_num_watchdog=30
 828 pio_addr=520095232
 829 pio_latency=1000
 830 system=system
 831 pio=system.membus.port[6]
 832
 833 [system.realview.mmc_fake]
 834 type=AmbaFake
 835 amba_id=0
 836 ignore_access=false
 837 pio_addr=268455936
 838 pio_latency=1000
 839 system=system
 840 pio=system.iobus.port[25]
 841
 842 [system.realview.realview_io]
 843 type=RealViewCtrl
 844 idreg=0
 845 pio_addr=268435456
 846 pio_latency=1000
 847 proc_id0=201326592
 848 proc_id1=201327138
 849 system=system
 850 pio=system.iobus.port[2]
 851
 852 [system.realview.rtc_fake]
 853 type=AmbaFake
 854 amba_id=266289
 855 ignore_access=false
 856 pio_addr=268529664
 857 pio_latency=1000
 858 system=system
 859 pio=system.iobus.port[26]
 860
 861 [system.realview.sci_fake]
 862 type=AmbaFake
 863 amba_id=0
 864 ignore_access=false
 865 pio_addr=268492800
 866 pio_latency=1000
 867 system=system
 868 pio=system.iobus.port[23]
 869
 870 [system.realview.smc_fake]
 871 type=AmbaFake
 872 amba_id=0
 873 ignore_access=false
 874 pio_addr=269357056
 875 pio_latency=1000
 876 system=system
 877 pio=system.iobus.port[16]
 878
 879 [system.realview.sp810_fake]
 880 type=AmbaFake
 881 amba_id=0
 882 ignore_access=true
 883 pio_addr=268439552
 884 pio_latency=1000
 885 system=system
 886 pio=system.iobus.port[17]
 887
 888 [system.realview.ssp_fake]
 889 type=AmbaFake
 890 amba_id=0
 891 ignore_access=false
 892 pio_addr=268488704
 893 pio_latency=1000
 894 system=system
 895 pio=system.iobus.port[22]
 896
 897 [system.realview.timer0]
 898 type=Sp804
 899 amba_id=1316868
 900 clock0=1000000
 901 clock1=1000000
 902 gic=system.realview.gic
 903 int_num0=36
 904 int_num1=36
 905 pio_addr=268505088
 906 pio_latency=1000
 907 system=system
 908 pio=system.iobus.port[3]
 909
 910 [system.realview.timer1]
 911 type=Sp804
 912 amba_id=1316868
 913 clock0=1000000
 914 clock1=1000000
 915 gic=system.realview.gic
 916 int_num0=37
 917 int_num1=37
 918 pio_addr=268509184
 919 pio_latency=1000
 920 system=system
 921 pio=system.iobus.port[4]
 922
 923 [system.realview.uart]
 924 type=Pl011
 925 end_on_eot=false
 926 gic=system.realview.gic
 927 int_delay=100000
 928 int_num=44
 929 pio_addr=268472320
 930 pio_latency=1000
 931 platform=system.realview
 932 system=system
 933 terminal=system.terminal
 934 pio=system.iobus.port[1]
 935
 936 [system.realview.uart1_fake]
 937 type=AmbaFake
 938 amba_id=0
 939 ignore_access=false
 940 pio_addr=268476416
 941 pio_latency=1000
 942 system=system
 943 pio=system.iobus.port[13]
 944
 945 [system.realview.uart2_fake]
 946 type=AmbaFake
 947 amba_id=0
 948 ignore_access=false
 949 pio_addr=268480512
 950 pio_latency=1000
 951 system=system
 952 pio=system.iobus.port[14]
 953
 954 [system.realview.uart3_fake]
 955 type=AmbaFake
 956 amba_id=0
 957 ignore_access=false
 958 pio_addr=268484608
 959 pio_latency=1000
 960 system=system
 961 pio=system.iobus.port[15]
 962
 963 [system.realview.watchdog_fake]
 964 type=AmbaFake
 965 amba_id=0
 966 ignore_access=false
 967 pio_addr=268500992
 968 pio_latency=1000
 969 system=system
 970 pio=system.iobus.port[18]
 971
 972 [system.terminal]
 973 type=Terminal
 974 intr_control=system.intrctrl
 975 number=0
 976 output=true
 977 port=3456
 978
 979 [system.toL2Bus]
 980 type=Bus
 981 block_size=64
 982 bus_id=0
 983 clock=1000
 984 header_cycles=1
 985 use_default_range=false
 986 width=64
 987 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 988
 989 [system.vncserver]
 990 type=VncServer
 991 frame_capture=false
 992 number=0
 993 port=5900
 994