tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 load_addr_mask=268435455
  35 load_offset=0
  36 machine_type=RealView_PBX
  37 mem_mode=timing
  38 mem_ranges=0:134217727
  39 memories=system.physmem system.realview.nvmem
  40 multi_proc=true
  41 num_work_ids=16
  42 panic_on_oops=true
  43 panic_on_panic=true
  44 phys_addr_range_64=40
  45 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
  46 reset_addr_64=0
  47 symbolfile=
  48 work_begin_ckpt_count=0
  49 work_begin_cpu_id_exit=-1
  50 work_begin_exit_count=0
  51 work_cpus_ckpt_count=0
  52 work_end_ckpt_count=0
  53 work_end_exit_count=0
  54 work_item_id=-1
  55 system_port=system.membus.slave[0]
  56
  57 [system.bridge]
  58 type=Bridge
  59 clk_domain=system.clk_domain
  60 delay=50000
  61 eventq_index=0
  62 ranges=268435456:520093695 1073741824:1610612735
  63 req_size=16
  64 resp_size=16
  65 master=system.iobus.slave[0]
  66 slave=system.membus.master[0]
  67
  68 [system.cf0]
  69 type=IdeDisk
  70 children=image
  71 delay=1000000
  72 driveID=master
  73 eventq_index=0
  74 image=system.cf0.image
  75
  76 [system.cf0.image]
  77 type=CowDiskImage
  78 children=child
  79 child=system.cf0.image.child
  80 eventq_index=0
  81 image_file=
  82 read_only=false
  83 table_size=65536
  84
  85 [system.cf0.image.child]
  86 type=RawDiskImage
  87 eventq_index=0
  88 image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
  89 read_only=true
  90
  91 [system.clk_domain]
  92 type=SrcClockDomain
  93 clock=1000
  94 eventq_index=0
  95 voltage_domain=system.voltage_domain
  96
  97 [system.cpu]
  98 type=DerivO3CPU
  99 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 100 LFSTSize=1024
 101 LQEntries=32
 102 LSQCheckLoads=true
 103 LSQDepCheckShift=4
 104 SQEntries=32
 105 SSITSize=1024
 106 activity=0
 107 backComSize=5
 108 branchPred=system.cpu.branchPred
 109 cachePorts=200
 110 checker=Null
 111 clk_domain=system.cpu_clk_domain
 112 commitToDecodeDelay=1
 113 commitToFetchDelay=1
 114 commitToIEWDelay=1
 115 commitToRenameDelay=1
 116 commitWidth=8
 117 cpu_id=0
 118 decodeToFetchDelay=1
 119 decodeToRenameDelay=1
 120 decodeWidth=8
 121 dispatchWidth=8
 122 do_checkpoint_insts=true
 123 do_quiesce=true
 124 do_statistics_insts=true
 125 dstage2_mmu=system.cpu.dstage2_mmu
 126 dtb=system.cpu.dtb
 127 eventq_index=0
 128 fetchBufferSize=64
 129 fetchToDecodeDelay=1
 130 fetchTrapLatency=1
 131 fetchWidth=8
 132 forwardComSize=5
 133 fuPool=system.cpu.fuPool
 134 function_trace=false
 135 function_trace_start=0
 136 iewToCommitDelay=1
 137 iewToDecodeDelay=1
 138 iewToFetchDelay=1
 139 iewToRenameDelay=1
 140 interrupts=system.cpu.interrupts
 141 isa=system.cpu.isa
 142 issueToExecuteDelay=1
 143 issueWidth=8
 144 istage2_mmu=system.cpu.istage2_mmu
 145 itb=system.cpu.itb
 146 max_insts_all_threads=0
 147 max_insts_any_thread=0
 148 max_loads_all_threads=0
 149 max_loads_any_thread=0
 150 needsTSO=false
 151 numIQEntries=64
 152 numPhysCCRegs=0
 153 numPhysFloatRegs=256
 154 numPhysIntRegs=256
 155 numROBEntries=192
 156 numRobs=1
 157 numThreads=1
 158 profile=0
 159 progress_interval=0
 160 renameToDecodeDelay=1
 161 renameToFetchDelay=1
 162 renameToIEWDelay=2
 163 renameToROBDelay=1
 164 renameWidth=8
 165 simpoint_start_insts=
 166 smtCommitPolicy=RoundRobin
 167 smtFetchPolicy=SingleThread
 168 smtIQPolicy=Partitioned
 169 smtIQThreshold=100
 170 smtLSQPolicy=Partitioned
 171 smtLSQThreshold=100
 172 smtNumFetchingThreads=1
 173 smtROBPolicy=Partitioned
 174 smtROBThreshold=100
 175 socket_id=0
 176 squashWidth=8
 177 store_set_clear_period=250000
 178 switched_out=false
 179 system=system
 180 tracer=system.cpu.tracer
 181 trapLatency=13
 182 wbDepth=1
 183 wbWidth=8
 184 workload=
 185 dcache_port=system.cpu.dcache.cpu_side
 186 icache_port=system.cpu.icache.cpu_side
 187
 188 [system.cpu.branchPred]
 189 type=BranchPredictor
 190 BTBEntries=4096
 191 BTBTagSize=16
 192 RASSize=16
 193 choiceCtrBits=2
 194 choicePredictorSize=8192
 195 eventq_index=0
 196 globalCtrBits=2
 197 globalPredictorSize=8192
 198 instShiftAmt=2
 199 localCtrBits=2
 200 localHistoryTableSize=2048
 201 localPredictorSize=2048
 202 numThreads=1
 203 predType=tournament
 204
 205 [system.cpu.dcache]
 206 type=BaseCache
 207 children=tags
 208 addr_ranges=0:18446744073709551615
 209 assoc=4
 210 clk_domain=system.cpu_clk_domain
 211 eventq_index=0
 212 forward_snoops=true
 213 hit_latency=2
 214 is_top_level=true
 215 max_miss_count=0
 216 mshrs=4
 217 prefetch_on_access=false
 218 prefetcher=Null
 219 response_latency=2
 220 sequential_access=false
 221 size=32768
 222 system=system
 223 tags=system.cpu.dcache.tags
 224 tgts_per_mshr=20
 225 two_queue=false
 226 write_buffers=8
 227 cpu_side=system.cpu.dcache_port
 228 mem_side=system.cpu.toL2Bus.slave[1]
 229
 230 [system.cpu.dcache.tags]
 231 type=LRU
 232 assoc=4
 233 block_size=64
 234 clk_domain=system.cpu_clk_domain
 235 eventq_index=0
 236 hit_latency=2
 237 sequential_access=false
 238 size=32768
 239
 240 [system.cpu.dstage2_mmu]
 241 type=ArmStage2MMU
 242 children=stage2_tlb
 243 eventq_index=0
 244 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 245 tlb=system.cpu.dtb
 246
 247 [system.cpu.dstage2_mmu.stage2_tlb]
 248 type=ArmTLB
 249 children=walker
 250 eventq_index=0
 251 is_stage2=true
 252 size=32
 253 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 254
 255 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 256 type=ArmTableWalker
 257 clk_domain=system.cpu_clk_domain
 258 eventq_index=0
 259 is_stage2=true
 260 num_squash_per_cycle=2
 261 sys=system
 262 port=system.cpu.toL2Bus.slave[5]
 263
 264 [system.cpu.dtb]
 265 type=ArmTLB
 266 children=walker
 267 eventq_index=0
 268 is_stage2=false
 269 size=64
 270 walker=system.cpu.dtb.walker
 271
 272 [system.cpu.dtb.walker]
 273 type=ArmTableWalker
 274 clk_domain=system.cpu_clk_domain
 275 eventq_index=0
 276 is_stage2=false
 277 num_squash_per_cycle=2
 278 sys=system
 279 port=system.cpu.toL2Bus.slave[3]
 280
 281 [system.cpu.fuPool]
 282 type=FUPool
 283 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 284 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 285 eventq_index=0
 286
 287 [system.cpu.fuPool.FUList0]
 288 type=FUDesc
 289 children=opList
 290 count=6
 291 eventq_index=0
 292 opList=system.cpu.fuPool.FUList0.opList
 293
 294 [system.cpu.fuPool.FUList0.opList]
 295 type=OpDesc
 296 eventq_index=0
 297 issueLat=1
 298 opClass=IntAlu
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList1]
 302 type=FUDesc
 303 children=opList0 opList1
 304 count=2
 305 eventq_index=0
 306 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 307
 308 [system.cpu.fuPool.FUList1.opList0]
 309 type=OpDesc
 310 eventq_index=0
 311 issueLat=1
 312 opClass=IntMult
 313 opLat=3
 314
 315 [system.cpu.fuPool.FUList1.opList1]
 316 type=OpDesc
 317 eventq_index=0
 318 issueLat=19
 319 opClass=IntDiv
 320 opLat=20
 321
 322 [system.cpu.fuPool.FUList2]
 323 type=FUDesc
 324 children=opList0 opList1 opList2
 325 count=4
 326 eventq_index=0
 327 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 328
 329 [system.cpu.fuPool.FUList2.opList0]
 330 type=OpDesc
 331 eventq_index=0
 332 issueLat=1
 333 opClass=FloatAdd
 334 opLat=2
 335
 336 [system.cpu.fuPool.FUList2.opList1]
 337 type=OpDesc
 338 eventq_index=0
 339 issueLat=1
 340 opClass=FloatCmp
 341 opLat=2
 342
 343 [system.cpu.fuPool.FUList2.opList2]
 344 type=OpDesc
 345 eventq_index=0
 346 issueLat=1
 347 opClass=FloatCvt
 348 opLat=2
 349
 350 [system.cpu.fuPool.FUList3]
 351 type=FUDesc
 352 children=opList0 opList1 opList2
 353 count=2
 354 eventq_index=0
 355 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 356
 357 [system.cpu.fuPool.FUList3.opList0]
 358 type=OpDesc
 359 eventq_index=0
 360 issueLat=1
 361 opClass=FloatMult
 362 opLat=4
 363
 364 [system.cpu.fuPool.FUList3.opList1]
 365 type=OpDesc
 366 eventq_index=0
 367 issueLat=12
 368 opClass=FloatDiv
 369 opLat=12
 370
 371 [system.cpu.fuPool.FUList3.opList2]
 372 type=OpDesc
 373 eventq_index=0
 374 issueLat=24
 375 opClass=FloatSqrt
 376 opLat=24
 377
 378 [system.cpu.fuPool.FUList4]
 379 type=FUDesc
 380 children=opList
 381 count=0
 382 eventq_index=0
 383 opList=system.cpu.fuPool.FUList4.opList
 384
 385 [system.cpu.fuPool.FUList4.opList]
 386 type=OpDesc
 387 eventq_index=0
 388 issueLat=1
 389 opClass=MemRead
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5]
 393 type=FUDesc
 394 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 395 count=4
 396 eventq_index=0
 397 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 398
 399 [system.cpu.fuPool.FUList5.opList00]
 400 type=OpDesc
 401 eventq_index=0
 402 issueLat=1
 403 opClass=SimdAdd
 404 opLat=1
 405
 406 [system.cpu.fuPool.FUList5.opList01]
 407 type=OpDesc
 408 eventq_index=0
 409 issueLat=1
 410 opClass=SimdAddAcc
 411 opLat=1
 412
 413 [system.cpu.fuPool.FUList5.opList02]
 414 type=OpDesc
 415 eventq_index=0
 416 issueLat=1
 417 opClass=SimdAlu
 418 opLat=1
 419
 420 [system.cpu.fuPool.FUList5.opList03]
 421 type=OpDesc
 422 eventq_index=0
 423 issueLat=1
 424 opClass=SimdCmp
 425 opLat=1
 426
 427 [system.cpu.fuPool.FUList5.opList04]
 428 type=OpDesc
 429 eventq_index=0
 430 issueLat=1
 431 opClass=SimdCvt
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList5.opList05]
 435 type=OpDesc
 436 eventq_index=0
 437 issueLat=1
 438 opClass=SimdMisc
 439 opLat=1
 440
 441 [system.cpu.fuPool.FUList5.opList06]
 442 type=OpDesc
 443 eventq_index=0
 444 issueLat=1
 445 opClass=SimdMult
 446 opLat=1
 447
 448 [system.cpu.fuPool.FUList5.opList07]
 449 type=OpDesc
 450 eventq_index=0
 451 issueLat=1
 452 opClass=SimdMultAcc
 453 opLat=1
 454
 455 [system.cpu.fuPool.FUList5.opList08]
 456 type=OpDesc
 457 eventq_index=0
 458 issueLat=1
 459 opClass=SimdShift
 460 opLat=1
 461
 462 [system.cpu.fuPool.FUList5.opList09]
 463 type=OpDesc
 464 eventq_index=0
 465 issueLat=1
 466 opClass=SimdShiftAcc
 467 opLat=1
 468
 469 [system.cpu.fuPool.FUList5.opList10]
 470 type=OpDesc
 471 eventq_index=0
 472 issueLat=1
 473 opClass=SimdSqrt
 474 opLat=1
 475
 476 [system.cpu.fuPool.FUList5.opList11]
 477 type=OpDesc
 478 eventq_index=0
 479 issueLat=1
 480 opClass=SimdFloatAdd
 481 opLat=1
 482
 483 [system.cpu.fuPool.FUList5.opList12]
 484 type=OpDesc
 485 eventq_index=0
 486 issueLat=1
 487 opClass=SimdFloatAlu
 488 opLat=1
 489
 490 [system.cpu.fuPool.FUList5.opList13]
 491 type=OpDesc
 492 eventq_index=0
 493 issueLat=1
 494 opClass=SimdFloatCmp
 495 opLat=1
 496
 497 [system.cpu.fuPool.FUList5.opList14]
 498 type=OpDesc
 499 eventq_index=0
 500 issueLat=1
 501 opClass=SimdFloatCvt
 502 opLat=1
 503
 504 [system.cpu.fuPool.FUList5.opList15]
 505 type=OpDesc
 506 eventq_index=0
 507 issueLat=1
 508 opClass=SimdFloatDiv
 509 opLat=1
 510
 511 [system.cpu.fuPool.FUList5.opList16]
 512 type=OpDesc
 513 eventq_index=0
 514 issueLat=1
 515 opClass=SimdFloatMisc
 516 opLat=1
 517
 518 [system.cpu.fuPool.FUList5.opList17]
 519 type=OpDesc
 520 eventq_index=0
 521 issueLat=1
 522 opClass=SimdFloatMult
 523 opLat=1
 524
 525 [system.cpu.fuPool.FUList5.opList18]
 526 type=OpDesc
 527 eventq_index=0
 528 issueLat=1
 529 opClass=SimdFloatMultAcc
 530 opLat=1
 531
 532 [system.cpu.fuPool.FUList5.opList19]
 533 type=OpDesc
 534 eventq_index=0
 535 issueLat=1
 536 opClass=SimdFloatSqrt
 537 opLat=1
 538
 539 [system.cpu.fuPool.FUList6]
 540 type=FUDesc
 541 children=opList
 542 count=0
 543 eventq_index=0
 544 opList=system.cpu.fuPool.FUList6.opList
 545
 546 [system.cpu.fuPool.FUList6.opList]
 547 type=OpDesc
 548 eventq_index=0
 549 issueLat=1
 550 opClass=MemWrite
 551 opLat=1
 552
 553 [system.cpu.fuPool.FUList7]
 554 type=FUDesc
 555 children=opList0 opList1
 556 count=4
 557 eventq_index=0
 558 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 559
 560 [system.cpu.fuPool.FUList7.opList0]
 561 type=OpDesc
 562 eventq_index=0
 563 issueLat=1
 564 opClass=MemRead
 565 opLat=1
 566
 567 [system.cpu.fuPool.FUList7.opList1]
 568 type=OpDesc
 569 eventq_index=0
 570 issueLat=1
 571 opClass=MemWrite
 572 opLat=1
 573
 574 [system.cpu.fuPool.FUList8]
 575 type=FUDesc
 576 children=opList
 577 count=1
 578 eventq_index=0
 579 opList=system.cpu.fuPool.FUList8.opList
 580
 581 [system.cpu.fuPool.FUList8.opList]
 582 type=OpDesc
 583 eventq_index=0
 584 issueLat=3
 585 opClass=IprAccess
 586 opLat=3
 587
 588 [system.cpu.icache]
 589 type=BaseCache
 590 children=tags
 591 addr_ranges=0:18446744073709551615
 592 assoc=1
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_snoops=true
 596 hit_latency=2
 597 is_top_level=true
 598 max_miss_count=0
 599 mshrs=4
 600 prefetch_on_access=false
 601 prefetcher=Null
 602 response_latency=2
 603 sequential_access=false
 604 size=32768
 605 system=system
 606 tags=system.cpu.icache.tags
 607 tgts_per_mshr=20
 608 two_queue=false
 609 write_buffers=8
 610 cpu_side=system.cpu.icache_port
 611 mem_side=system.cpu.toL2Bus.slave[0]
 612
 613 [system.cpu.icache.tags]
 614 type=LRU
 615 assoc=1
 616 block_size=64
 617 clk_domain=system.cpu_clk_domain
 618 eventq_index=0
 619 hit_latency=2
 620 sequential_access=false
 621 size=32768
 622
 623 [system.cpu.interrupts]
 624 type=ArmInterrupts
 625 eventq_index=0
 626
 627 [system.cpu.isa]
 628 type=ArmISA
 629 eventq_index=0
 630 fpsid=1090793632
 631 id_aa64afr0_el1=0
 632 id_aa64afr1_el1=0
 633 id_aa64dfr0_el1=1052678
 634 id_aa64dfr1_el1=0
 635 id_aa64isar0_el1=0
 636 id_aa64isar1_el1=0
 637 id_aa64mmfr0_el1=15728642
 638 id_aa64mmfr1_el1=0
 639 id_aa64pfr0_el1=17
 640 id_aa64pfr1_el1=0
 641 id_isar0=34607377
 642 id_isar1=34677009
 643 id_isar2=555950401
 644 id_isar3=17899825
 645 id_isar4=268501314
 646 id_isar5=0
 647 id_mmfr0=270536963
 648 id_mmfr1=0
 649 id_mmfr2=19070976
 650 id_mmfr3=34611729
 651 id_pfr0=49
 652 id_pfr1=4113
 653 midr=1091551472
 654 system=system
 655
 656 [system.cpu.istage2_mmu]
 657 type=ArmStage2MMU
 658 children=stage2_tlb
 659 eventq_index=0
 660 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 661 tlb=system.cpu.itb
 662
 663 [system.cpu.istage2_mmu.stage2_tlb]
 664 type=ArmTLB
 665 children=walker
 666 eventq_index=0
 667 is_stage2=true
 668 size=32
 669 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 670
 671 [system.cpu.istage2_mmu.stage2_tlb.walker]
 672 type=ArmTableWalker
 673 clk_domain=system.cpu_clk_domain
 674 eventq_index=0
 675 is_stage2=true
 676 num_squash_per_cycle=2
 677 sys=system
 678 port=system.cpu.toL2Bus.slave[4]
 679
 680 [system.cpu.itb]
 681 type=ArmTLB
 682 children=walker
 683 eventq_index=0
 684 is_stage2=false
 685 size=64
 686 walker=system.cpu.itb.walker
 687
 688 [system.cpu.itb.walker]
 689 type=ArmTableWalker
 690 clk_domain=system.cpu_clk_domain
 691 eventq_index=0
 692 is_stage2=false
 693 num_squash_per_cycle=2
 694 sys=system
 695 port=system.cpu.toL2Bus.slave[2]
 696
 697 [system.cpu.l2cache]
 698 type=BaseCache
 699 children=tags
 700 addr_ranges=0:18446744073709551615
 701 assoc=8
 702 clk_domain=system.cpu_clk_domain
 703 eventq_index=0
 704 forward_snoops=true
 705 hit_latency=20
 706 is_top_level=false
 707 max_miss_count=0
 708 mshrs=20
 709 prefetch_on_access=false
 710 prefetcher=Null
 711 response_latency=20
 712 sequential_access=false
 713 size=4194304
 714 system=system
 715 tags=system.cpu.l2cache.tags
 716 tgts_per_mshr=12
 717 two_queue=false
 718 write_buffers=8
 719 cpu_side=system.cpu.toL2Bus.master[0]
 720 mem_side=system.membus.slave[1]
 721
 722 [system.cpu.l2cache.tags]
 723 type=LRU
 724 assoc=8
 725 block_size=64
 726 clk_domain=system.cpu_clk_domain
 727 eventq_index=0
 728 hit_latency=20
 729 sequential_access=false
 730 size=4194304
 731
 732 [system.cpu.toL2Bus]
 733 type=CoherentBus
 734 clk_domain=system.cpu_clk_domain
 735 eventq_index=0
 736 header_cycles=1
 737 system=system
 738 use_default_range=false
 739 width=32
 740 master=system.cpu.l2cache.cpu_side
 741 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 742
 743 [system.cpu.tracer]
 744 type=ExeTracer
 745 eventq_index=0
 746
 747 [system.cpu_clk_domain]
 748 type=SrcClockDomain
 749 clock=500
 750 eventq_index=0
 751 voltage_domain=system.voltage_domain
 752
 753 [system.intrctrl]
 754 type=IntrControl
 755 eventq_index=0
 756 sys=system
 757
 758 [system.iobus]
 759 type=NoncoherentBus
 760 clk_domain=system.clk_domain
 761 eventq_index=0
 762 header_cycles=1
 763 use_default_range=false
 764 width=8
 765 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 766 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 767
 768 [system.iocache]
 769 type=BaseCache
 770 children=tags
 771 addr_ranges=0:134217727
 772 assoc=8
 773 clk_domain=system.clk_domain
 774 eventq_index=0
 775 forward_snoops=false
 776 hit_latency=50
 777 is_top_level=true
 778 max_miss_count=0
 779 mshrs=20
 780 prefetch_on_access=false
 781 prefetcher=Null
 782 response_latency=50
 783 sequential_access=false
 784 size=1024
 785 system=system
 786 tags=system.iocache.tags
 787 tgts_per_mshr=12
 788 two_queue=false
 789 write_buffers=8
 790 cpu_side=system.iobus.master[25]
 791 mem_side=system.membus.slave[2]
 792
 793 [system.iocache.tags]
 794 type=LRU
 795 assoc=8
 796 block_size=64
 797 clk_domain=system.clk_domain
 798 eventq_index=0
 799 hit_latency=50
 800 sequential_access=false
 801 size=1024
 802
 803 [system.membus]
 804 type=CoherentBus
 805 children=badaddr_responder
 806 clk_domain=system.clk_domain
 807 eventq_index=0
 808 header_cycles=1
 809 system=system
 810 use_default_range=false
 811 width=8
 812 default=system.membus.badaddr_responder.pio
 813 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 814 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 815
 816 [system.membus.badaddr_responder]
 817 type=IsaFake
 818 clk_domain=system.clk_domain
 819 eventq_index=0
 820 fake_mem=false
 821 pio_addr=0
 822 pio_latency=100000
 823 pio_size=8
 824 ret_bad_addr=true
 825 ret_data16=65535
 826 ret_data32=4294967295
 827 ret_data64=18446744073709551615
 828 ret_data8=255
 829 system=system
 830 update_data=false
 831 warn_access=warn
 832 pio=system.membus.default
 833
 834 [system.physmem]
 835 type=DRAMCtrl
 836 activation_limit=4
 837 addr_mapping=RoRaBaChCo
 838 banks_per_rank=8
 839 burst_length=8
 840 channels=1
 841 clk_domain=system.clk_domain
 842 conf_table_reported=true
 843 device_bus_width=8
 844 device_rowbuffer_size=1024
 845 devices_per_rank=8
 846 eventq_index=0
 847 in_addr_map=true
 848 max_accesses_per_row=16
 849 mem_sched_policy=frfcfs
 850 min_writes_per_switch=16
 851 null=false
 852 page_policy=open_adaptive
 853 range=0:134217727
 854 ranks_per_channel=2
 855 read_buffer_size=32
 856 static_backend_latency=10000
 857 static_frontend_latency=10000
 858 tBURST=5000
 859 tCK=1250
 860 tCL=13750
 861 tRAS=35000
 862 tRCD=13750
 863 tREFI=7800000
 864 tRFC=260000
 865 tRP=13750
 866 tRRD=6000
 867 tRTP=7500
 868 tRTW=2500
 869 tWR=15000
 870 tWTR=7500
 871 tXAW=30000
 872 write_buffer_size=64
 873 write_high_thresh_perc=85
 874 write_low_thresh_perc=50
 875 port=system.membus.master[6]
 876
 877 [system.realview]
 878 type=RealView
 879 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 880 eventq_index=0
 881 intrctrl=system.intrctrl
 882 max_mem_size=268435456
 883 mem_start_addr=0
 884 pci_cfg_base=0
 885 system=system
 886
 887 [system.realview.a9scu]
 888 type=A9SCU
 889 clk_domain=system.clk_domain
 890 eventq_index=0
 891 pio_addr=520093696
 892 pio_latency=100000
 893 system=system
 894 pio=system.membus.master[4]
 895
 896 [system.realview.aaci_fake]
 897 type=AmbaFake
 898 amba_id=0
 899 clk_domain=system.clk_domain
 900 eventq_index=0
 901 ignore_access=false
 902 pio_addr=268451840
 903 pio_latency=100000
 904 system=system
 905 pio=system.iobus.master[21]
 906
 907 [system.realview.cf_ctrl]
 908 type=IdeController
 909 BAR0=402653184
 910 BAR0LegacyIO=true
 911 BAR0Size=16
 912 BAR1=402653440
 913 BAR1LegacyIO=true
 914 BAR1Size=1
 915 BAR2=1
 916 BAR2LegacyIO=false
 917 BAR2Size=8
 918 BAR3=1
 919 BAR3LegacyIO=false
 920 BAR3Size=4
 921 BAR4=1
 922 BAR4LegacyIO=false
 923 BAR4Size=16
 924 BAR5=1
 925 BAR5LegacyIO=false
 926 BAR5Size=0
 927 BIST=0
 928 CacheLineSize=0
 929 CapabilityPtr=0
 930 CardbusCIS=0
 931 ClassCode=1
 932 Command=1
 933 DeviceID=28945
 934 ExpansionROM=0
 935 HeaderType=0
 936 InterruptLine=31
 937 InterruptPin=1
 938 LatencyTimer=0
 939 MSICAPBaseOffset=0
 940 MSICAPCapId=0
 941 MSICAPMaskBits=0
 942 MSICAPMsgAddr=0
 943 MSICAPMsgCtrl=0
 944 MSICAPMsgData=0
 945 MSICAPMsgUpperAddr=0
 946 MSICAPNextCapability=0
 947 MSICAPPendingBits=0
 948 MSIXCAPBaseOffset=0
 949 MSIXCAPCapId=0
 950 MSIXCAPNextCapability=0
 951 MSIXMsgCtrl=0
 952 MSIXPbaOffset=0
 953 MSIXTableOffset=0
 954 MaximumLatency=0
 955 MinimumGrant=0
 956 PMCAPBaseOffset=0
 957 PMCAPCapId=0
 958 PMCAPCapabilities=0
 959 PMCAPCtrlStatus=0
 960 PMCAPNextCapability=0
 961 PXCAPBaseOffset=0
 962 PXCAPCapId=0
 963 PXCAPCapabilities=0
 964 PXCAPDevCap2=0
 965 PXCAPDevCapabilities=0
 966 PXCAPDevCtrl=0
 967 PXCAPDevCtrl2=0
 968 PXCAPDevStatus=0
 969 PXCAPLinkCap=0
 970 PXCAPLinkCtrl=0
 971 PXCAPLinkStatus=0
 972 PXCAPNextCapability=0
 973 ProgIF=133
 974 Revision=0
 975 Status=640
 976 SubClassCode=1
 977 SubsystemID=0
 978 SubsystemVendorID=0
 979 VendorID=32902
 980 clk_domain=system.clk_domain
 981 config_latency=20000
 982 ctrl_offset=2
 983 disks=system.cf0
 984 eventq_index=0
 985 io_shift=1
 986 pci_bus=2
 987 pci_dev=7
 988 pci_func=0
 989 pio_latency=30000
 990 platform=system.realview
 991 system=system
 992 config=system.iobus.master[8]
 993 dma=system.iobus.slave[2]
 994 pio=system.iobus.master[7]
 995
 996 [system.realview.clcd]
 997 type=Pl111
 998 amba_id=1315089
 999 clk_domain=system.clk_domain
1000 enable_capture=true
1001 eventq_index=0
1002 gic=system.realview.gic
1003 int_num=55
1004 pio_addr=268566528
1005 pio_latency=10000
1006 pixel_clock=41667
1007 system=system
1008 vnc=system.vncserver
1009 dma=system.iobus.slave[1]
1010 pio=system.iobus.master[4]
1011
1012 [system.realview.dmac_fake]
1013 type=AmbaFake
1014 amba_id=0
1015 clk_domain=system.clk_domain
1016 eventq_index=0
1017 ignore_access=false
1018 pio_addr=268632064
1019 pio_latency=100000
1020 system=system
1021 pio=system.iobus.master[9]
1022
1023 [system.realview.flash_fake]
1024 type=IsaFake
1025 clk_domain=system.clk_domain
1026 eventq_index=0
1027 fake_mem=true
1028 pio_addr=1073741824
1029 pio_latency=100000
1030 pio_size=536870912
1031 ret_bad_addr=false
1032 ret_data16=65535
1033 ret_data32=4294967295
1034 ret_data64=18446744073709551615
1035 ret_data8=255
1036 system=system
1037 update_data=false
1038 warn_access=
1039 pio=system.iobus.master[24]
1040
1041 [system.realview.gic]
1042 type=Pl390
1043 clk_domain=system.clk_domain
1044 cpu_addr=520093952
1045 cpu_pio_delay=10000
1046 dist_addr=520097792
1047 dist_pio_delay=10000
1048 eventq_index=0
1049 int_latency=10000
1050 it_lines=128
1051 msix_addr=0
1052 platform=system.realview
1053 system=system
1054 pio=system.membus.master[2]
1055
1056 [system.realview.gpio0_fake]
1057 type=AmbaFake
1058 amba_id=0
1059 clk_domain=system.clk_domain
1060 eventq_index=0
1061 ignore_access=false
1062 pio_addr=268513280
1063 pio_latency=100000
1064 system=system
1065 pio=system.iobus.master[16]
1066
1067 [system.realview.gpio1_fake]
1068 type=AmbaFake
1069 amba_id=0
1070 clk_domain=system.clk_domain
1071 eventq_index=0
1072 ignore_access=false
1073 pio_addr=268517376
1074 pio_latency=100000
1075 system=system
1076 pio=system.iobus.master[17]
1077
1078 [system.realview.gpio2_fake]
1079 type=AmbaFake
1080 amba_id=0
1081 clk_domain=system.clk_domain
1082 eventq_index=0
1083 ignore_access=false
1084 pio_addr=268521472
1085 pio_latency=100000
1086 system=system
1087 pio=system.iobus.master[18]
1088
1089 [system.realview.kmi0]
1090 type=Pl050
1091 amba_id=1314896
1092 clk_domain=system.clk_domain
1093 eventq_index=0
1094 gic=system.realview.gic
1095 int_delay=1000000
1096 int_num=52
1097 is_mouse=false
1098 pio_addr=268460032
1099 pio_latency=100000
1100 system=system
1101 vnc=system.vncserver
1102 pio=system.iobus.master[5]
1103
1104 [system.realview.kmi1]
1105 type=Pl050
1106 amba_id=1314896
1107 clk_domain=system.clk_domain
1108 eventq_index=0
1109 gic=system.realview.gic
1110 int_delay=1000000
1111 int_num=53
1112 is_mouse=true
1113 pio_addr=268464128
1114 pio_latency=100000
1115 system=system
1116 vnc=system.vncserver
1117 pio=system.iobus.master[6]
1118
1119 [system.realview.l2x0_fake]
1120 type=IsaFake
1121 clk_domain=system.clk_domain
1122 eventq_index=0
1123 fake_mem=false
1124 pio_addr=520101888
1125 pio_latency=100000
1126 pio_size=4095
1127 ret_bad_addr=false
1128 ret_data16=65535
1129 ret_data32=4294967295
1130 ret_data64=18446744073709551615
1131 ret_data8=255
1132 system=system
1133 update_data=false
1134 warn_access=
1135 pio=system.membus.master[3]
1136
1137 [system.realview.local_cpu_timer]
1138 type=CpuLocalTimer
1139 clk_domain=system.clk_domain
1140 eventq_index=0
1141 gic=system.realview.gic
1142 int_num_timer=29
1143 int_num_watchdog=30
1144 pio_addr=520095232
1145 pio_latency=100000
1146 system=system
1147 pio=system.membus.master[5]
1148
1149 [system.realview.mmc_fake]
1150 type=AmbaFake
1151 amba_id=0
1152 clk_domain=system.clk_domain
1153 eventq_index=0
1154 ignore_access=false
1155 pio_addr=268455936
1156 pio_latency=100000
1157 system=system
1158 pio=system.iobus.master[22]
1159
1160 [system.realview.nvmem]
1161 type=SimpleMemory
1162 bandwidth=73.000000
1163 clk_domain=system.clk_domain
1164 conf_table_reported=false
1165 eventq_index=0
1166 in_addr_map=true
1167 latency=30000
1168 latency_var=0
1169 null=false
1170 range=2147483648:2214592511
1171 port=system.membus.master[1]
1172
1173 [system.realview.realview_io]
1174 type=RealViewCtrl
1175 clk_domain=system.clk_domain
1176 eventq_index=0
1177 idreg=0
1178 pio_addr=268435456
1179 pio_latency=100000
1180 proc_id0=201326592
1181 proc_id1=201327138
1182 system=system
1183 pio=system.iobus.master[1]
1184
1185 [system.realview.rtc]
1186 type=PL031
1187 amba_id=3412017
1188 clk_domain=system.clk_domain
1189 eventq_index=0
1190 gic=system.realview.gic
1191 int_delay=100000
1192 int_num=42
1193 pio_addr=268529664
1194 pio_latency=100000
1195 system=system
1196 time=Thu Jan  1 00:00:00 2009
1197 pio=system.iobus.master[23]
1198
1199 [system.realview.sci_fake]
1200 type=AmbaFake
1201 amba_id=0
1202 clk_domain=system.clk_domain
1203 eventq_index=0
1204 ignore_access=false
1205 pio_addr=268492800
1206 pio_latency=100000
1207 system=system
1208 pio=system.iobus.master[20]
1209
1210 [system.realview.smc_fake]
1211 type=AmbaFake
1212 amba_id=0
1213 clk_domain=system.clk_domain
1214 eventq_index=0
1215 ignore_access=false
1216 pio_addr=269357056
1217 pio_latency=100000
1218 system=system
1219 pio=system.iobus.master[13]
1220
1221 [system.realview.sp810_fake]
1222 type=AmbaFake
1223 amba_id=0
1224 clk_domain=system.clk_domain
1225 eventq_index=0
1226 ignore_access=true
1227 pio_addr=268439552
1228 pio_latency=100000
1229 system=system
1230 pio=system.iobus.master[14]
1231
1232 [system.realview.ssp_fake]
1233 type=AmbaFake
1234 amba_id=0
1235 clk_domain=system.clk_domain
1236 eventq_index=0
1237 ignore_access=false
1238 pio_addr=268488704
1239 pio_latency=100000
1240 system=system
1241 pio=system.iobus.master[19]
1242
1243 [system.realview.timer0]
1244 type=Sp804
1245 amba_id=1316868
1246 clk_domain=system.clk_domain
1247 clock0=1000000
1248 clock1=1000000
1249 eventq_index=0
1250 gic=system.realview.gic
1251 int_num0=36
1252 int_num1=36
1253 pio_addr=268505088
1254 pio_latency=100000
1255 system=system
1256 pio=system.iobus.master[2]
1257
1258 [system.realview.timer1]
1259 type=Sp804
1260 amba_id=1316868
1261 clk_domain=system.clk_domain
1262 clock0=1000000
1263 clock1=1000000
1264 eventq_index=0
1265 gic=system.realview.gic
1266 int_num0=37
1267 int_num1=37
1268 pio_addr=268509184
1269 pio_latency=100000
1270 system=system
1271 pio=system.iobus.master[3]
1272
1273 [system.realview.uart]
1274 type=Pl011
1275 clk_domain=system.clk_domain
1276 end_on_eot=false
1277 eventq_index=0
1278 gic=system.realview.gic
1279 int_delay=100000
1280 int_num=44
1281 pio_addr=268472320
1282 pio_latency=100000
1283 platform=system.realview
1284 system=system
1285 terminal=system.terminal
1286 pio=system.iobus.master[0]
1287
1288 [system.realview.uart1_fake]
1289 type=AmbaFake
1290 amba_id=0
1291 clk_domain=system.clk_domain
1292 eventq_index=0
1293 ignore_access=false
1294 pio_addr=268476416
1295 pio_latency=100000
1296 system=system
1297 pio=system.iobus.master[10]
1298
1299 [system.realview.uart2_fake]
1300 type=AmbaFake
1301 amba_id=0
1302 clk_domain=system.clk_domain
1303 eventq_index=0
1304 ignore_access=false
1305 pio_addr=268480512
1306 pio_latency=100000
1307 system=system
1308 pio=system.iobus.master[11]
1309
1310 [system.realview.uart3_fake]
1311 type=AmbaFake
1312 amba_id=0
1313 clk_domain=system.clk_domain
1314 eventq_index=0
1315 ignore_access=false
1316 pio_addr=268484608
1317 pio_latency=100000
1318 system=system
1319 pio=system.iobus.master[12]
1320
1321 [system.realview.watchdog_fake]
1322 type=AmbaFake
1323 amba_id=0
1324 clk_domain=system.clk_domain
1325 eventq_index=0
1326 ignore_access=false
1327 pio_addr=268500992
1328 pio_latency=100000
1329 system=system
1330 pio=system.iobus.master[15]
1331
1332 [system.terminal]
1333 type=Terminal
1334 eventq_index=0
1335 intr_control=system.intrctrl
1336 number=0
1337 output=true
1338 port=3456
1339
1340 [system.vncserver]
1341 type=VncServer
1342 eventq_index=0
1343 frame_capture=false
1344 number=0
1345 port=5900
1346
1347 [system.voltage_domain]
1348 type=VoltageDomain
1349 eventq_index=0
1350 voltage=1.000000
1351