tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
  12 atags_addr=256
  13 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 clock=1000
  16 dtb_filename=
  17 early_kernel_symbols=false
  18 enable_context_switch_stats_dump=false
  19 flags_addr=268435504
  20 gic_cpu_addr=520093952
  21 init_param=0
  22 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  23 load_addr_mask=268435455
  24 machine_type=RealView_PBX
  25 mem_mode=timing
  26 memories=system.physmem system.realview.nvmem
  27 midr_regval=890224640
  28 multi_proc=true
  29 num_work_ids=16
  30 readfile=tests/halt.sh
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.bridge]
  42 type=Bridge
  43 clock=1000
  44 delay=50000
  45 ranges=268435456:520093695 1073741824:1610612735
  46 req_size=16
  47 resp_size=16
  48 master=system.iobus.slave[0]
  49 slave=system.membus.master[0]
  50
  51 [system.cf0]
  52 type=IdeDisk
  53 children=image
  54 delay=1000000
  55 driveID=master
  56 image=system.cf0.image
  57
  58 [system.cf0.image]
  59 type=CowDiskImage
  60 children=child
  61 child=system.cf0.image.child
  62 image_file=
  63 read_only=false
  64 table_size=65536
  65
  66 [system.cf0.image.child]
  67 type=RawDiskImage
  68 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  69 read_only=true
  70
  71 [system.cpu]
  72 type=DerivO3CPU
  73 children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
  74 BTBEntries=4096
  75 BTBTagSize=16
  76 LFSTSize=1024
  77 LQEntries=32
  78 LSQCheckLoads=true
  79 LSQDepCheckShift=4
  80 RASSize=16
  81 SQEntries=32
  82 SSITSize=1024
  83 activity=0
  84 backComSize=5
  85 cachePorts=200
  86 checker=Null
  87 choiceCtrBits=2
  88 choicePredictorSize=8192
  89 clock=500
  90 commitToDecodeDelay=1
  91 commitToFetchDelay=1
  92 commitToIEWDelay=1
  93 commitToRenameDelay=1
  94 commitWidth=8
  95 cpu_id=0
  96 decodeToFetchDelay=1
  97 decodeToRenameDelay=1
  98 decodeWidth=8
  99 defer_registration=false
 100 dispatchWidth=8
 101 do_checkpoint_insts=true
 102 do_quiesce=true
 103 do_statistics_insts=true
 104 dtb=system.cpu.dtb
 105 fetchToDecodeDelay=1
 106 fetchTrapLatency=1
 107 fetchWidth=8
 108 forwardComSize=5
 109 fuPool=system.cpu.fuPool
 110 function_trace=false
 111 function_trace_start=0
 112 globalCtrBits=2
 113 globalHistoryBits=13
 114 globalPredictorSize=8192
 115 iewToCommitDelay=1
 116 iewToDecodeDelay=1
 117 iewToFetchDelay=1
 118 iewToRenameDelay=1
 119 instShiftAmt=2
 120 interrupts=system.cpu.interrupts
 121 issueToExecuteDelay=1
 122 issueWidth=8
 123 itb=system.cpu.itb
 124 localCtrBits=2
 125 localHistoryBits=11
 126 localHistoryTableSize=2048
 127 localPredictorSize=2048
 128 max_insts_all_threads=0
 129 max_insts_any_thread=0
 130 max_loads_all_threads=0
 131 max_loads_any_thread=0
 132 needsTSO=false
 133 numIQEntries=64
 134 numPhysFloatRegs=256
 135 numPhysIntRegs=256
 136 numROBEntries=192
 137 numRobs=1
 138 numThreads=1
 139 predType=tournament
 140 profile=0
 141 progress_interval=0
 142 renameToDecodeDelay=1
 143 renameToFetchDelay=1
 144 renameToIEWDelay=2
 145 renameToROBDelay=1
 146 renameWidth=8
 147 smtCommitPolicy=RoundRobin
 148 smtFetchPolicy=SingleThread
 149 smtIQPolicy=Partitioned
 150 smtIQThreshold=100
 151 smtLSQPolicy=Partitioned
 152 smtLSQThreshold=100
 153 smtNumFetchingThreads=1
 154 smtROBPolicy=Partitioned
 155 smtROBThreshold=100
 156 squashWidth=8
 157 store_set_clear_period=250000
 158 system=system
 159 tracer=system.cpu.tracer
 160 trapLatency=13
 161 wbDepth=1
 162 wbWidth=8
 163 workload=
 164 dcache_port=system.cpu.dcache.cpu_side
 165 icache_port=system.cpu.icache.cpu_side
 166
 167 [system.cpu.dcache]
 168 type=BaseCache
 169 addr_ranges=0:18446744073709551615
 170 assoc=4
 171 block_size=64
 172 clock=500
 173 forward_snoops=true
 174 hash_delay=1
 175 hit_latency=2
 176 is_top_level=true
 177 max_miss_count=0
 178 mshrs=4
 179 prefetch_on_access=false
 180 prefetcher=Null
 181 prioritizeRequests=false
 182 repl=Null
 183 response_latency=2
 184 size=32768
 185 subblock_size=0
 186 system=system
 187 tgts_per_mshr=20
 188 trace_addr=0
 189 two_queue=false
 190 write_buffers=8
 191 cpu_side=system.cpu.dcache_port
 192 mem_side=system.cpu.toL2Bus.slave[1]
 193
 194 [system.cpu.dtb]
 195 type=ArmTLB
 196 children=walker
 197 size=64
 198 walker=system.cpu.dtb.walker
 199
 200 [system.cpu.dtb.walker]
 201 type=ArmTableWalker
 202 clock=500
 203 num_squash_per_cycle=2
 204 sys=system
 205 port=system.cpu.toL2Bus.slave[3]
 206
 207 [system.cpu.fuPool]
 208 type=FUPool
 209 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 210 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 211
 212 [system.cpu.fuPool.FUList0]
 213 type=FUDesc
 214 children=opList
 215 count=6
 216 opList=system.cpu.fuPool.FUList0.opList
 217
 218 [system.cpu.fuPool.FUList0.opList]
 219 type=OpDesc
 220 issueLat=1
 221 opClass=IntAlu
 222 opLat=1
 223
 224 [system.cpu.fuPool.FUList1]
 225 type=FUDesc
 226 children=opList0 opList1
 227 count=2
 228 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 229
 230 [system.cpu.fuPool.FUList1.opList0]
 231 type=OpDesc
 232 issueLat=1
 233 opClass=IntMult
 234 opLat=3
 235
 236 [system.cpu.fuPool.FUList1.opList1]
 237 type=OpDesc
 238 issueLat=19
 239 opClass=IntDiv
 240 opLat=20
 241
 242 [system.cpu.fuPool.FUList2]
 243 type=FUDesc
 244 children=opList0 opList1 opList2
 245 count=4
 246 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 247
 248 [system.cpu.fuPool.FUList2.opList0]
 249 type=OpDesc
 250 issueLat=1
 251 opClass=FloatAdd
 252 opLat=2
 253
 254 [system.cpu.fuPool.FUList2.opList1]
 255 type=OpDesc
 256 issueLat=1
 257 opClass=FloatCmp
 258 opLat=2
 259
 260 [system.cpu.fuPool.FUList2.opList2]
 261 type=OpDesc
 262 issueLat=1
 263 opClass=FloatCvt
 264 opLat=2
 265
 266 [system.cpu.fuPool.FUList3]
 267 type=FUDesc
 268 children=opList0 opList1 opList2
 269 count=2
 270 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 271
 272 [system.cpu.fuPool.FUList3.opList0]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=FloatMult
 276 opLat=4
 277
 278 [system.cpu.fuPool.FUList3.opList1]
 279 type=OpDesc
 280 issueLat=12
 281 opClass=FloatDiv
 282 opLat=12
 283
 284 [system.cpu.fuPool.FUList3.opList2]
 285 type=OpDesc
 286 issueLat=24
 287 opClass=FloatSqrt
 288 opLat=24
 289
 290 [system.cpu.fuPool.FUList4]
 291 type=FUDesc
 292 children=opList
 293 count=0
 294 opList=system.cpu.fuPool.FUList4.opList
 295
 296 [system.cpu.fuPool.FUList4.opList]
 297 type=OpDesc
 298 issueLat=1
 299 opClass=MemRead
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5]
 303 type=FUDesc
 304 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 305 count=4
 306 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 307
 308 [system.cpu.fuPool.FUList5.opList00]
 309 type=OpDesc
 310 issueLat=1
 311 opClass=SimdAdd
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList01]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=SimdAddAcc
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList02]
 321 type=OpDesc
 322 issueLat=1
 323 opClass=SimdAlu
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList03]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdCmp
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList04]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdCvt
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList05]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdMisc
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList06]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdMult
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList07]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdMultAcc
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList08]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdShift
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList09]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdShiftAcc
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList10]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdSqrt
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList11]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdFloatAdd
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList12]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdFloatAlu
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList13]
 387 type=OpDesc
 388 issueLat=1
 389 opClass=SimdFloatCmp
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList14]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=SimdFloatCvt
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList15]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=SimdFloatDiv
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList16]
 405 type=OpDesc
 406 issueLat=1
 407 opClass=SimdFloatMisc
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList5.opList17]
 411 type=OpDesc
 412 issueLat=1
 413 opClass=SimdFloatMult
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList5.opList18]
 417 type=OpDesc
 418 issueLat=1
 419 opClass=SimdFloatMultAcc
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList19]
 423 type=OpDesc
 424 issueLat=1
 425 opClass=SimdFloatSqrt
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList6]
 429 type=FUDesc
 430 children=opList
 431 count=0
 432 opList=system.cpu.fuPool.FUList6.opList
 433
 434 [system.cpu.fuPool.FUList6.opList]
 435 type=OpDesc
 436 issueLat=1
 437 opClass=MemWrite
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList7]
 441 type=FUDesc
 442 children=opList0 opList1
 443 count=4
 444 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 445
 446 [system.cpu.fuPool.FUList7.opList0]
 447 type=OpDesc
 448 issueLat=1
 449 opClass=MemRead
 450 opLat=1
 451
 452 [system.cpu.fuPool.FUList7.opList1]
 453 type=OpDesc
 454 issueLat=1
 455 opClass=MemWrite
 456 opLat=1
 457
 458 [system.cpu.fuPool.FUList8]
 459 type=FUDesc
 460 children=opList
 461 count=1
 462 opList=system.cpu.fuPool.FUList8.opList
 463
 464 [system.cpu.fuPool.FUList8.opList]
 465 type=OpDesc
 466 issueLat=3
 467 opClass=IprAccess
 468 opLat=3
 469
 470 [system.cpu.icache]
 471 type=BaseCache
 472 addr_ranges=0:18446744073709551615
 473 assoc=1
 474 block_size=64
 475 clock=500
 476 forward_snoops=true
 477 hash_delay=1
 478 hit_latency=2
 479 is_top_level=true
 480 max_miss_count=0
 481 mshrs=4
 482 prefetch_on_access=false
 483 prefetcher=Null
 484 prioritizeRequests=false
 485 repl=Null
 486 response_latency=2
 487 size=32768
 488 subblock_size=0
 489 system=system
 490 tgts_per_mshr=20
 491 trace_addr=0
 492 two_queue=false
 493 write_buffers=8
 494 cpu_side=system.cpu.icache_port
 495 mem_side=system.cpu.toL2Bus.slave[0]
 496
 497 [system.cpu.interrupts]
 498 type=ArmInterrupts
 499
 500 [system.cpu.itb]
 501 type=ArmTLB
 502 children=walker
 503 size=64
 504 walker=system.cpu.itb.walker
 505
 506 [system.cpu.itb.walker]
 507 type=ArmTableWalker
 508 clock=500
 509 num_squash_per_cycle=2
 510 sys=system
 511 port=system.cpu.toL2Bus.slave[2]
 512
 513 [system.cpu.l2cache]
 514 type=BaseCache
 515 addr_ranges=0:18446744073709551615
 516 assoc=8
 517 block_size=64
 518 clock=500
 519 forward_snoops=true
 520 hash_delay=1
 521 hit_latency=20
 522 is_top_level=false
 523 max_miss_count=0
 524 mshrs=20
 525 prefetch_on_access=false
 526 prefetcher=Null
 527 prioritizeRequests=false
 528 repl=Null
 529 response_latency=20
 530 size=4194304
 531 subblock_size=0
 532 system=system
 533 tgts_per_mshr=12
 534 trace_addr=0
 535 two_queue=false
 536 write_buffers=8
 537 cpu_side=system.cpu.toL2Bus.master[0]
 538 mem_side=system.membus.slave[2]
 539
 540 [system.cpu.toL2Bus]
 541 type=CoherentBus
 542 block_size=64
 543 clock=500
 544 header_cycles=1
 545 use_default_range=false
 546 width=32
 547 master=system.cpu.l2cache.cpu_side
 548 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 549
 550 [system.cpu.tracer]
 551 type=ExeTracer
 552
 553 [system.intrctrl]
 554 type=IntrControl
 555 sys=system
 556
 557 [system.iobus]
 558 type=NoncoherentBus
 559 block_size=64
 560 clock=1000
 561 header_cycles=1
 562 use_default_range=false
 563 width=8
 564 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 565 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 566
 567 [system.iocache]
 568 type=BaseCache
 569 addr_ranges=0:268435455
 570 assoc=8
 571 block_size=64
 572 clock=1000
 573 forward_snoops=false
 574 hash_delay=1
 575 hit_latency=50
 576 is_top_level=true
 577 max_miss_count=0
 578 mshrs=20
 579 prefetch_on_access=false
 580 prefetcher=Null
 581 prioritizeRequests=false
 582 repl=Null
 583 response_latency=50
 584 size=1024
 585 subblock_size=0
 586 system=system
 587 tgts_per_mshr=12
 588 trace_addr=0
 589 two_queue=false
 590 write_buffers=8
 591 cpu_side=system.iobus.master[25]
 592 mem_side=system.membus.slave[1]
 593
 594 [system.membus]
 595 type=CoherentBus
 596 children=badaddr_responder
 597 block_size=64
 598 clock=1000
 599 header_cycles=1
 600 use_default_range=false
 601 width=8
 602 default=system.membus.badaddr_responder.pio
 603 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 604 slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
 605
 606 [system.membus.badaddr_responder]
 607 type=IsaFake
 608 clock=1000
 609 fake_mem=false
 610 pio_addr=0
 611 pio_latency=100000
 612 pio_size=8
 613 ret_bad_addr=true
 614 ret_data16=65535
 615 ret_data32=4294967295
 616 ret_data64=18446744073709551615
 617 ret_data8=255
 618 system=system
 619 update_data=false
 620 warn_access=warn
 621 pio=system.membus.default
 622
 623 [system.physmem]
 624 type=SimpleDRAM
 625 addr_mapping=openmap
 626 banks_per_rank=8
 627 clock=1000
 628 conf_table_reported=true
 629 in_addr_map=true
 630 lines_per_rowbuffer=64
 631 mem_sched_policy=fcfs
 632 null=false
 633 page_policy=open
 634 range=0:134217727
 635 ranks_per_channel=2
 636 read_buffer_size=32
 637 tBURST=4000
 638 tCL=14000
 639 tRCD=14000
 640 tREFI=7800000
 641 tRFC=300000
 642 tRP=14000
 643 tWTR=1000
 644 write_buffer_size=32
 645 write_thresh_perc=70
 646 zero=false
 647 port=system.membus.master[2]
 648
 649 [system.realview]
 650 type=RealView
 651 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 652 intrctrl=system.intrctrl
 653 max_mem_size=268435456
 654 mem_start_addr=0
 655 pci_cfg_base=0
 656 system=system
 657
 658 [system.realview.a9scu]
 659 type=A9SCU
 660 clock=1000
 661 pio_addr=520093696
 662 pio_latency=100000
 663 system=system
 664 pio=system.membus.master[5]
 665
 666 [system.realview.aaci_fake]
 667 type=AmbaFake
 668 amba_id=0
 669 clock=1000
 670 ignore_access=false
 671 pio_addr=268451840
 672 pio_latency=100000
 673 system=system
 674 pio=system.iobus.master[21]
 675
 676 [system.realview.cf_ctrl]
 677 type=IdeController
 678 BAR0=402653184
 679 BAR0LegacyIO=true
 680 BAR0Size=16
 681 BAR1=402653440
 682 BAR1LegacyIO=true
 683 BAR1Size=1
 684 BAR2=1
 685 BAR2LegacyIO=false
 686 BAR2Size=8
 687 BAR3=1
 688 BAR3LegacyIO=false
 689 BAR3Size=4
 690 BAR4=1
 691 BAR4LegacyIO=false
 692 BAR4Size=16
 693 BAR5=1
 694 BAR5LegacyIO=false
 695 BAR5Size=0
 696 BIST=0
 697 CacheLineSize=0
 698 CardbusCIS=0
 699 ClassCode=1
 700 Command=1
 701 DeviceID=28945
 702 ExpansionROM=0
 703 HeaderType=0
 704 InterruptLine=31
 705 InterruptPin=1
 706 LatencyTimer=0
 707 MaximumLatency=0
 708 MinimumGrant=0
 709 ProgIF=133
 710 Revision=0
 711 Status=640
 712 SubClassCode=1
 713 SubsystemID=0
 714 SubsystemVendorID=0
 715 VendorID=32902
 716 clock=1000
 717 config_latency=20000
 718 ctrl_offset=2
 719 disks=system.cf0
 720 io_shift=1
 721 pci_bus=2
 722 pci_dev=7
 723 pci_func=0
 724 pio_latency=30000
 725 platform=system.realview
 726 system=system
 727 config=system.iobus.master[8]
 728 dma=system.iobus.slave[2]
 729 pio=system.iobus.master[7]
 730
 731 [system.realview.clcd]
 732 type=Pl111
 733 amba_id=1315089
 734 clock=41667
 735 gic=system.realview.gic
 736 int_num=55
 737 pio_addr=268566528
 738 pio_latency=10000
 739 system=system
 740 vnc=system.vncserver
 741 dma=system.iobus.slave[1]
 742 pio=system.iobus.master[4]
 743
 744 [system.realview.dmac_fake]
 745 type=AmbaFake
 746 amba_id=0
 747 clock=1000
 748 ignore_access=false
 749 pio_addr=268632064
 750 pio_latency=100000
 751 system=system
 752 pio=system.iobus.master[9]
 753
 754 [system.realview.flash_fake]
 755 type=IsaFake
 756 clock=1000
 757 fake_mem=true
 758 pio_addr=1073741824
 759 pio_latency=100000
 760 pio_size=536870912
 761 ret_bad_addr=false
 762 ret_data16=65535
 763 ret_data32=4294967295
 764 ret_data64=18446744073709551615
 765 ret_data8=255
 766 system=system
 767 update_data=false
 768 warn_access=
 769 pio=system.iobus.master[24]
 770
 771 [system.realview.gic]
 772 type=Gic
 773 clock=1000
 774 cpu_addr=520093952
 775 cpu_pio_delay=10000
 776 dist_addr=520097792
 777 dist_pio_delay=10000
 778 int_latency=10000
 779 it_lines=128
 780 platform=system.realview
 781 system=system
 782 pio=system.membus.master[3]
 783
 784 [system.realview.gpio0_fake]
 785 type=AmbaFake
 786 amba_id=0
 787 clock=1000
 788 ignore_access=false
 789 pio_addr=268513280
 790 pio_latency=100000
 791 system=system
 792 pio=system.iobus.master[16]
 793
 794 [system.realview.gpio1_fake]
 795 type=AmbaFake
 796 amba_id=0
 797 clock=1000
 798 ignore_access=false
 799 pio_addr=268517376
 800 pio_latency=100000
 801 system=system
 802 pio=system.iobus.master[17]
 803
 804 [system.realview.gpio2_fake]
 805 type=AmbaFake
 806 amba_id=0
 807 clock=1000
 808 ignore_access=false
 809 pio_addr=268521472
 810 pio_latency=100000
 811 system=system
 812 pio=system.iobus.master[18]
 813
 814 [system.realview.kmi0]
 815 type=Pl050
 816 amba_id=1314896
 817 clock=1000
 818 gic=system.realview.gic
 819 int_delay=1000000
 820 int_num=52
 821 is_mouse=false
 822 pio_addr=268460032
 823 pio_latency=100000
 824 system=system
 825 vnc=system.vncserver
 826 pio=system.iobus.master[5]
 827
 828 [system.realview.kmi1]
 829 type=Pl050
 830 amba_id=1314896
 831 clock=1000
 832 gic=system.realview.gic
 833 int_delay=1000000
 834 int_num=53
 835 is_mouse=true
 836 pio_addr=268464128
 837 pio_latency=100000
 838 system=system
 839 vnc=system.vncserver
 840 pio=system.iobus.master[6]
 841
 842 [system.realview.l2x0_fake]
 843 type=IsaFake
 844 clock=1000
 845 fake_mem=false
 846 pio_addr=520101888
 847 pio_latency=100000
 848 pio_size=4095
 849 ret_bad_addr=false
 850 ret_data16=65535
 851 ret_data32=4294967295
 852 ret_data64=18446744073709551615
 853 ret_data8=255
 854 system=system
 855 update_data=false
 856 warn_access=
 857 pio=system.membus.master[4]
 858
 859 [system.realview.local_cpu_timer]
 860 type=CpuLocalTimer
 861 clock=1000
 862 gic=system.realview.gic
 863 int_num_timer=29
 864 int_num_watchdog=30
 865 pio_addr=520095232
 866 pio_latency=100000
 867 system=system
 868 pio=system.membus.master[6]
 869
 870 [system.realview.mmc_fake]
 871 type=AmbaFake
 872 amba_id=0
 873 clock=1000
 874 ignore_access=false
 875 pio_addr=268455936
 876 pio_latency=100000
 877 system=system
 878 pio=system.iobus.master[22]
 879
 880 [system.realview.nvmem]
 881 type=SimpleMemory
 882 bandwidth=73.000000
 883 clock=1000
 884 conf_table_reported=false
 885 in_addr_map=true
 886 latency=30000
 887 latency_var=0
 888 null=false
 889 range=2147483648:2214592511
 890 zero=true
 891 port=system.membus.master[1]
 892
 893 [system.realview.realview_io]
 894 type=RealViewCtrl
 895 clock=1000
 896 idreg=0
 897 pio_addr=268435456
 898 pio_latency=100000
 899 proc_id0=201326592
 900 proc_id1=201327138
 901 system=system
 902 pio=system.iobus.master[1]
 903
 904 [system.realview.rtc]
 905 type=PL031
 906 amba_id=3412017
 907 clock=1000
 908 gic=system.realview.gic
 909 int_delay=100000
 910 int_num=42
 911 pio_addr=268529664
 912 pio_latency=100000
 913 system=system
 914 time=Thu Jan  1 00:00:00 2009
 915 pio=system.iobus.master[23]
 916
 917 [system.realview.sci_fake]
 918 type=AmbaFake
 919 amba_id=0
 920 clock=1000
 921 ignore_access=false
 922 pio_addr=268492800
 923 pio_latency=100000
 924 system=system
 925 pio=system.iobus.master[20]
 926
 927 [system.realview.smc_fake]
 928 type=AmbaFake
 929 amba_id=0
 930 clock=1000
 931 ignore_access=false
 932 pio_addr=269357056
 933 pio_latency=100000
 934 system=system
 935 pio=system.iobus.master[13]
 936
 937 [system.realview.sp810_fake]
 938 type=AmbaFake
 939 amba_id=0
 940 clock=1000
 941 ignore_access=true
 942 pio_addr=268439552
 943 pio_latency=100000
 944 system=system
 945 pio=system.iobus.master[14]
 946
 947 [system.realview.ssp_fake]
 948 type=AmbaFake
 949 amba_id=0
 950 clock=1000
 951 ignore_access=false
 952 pio_addr=268488704
 953 pio_latency=100000
 954 system=system
 955 pio=system.iobus.master[19]
 956
 957 [system.realview.timer0]
 958 type=Sp804
 959 amba_id=1316868
 960 clock=1000
 961 clock0=1000000
 962 clock1=1000000
 963 gic=system.realview.gic
 964 int_num0=36
 965 int_num1=36
 966 pio_addr=268505088
 967 pio_latency=100000
 968 system=system
 969 pio=system.iobus.master[2]
 970
 971 [system.realview.timer1]
 972 type=Sp804
 973 amba_id=1316868
 974 clock=1000
 975 clock0=1000000
 976 clock1=1000000
 977 gic=system.realview.gic
 978 int_num0=37
 979 int_num1=37
 980 pio_addr=268509184
 981 pio_latency=100000
 982 system=system
 983 pio=system.iobus.master[3]
 984
 985 [system.realview.uart]
 986 type=Pl011
 987 clock=1000
 988 end_on_eot=false
 989 gic=system.realview.gic
 990 int_delay=100000
 991 int_num=44
 992 pio_addr=268472320
 993 pio_latency=100000
 994 platform=system.realview
 995 system=system
 996 terminal=system.terminal
 997 pio=system.iobus.master[0]
 998
 999 [system.realview.uart1_fake]
1000 type=AmbaFake
1001 amba_id=0
1002 clock=1000
1003 ignore_access=false
1004 pio_addr=268476416
1005 pio_latency=100000
1006 system=system
1007 pio=system.iobus.master[10]
1008
1009 [system.realview.uart2_fake]
1010 type=AmbaFake
1011 amba_id=0
1012 clock=1000
1013 ignore_access=false
1014 pio_addr=268480512
1015 pio_latency=100000
1016 system=system
1017 pio=system.iobus.master[11]
1018
1019 [system.realview.uart3_fake]
1020 type=AmbaFake
1021 amba_id=0
1022 clock=1000
1023 ignore_access=false
1024 pio_addr=268484608
1025 pio_latency=100000
1026 system=system
1027 pio=system.iobus.master[12]
1028
1029 [system.realview.watchdog_fake]
1030 type=AmbaFake
1031 amba_id=0
1032 clock=1000
1033 ignore_access=false
1034 pio_addr=268500992
1035 pio_latency=100000
1036 system=system
1037 pio=system.iobus.master[15]
1038
1039 [system.terminal]
1040 type=Terminal
1041 intr_control=system.intrctrl
1042 number=0
1043 output=true
1044 port=3456
1045
1046 [system.vncserver]
1047 type=VncServer
1048 frame_capture=false
1049 number=0
1050 port=5900
1051