tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
  12 atags_addr=256
  13 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 clock=1000
  16 dtb_filename=
  17 early_kernel_symbols=false
  18 enable_context_switch_stats_dump=false
  19 flags_addr=268435504
  20 gic_cpu_addr=520093952
  21 init_param=0
  22 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  23 load_addr_mask=268435455
  24 machine_type=RealView_PBX
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.realview.nvmem system.physmem
  28 multi_proc=true
  29 num_work_ids=16
  30 readfile=tests/halt.sh
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.bridge]
  42 type=Bridge
  43 clock=1000
  44 delay=50000
  45 ranges=268435456:520093695 1073741824:1610612735
  46 req_size=16
  47 resp_size=16
  48 master=system.iobus.slave[0]
  49 slave=system.membus.master[0]
  50
  51 [system.cf0]
  52 type=IdeDisk
  53 children=image
  54 delay=1000000
  55 driveID=master
  56 image=system.cf0.image
  57
  58 [system.cf0.image]
  59 type=CowDiskImage
  60 children=child
  61 child=system.cf0.image.child
  62 image_file=
  63 read_only=false
  64 table_size=65536
  65
  66 [system.cf0.image.child]
  67 type=RawDiskImage
  68 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  69 read_only=true
  70
  71 [system.cpu]
  72 type=DerivO3CPU
  73 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  74 LFSTSize=1024
  75 LQEntries=32
  76 LSQCheckLoads=true
  77 LSQDepCheckShift=4
  78 SQEntries=32
  79 SSITSize=1024
  80 activity=0
  81 backComSize=5
  82 branchPred=system.cpu.branchPred
  83 cachePorts=200
  84 checker=Null
  85 clock=500
  86 commitToDecodeDelay=1
  87 commitToFetchDelay=1
  88 commitToIEWDelay=1
  89 commitToRenameDelay=1
  90 commitWidth=8
  91 cpu_id=0
  92 decodeToFetchDelay=1
  93 decodeToRenameDelay=1
  94 decodeWidth=8
  95 dispatchWidth=8
  96 do_checkpoint_insts=true
  97 do_quiesce=true
  98 do_statistics_insts=true
  99 dtb=system.cpu.dtb
 100 fetchToDecodeDelay=1
 101 fetchTrapLatency=1
 102 fetchWidth=8
 103 forwardComSize=5
 104 fuPool=system.cpu.fuPool
 105 function_trace=false
 106 function_trace_start=0
 107 iewToCommitDelay=1
 108 iewToDecodeDelay=1
 109 iewToFetchDelay=1
 110 iewToRenameDelay=1
 111 interrupts=system.cpu.interrupts
 112 isa=system.cpu.isa
 113 issueToExecuteDelay=1
 114 issueWidth=8
 115 itb=system.cpu.itb
 116 max_insts_all_threads=0
 117 max_insts_any_thread=0
 118 max_loads_all_threads=0
 119 max_loads_any_thread=0
 120 needsTSO=false
 121 numIQEntries=64
 122 numPhysFloatRegs=256
 123 numPhysIntRegs=256
 124 numROBEntries=192
 125 numRobs=1
 126 numThreads=1
 127 profile=0
 128 progress_interval=0
 129 renameToDecodeDelay=1
 130 renameToFetchDelay=1
 131 renameToIEWDelay=2
 132 renameToROBDelay=1
 133 renameWidth=8
 134 smtCommitPolicy=RoundRobin
 135 smtFetchPolicy=SingleThread
 136 smtIQPolicy=Partitioned
 137 smtIQThreshold=100
 138 smtLSQPolicy=Partitioned
 139 smtLSQThreshold=100
 140 smtNumFetchingThreads=1
 141 smtROBPolicy=Partitioned
 142 smtROBThreshold=100
 143 squashWidth=8
 144 store_set_clear_period=250000
 145 switched_out=false
 146 system=system
 147 tracer=system.cpu.tracer
 148 trapLatency=13
 149 wbDepth=1
 150 wbWidth=8
 151 workload=
 152 dcache_port=system.cpu.dcache.cpu_side
 153 icache_port=system.cpu.icache.cpu_side
 154
 155 [system.cpu.branchPred]
 156 type=BranchPredictor
 157 BTBEntries=4096
 158 BTBTagSize=16
 159 RASSize=16
 160 choiceCtrBits=2
 161 choicePredictorSize=8192
 162 globalCtrBits=2
 163 globalHistoryBits=13
 164 globalPredictorSize=8192
 165 instShiftAmt=2
 166 localCtrBits=2
 167 localHistoryBits=11
 168 localHistoryTableSize=2048
 169 localPredictorSize=2048
 170 numThreads=1
 171 predType=tournament
 172
 173 [system.cpu.dcache]
 174 type=BaseCache
 175 addr_ranges=0:18446744073709551615
 176 assoc=4
 177 block_size=64
 178 clock=500
 179 forward_snoops=true
 180 hit_latency=2
 181 is_top_level=true
 182 max_miss_count=0
 183 mshrs=4
 184 prefetch_on_access=false
 185 prefetcher=Null
 186 response_latency=2
 187 size=32768
 188 system=system
 189 tgts_per_mshr=20
 190 two_queue=false
 191 write_buffers=8
 192 cpu_side=system.cpu.dcache_port
 193 mem_side=system.cpu.toL2Bus.slave[1]
 194
 195 [system.cpu.dtb]
 196 type=ArmTLB
 197 children=walker
 198 size=64
 199 walker=system.cpu.dtb.walker
 200
 201 [system.cpu.dtb.walker]
 202 type=ArmTableWalker
 203 clock=500
 204 num_squash_per_cycle=2
 205 sys=system
 206 port=system.cpu.toL2Bus.slave[3]
 207
 208 [system.cpu.fuPool]
 209 type=FUPool
 210 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 211 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 212
 213 [system.cpu.fuPool.FUList0]
 214 type=FUDesc
 215 children=opList
 216 count=6
 217 opList=system.cpu.fuPool.FUList0.opList
 218
 219 [system.cpu.fuPool.FUList0.opList]
 220 type=OpDesc
 221 issueLat=1
 222 opClass=IntAlu
 223 opLat=1
 224
 225 [system.cpu.fuPool.FUList1]
 226 type=FUDesc
 227 children=opList0 opList1
 228 count=2
 229 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 230
 231 [system.cpu.fuPool.FUList1.opList0]
 232 type=OpDesc
 233 issueLat=1
 234 opClass=IntMult
 235 opLat=3
 236
 237 [system.cpu.fuPool.FUList1.opList1]
 238 type=OpDesc
 239 issueLat=19
 240 opClass=IntDiv
 241 opLat=20
 242
 243 [system.cpu.fuPool.FUList2]
 244 type=FUDesc
 245 children=opList0 opList1 opList2
 246 count=4
 247 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 248
 249 [system.cpu.fuPool.FUList2.opList0]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=FloatAdd
 253 opLat=2
 254
 255 [system.cpu.fuPool.FUList2.opList1]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=FloatCmp
 259 opLat=2
 260
 261 [system.cpu.fuPool.FUList2.opList2]
 262 type=OpDesc
 263 issueLat=1
 264 opClass=FloatCvt
 265 opLat=2
 266
 267 [system.cpu.fuPool.FUList3]
 268 type=FUDesc
 269 children=opList0 opList1 opList2
 270 count=2
 271 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 272
 273 [system.cpu.fuPool.FUList3.opList0]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=FloatMult
 277 opLat=4
 278
 279 [system.cpu.fuPool.FUList3.opList1]
 280 type=OpDesc
 281 issueLat=12
 282 opClass=FloatDiv
 283 opLat=12
 284
 285 [system.cpu.fuPool.FUList3.opList2]
 286 type=OpDesc
 287 issueLat=24
 288 opClass=FloatSqrt
 289 opLat=24
 290
 291 [system.cpu.fuPool.FUList4]
 292 type=FUDesc
 293 children=opList
 294 count=0
 295 opList=system.cpu.fuPool.FUList4.opList
 296
 297 [system.cpu.fuPool.FUList4.opList]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=MemRead
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5]
 304 type=FUDesc
 305 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 306 count=4
 307 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 308
 309 [system.cpu.fuPool.FUList5.opList00]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdAdd
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList01]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdAddAcc
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList02]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdAlu
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList03]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdCmp
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList04]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdCvt
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList05]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdMisc
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList06]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdMult
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList07]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdMultAcc
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList08]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdShift
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList09]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdShiftAcc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList10]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdSqrt
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList11]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatAdd
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList12]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=SimdFloatAlu
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList13]
 388 type=OpDesc
 389 issueLat=1
 390 opClass=SimdFloatCmp
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList14]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=SimdFloatCvt
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList5.opList15]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=SimdFloatDiv
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList5.opList16]
 406 type=OpDesc
 407 issueLat=1
 408 opClass=SimdFloatMisc
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList17]
 412 type=OpDesc
 413 issueLat=1
 414 opClass=SimdFloatMult
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList5.opList18]
 418 type=OpDesc
 419 issueLat=1
 420 opClass=SimdFloatMultAcc
 421 opLat=1
 422
 423 [system.cpu.fuPool.FUList5.opList19]
 424 type=OpDesc
 425 issueLat=1
 426 opClass=SimdFloatSqrt
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList6]
 430 type=FUDesc
 431 children=opList
 432 count=0
 433 opList=system.cpu.fuPool.FUList6.opList
 434
 435 [system.cpu.fuPool.FUList6.opList]
 436 type=OpDesc
 437 issueLat=1
 438 opClass=MemWrite
 439 opLat=1
 440
 441 [system.cpu.fuPool.FUList7]
 442 type=FUDesc
 443 children=opList0 opList1
 444 count=4
 445 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 446
 447 [system.cpu.fuPool.FUList7.opList0]
 448 type=OpDesc
 449 issueLat=1
 450 opClass=MemRead
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList7.opList1]
 454 type=OpDesc
 455 issueLat=1
 456 opClass=MemWrite
 457 opLat=1
 458
 459 [system.cpu.fuPool.FUList8]
 460 type=FUDesc
 461 children=opList
 462 count=1
 463 opList=system.cpu.fuPool.FUList8.opList
 464
 465 [system.cpu.fuPool.FUList8.opList]
 466 type=OpDesc
 467 issueLat=3
 468 opClass=IprAccess
 469 opLat=3
 470
 471 [system.cpu.icache]
 472 type=BaseCache
 473 addr_ranges=0:18446744073709551615
 474 assoc=1
 475 block_size=64
 476 clock=500
 477 forward_snoops=true
 478 hit_latency=2
 479 is_top_level=true
 480 max_miss_count=0
 481 mshrs=4
 482 prefetch_on_access=false
 483 prefetcher=Null
 484 response_latency=2
 485 size=32768
 486 system=system
 487 tgts_per_mshr=20
 488 two_queue=false
 489 write_buffers=8
 490 cpu_side=system.cpu.icache_port
 491 mem_side=system.cpu.toL2Bus.slave[0]
 492
 493 [system.cpu.interrupts]
 494 type=ArmInterrupts
 495
 496 [system.cpu.isa]
 497 type=ArmISA
 498 fpsid=1090793632
 499 id_isar0=34607377
 500 id_isar1=34677009
 501 id_isar2=555950401
 502 id_isar3=17899825
 503 id_isar4=268501314
 504 id_isar5=0
 505 id_mmfr0=3
 506 id_mmfr1=0
 507 id_mmfr2=19070976
 508 id_mmfr3=4027589137
 509 id_pfr0=49
 510 id_pfr1=1
 511 midr=890224640
 512
 513 [system.cpu.itb]
 514 type=ArmTLB
 515 children=walker
 516 size=64
 517 walker=system.cpu.itb.walker
 518
 519 [system.cpu.itb.walker]
 520 type=ArmTableWalker
 521 clock=500
 522 num_squash_per_cycle=2
 523 sys=system
 524 port=system.cpu.toL2Bus.slave[2]
 525
 526 [system.cpu.l2cache]
 527 type=BaseCache
 528 addr_ranges=0:18446744073709551615
 529 assoc=8
 530 block_size=64
 531 clock=500
 532 forward_snoops=true
 533 hit_latency=20
 534 is_top_level=false
 535 max_miss_count=0
 536 mshrs=20
 537 prefetch_on_access=false
 538 prefetcher=Null
 539 response_latency=20
 540 size=4194304
 541 system=system
 542 tgts_per_mshr=12
 543 two_queue=false
 544 write_buffers=8
 545 cpu_side=system.cpu.toL2Bus.master[0]
 546 mem_side=system.membus.slave[1]
 547
 548 [system.cpu.toL2Bus]
 549 type=CoherentBus
 550 block_size=64
 551 clock=500
 552 header_cycles=1
 553 use_default_range=false
 554 width=32
 555 master=system.cpu.l2cache.cpu_side
 556 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 557
 558 [system.cpu.tracer]
 559 type=ExeTracer
 560
 561 [system.intrctrl]
 562 type=IntrControl
 563 sys=system
 564
 565 [system.iobus]
 566 type=NoncoherentBus
 567 block_size=64
 568 clock=1000
 569 header_cycles=1
 570 use_default_range=false
 571 width=8
 572 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 573 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 574
 575 [system.iocache]
 576 type=BaseCache
 577 addr_ranges=0:134217727
 578 assoc=8
 579 block_size=64
 580 clock=1000
 581 forward_snoops=false
 582 hit_latency=50
 583 is_top_level=true
 584 max_miss_count=0
 585 mshrs=20
 586 prefetch_on_access=false
 587 prefetcher=Null
 588 response_latency=50
 589 size=1024
 590 system=system
 591 tgts_per_mshr=12
 592 two_queue=false
 593 write_buffers=8
 594 cpu_side=system.iobus.master[25]
 595 mem_side=system.membus.slave[2]
 596
 597 [system.membus]
 598 type=CoherentBus
 599 children=badaddr_responder
 600 block_size=64
 601 clock=1000
 602 header_cycles=1
 603 use_default_range=false
 604 width=8
 605 default=system.membus.badaddr_responder.pio
 606 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 607 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 608
 609 [system.membus.badaddr_responder]
 610 type=IsaFake
 611 clock=1000
 612 fake_mem=false
 613 pio_addr=0
 614 pio_latency=100000
 615 pio_size=8
 616 ret_bad_addr=true
 617 ret_data16=65535
 618 ret_data32=4294967295
 619 ret_data64=18446744073709551615
 620 ret_data8=255
 621 system=system
 622 update_data=false
 623 warn_access=warn
 624 pio=system.membus.default
 625
 626 [system.physmem]
 627 type=SimpleDRAM
 628 addr_mapping=openmap
 629 banks_per_rank=8
 630 clock=1000
 631 conf_table_reported=true
 632 in_addr_map=true
 633 lines_per_rowbuffer=64
 634 mem_sched_policy=fcfs
 635 null=false
 636 page_policy=open
 637 range=0:134217727
 638 ranks_per_channel=2
 639 read_buffer_size=32
 640 tBURST=4000
 641 tCL=14000
 642 tRCD=14000
 643 tREFI=7800000
 644 tRFC=300000
 645 tRP=14000
 646 tWTR=1000
 647 write_buffer_size=32
 648 write_thresh_perc=70
 649 zero=false
 650 port=system.membus.master[2]
 651
 652 [system.realview]
 653 type=RealView
 654 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 655 intrctrl=system.intrctrl
 656 max_mem_size=268435456
 657 mem_start_addr=0
 658 pci_cfg_base=0
 659 system=system
 660
 661 [system.realview.a9scu]
 662 type=A9SCU
 663 clock=1000
 664 pio_addr=520093696
 665 pio_latency=100000
 666 system=system
 667 pio=system.membus.master[5]
 668
 669 [system.realview.aaci_fake]
 670 type=AmbaFake
 671 amba_id=0
 672 clock=1000
 673 ignore_access=false
 674 pio_addr=268451840
 675 pio_latency=100000
 676 system=system
 677 pio=system.iobus.master[21]
 678
 679 [system.realview.cf_ctrl]
 680 type=IdeController
 681 BAR0=402653184
 682 BAR0LegacyIO=true
 683 BAR0Size=16
 684 BAR1=402653440
 685 BAR1LegacyIO=true
 686 BAR1Size=1
 687 BAR2=1
 688 BAR2LegacyIO=false
 689 BAR2Size=8
 690 BAR3=1
 691 BAR3LegacyIO=false
 692 BAR3Size=4
 693 BAR4=1
 694 BAR4LegacyIO=false
 695 BAR4Size=16
 696 BAR5=1
 697 BAR5LegacyIO=false
 698 BAR5Size=0
 699 BIST=0
 700 CacheLineSize=0
 701 CardbusCIS=0
 702 ClassCode=1
 703 Command=1
 704 DeviceID=28945
 705 ExpansionROM=0
 706 HeaderType=0
 707 InterruptLine=31
 708 InterruptPin=1
 709 LatencyTimer=0
 710 MaximumLatency=0
 711 MinimumGrant=0
 712 ProgIF=133
 713 Revision=0
 714 Status=640
 715 SubClassCode=1
 716 SubsystemID=0
 717 SubsystemVendorID=0
 718 VendorID=32902
 719 clock=1000
 720 config_latency=20000
 721 ctrl_offset=2
 722 disks=system.cf0
 723 io_shift=1
 724 pci_bus=2
 725 pci_dev=7
 726 pci_func=0
 727 pio_latency=30000
 728 platform=system.realview
 729 system=system
 730 config=system.iobus.master[8]
 731 dma=system.iobus.slave[2]
 732 pio=system.iobus.master[7]
 733
 734 [system.realview.clcd]
 735 type=Pl111
 736 amba_id=1315089
 737 clock=1000
 738 gic=system.realview.gic
 739 int_num=55
 740 pio_addr=268566528
 741 pio_latency=10000
 742 pixel_clock=41667
 743 system=system
 744 vnc=system.vncserver
 745 dma=system.iobus.slave[1]
 746 pio=system.iobus.master[4]
 747
 748 [system.realview.dmac_fake]
 749 type=AmbaFake
 750 amba_id=0
 751 clock=1000
 752 ignore_access=false
 753 pio_addr=268632064
 754 pio_latency=100000
 755 system=system
 756 pio=system.iobus.master[9]
 757
 758 [system.realview.flash_fake]
 759 type=IsaFake
 760 clock=1000
 761 fake_mem=true
 762 pio_addr=1073741824
 763 pio_latency=100000
 764 pio_size=536870912
 765 ret_bad_addr=false
 766 ret_data16=65535
 767 ret_data32=4294967295
 768 ret_data64=18446744073709551615
 769 ret_data8=255
 770 system=system
 771 update_data=false
 772 warn_access=
 773 pio=system.iobus.master[24]
 774
 775 [system.realview.gic]
 776 type=Gic
 777 clock=1000
 778 cpu_addr=520093952
 779 cpu_pio_delay=10000
 780 dist_addr=520097792
 781 dist_pio_delay=10000
 782 int_latency=10000
 783 it_lines=128
 784 platform=system.realview
 785 system=system
 786 pio=system.membus.master[3]
 787
 788 [system.realview.gpio0_fake]
 789 type=AmbaFake
 790 amba_id=0
 791 clock=1000
 792 ignore_access=false
 793 pio_addr=268513280
 794 pio_latency=100000
 795 system=system
 796 pio=system.iobus.master[16]
 797
 798 [system.realview.gpio1_fake]
 799 type=AmbaFake
 800 amba_id=0
 801 clock=1000
 802 ignore_access=false
 803 pio_addr=268517376
 804 pio_latency=100000
 805 system=system
 806 pio=system.iobus.master[17]
 807
 808 [system.realview.gpio2_fake]
 809 type=AmbaFake
 810 amba_id=0
 811 clock=1000
 812 ignore_access=false
 813 pio_addr=268521472
 814 pio_latency=100000
 815 system=system
 816 pio=system.iobus.master[18]
 817
 818 [system.realview.kmi0]
 819 type=Pl050
 820 amba_id=1314896
 821 clock=1000
 822 gic=system.realview.gic
 823 int_delay=1000000
 824 int_num=52
 825 is_mouse=false
 826 pio_addr=268460032
 827 pio_latency=100000
 828 system=system
 829 vnc=system.vncserver
 830 pio=system.iobus.master[5]
 831
 832 [system.realview.kmi1]
 833 type=Pl050
 834 amba_id=1314896
 835 clock=1000
 836 gic=system.realview.gic
 837 int_delay=1000000
 838 int_num=53
 839 is_mouse=true
 840 pio_addr=268464128
 841 pio_latency=100000
 842 system=system
 843 vnc=system.vncserver
 844 pio=system.iobus.master[6]
 845
 846 [system.realview.l2x0_fake]
 847 type=IsaFake
 848 clock=1000
 849 fake_mem=false
 850 pio_addr=520101888
 851 pio_latency=100000
 852 pio_size=4095
 853 ret_bad_addr=false
 854 ret_data16=65535
 855 ret_data32=4294967295
 856 ret_data64=18446744073709551615
 857 ret_data8=255
 858 system=system
 859 update_data=false
 860 warn_access=
 861 pio=system.membus.master[4]
 862
 863 [system.realview.local_cpu_timer]
 864 type=CpuLocalTimer
 865 clock=1000
 866 gic=system.realview.gic
 867 int_num_timer=29
 868 int_num_watchdog=30
 869 pio_addr=520095232
 870 pio_latency=100000
 871 system=system
 872 pio=system.membus.master[6]
 873
 874 [system.realview.mmc_fake]
 875 type=AmbaFake
 876 amba_id=0
 877 clock=1000
 878 ignore_access=false
 879 pio_addr=268455936
 880 pio_latency=100000
 881 system=system
 882 pio=system.iobus.master[22]
 883
 884 [system.realview.nvmem]
 885 type=SimpleMemory
 886 bandwidth=73.000000
 887 clock=1000
 888 conf_table_reported=false
 889 in_addr_map=true
 890 latency=30000
 891 latency_var=0
 892 null=false
 893 range=2147483648:2214592511
 894 zero=true
 895 port=system.membus.master[1]
 896
 897 [system.realview.realview_io]
 898 type=RealViewCtrl
 899 clock=1000
 900 idreg=0
 901 pio_addr=268435456
 902 pio_latency=100000
 903 proc_id0=201326592
 904 proc_id1=201327138
 905 system=system
 906 pio=system.iobus.master[1]
 907
 908 [system.realview.rtc]
 909 type=PL031
 910 amba_id=3412017
 911 clock=1000
 912 gic=system.realview.gic
 913 int_delay=100000
 914 int_num=42
 915 pio_addr=268529664
 916 pio_latency=100000
 917 system=system
 918 time=Thu Jan  1 00:00:00 2009
 919 pio=system.iobus.master[23]
 920
 921 [system.realview.sci_fake]
 922 type=AmbaFake
 923 amba_id=0
 924 clock=1000
 925 ignore_access=false
 926 pio_addr=268492800
 927 pio_latency=100000
 928 system=system
 929 pio=system.iobus.master[20]
 930
 931 [system.realview.smc_fake]
 932 type=AmbaFake
 933 amba_id=0
 934 clock=1000
 935 ignore_access=false
 936 pio_addr=269357056
 937 pio_latency=100000
 938 system=system
 939 pio=system.iobus.master[13]
 940
 941 [system.realview.sp810_fake]
 942 type=AmbaFake
 943 amba_id=0
 944 clock=1000
 945 ignore_access=true
 946 pio_addr=268439552
 947 pio_latency=100000
 948 system=system
 949 pio=system.iobus.master[14]
 950
 951 [system.realview.ssp_fake]
 952 type=AmbaFake
 953 amba_id=0
 954 clock=1000
 955 ignore_access=false
 956 pio_addr=268488704
 957 pio_latency=100000
 958 system=system
 959 pio=system.iobus.master[19]
 960
 961 [system.realview.timer0]
 962 type=Sp804
 963 amba_id=1316868
 964 clock=1000
 965 clock0=1000000
 966 clock1=1000000
 967 gic=system.realview.gic
 968 int_num0=36
 969 int_num1=36
 970 pio_addr=268505088
 971 pio_latency=100000
 972 system=system
 973 pio=system.iobus.master[2]
 974
 975 [system.realview.timer1]
 976 type=Sp804
 977 amba_id=1316868
 978 clock=1000
 979 clock0=1000000
 980 clock1=1000000
 981 gic=system.realview.gic
 982 int_num0=37
 983 int_num1=37
 984 pio_addr=268509184
 985 pio_latency=100000
 986 system=system
 987 pio=system.iobus.master[3]
 988
 989 [system.realview.uart]
 990 type=Pl011
 991 clock=1000
 992 end_on_eot=false
 993 gic=system.realview.gic
 994 int_delay=100000
 995 int_num=44
 996 pio_addr=268472320
 997 pio_latency=100000
 998 platform=system.realview
 999 system=system
1000 terminal=system.terminal
1001 pio=system.iobus.master[0]
1002
1003 [system.realview.uart1_fake]
1004 type=AmbaFake
1005 amba_id=0
1006 clock=1000
1007 ignore_access=false
1008 pio_addr=268476416
1009 pio_latency=100000
1010 system=system
1011 pio=system.iobus.master[10]
1012
1013 [system.realview.uart2_fake]
1014 type=AmbaFake
1015 amba_id=0
1016 clock=1000
1017 ignore_access=false
1018 pio_addr=268480512
1019 pio_latency=100000
1020 system=system
1021 pio=system.iobus.master[11]
1022
1023 [system.realview.uart3_fake]
1024 type=AmbaFake
1025 amba_id=0
1026 clock=1000
1027 ignore_access=false
1028 pio_addr=268484608
1029 pio_latency=100000
1030 system=system
1031 pio=system.iobus.master[12]
1032
1033 [system.realview.watchdog_fake]
1034 type=AmbaFake
1035 amba_id=0
1036 clock=1000
1037 ignore_access=false
1038 pio_addr=268500992
1039 pio_latency=100000
1040 system=system
1041 pio=system.iobus.master[15]
1042
1043 [system.terminal]
1044 type=Terminal
1045 intr_control=system.intrctrl
1046 number=0
1047 output=true
1048 port=3456
1049
1050 [system.vncserver]
1051 type=VncServer
1052 frame_capture=false
1053 number=0
1054 port=5900
1055