tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
  12 atags_addr=256
  13 boot_loader=/gem5/dist/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 clock=1000
  16 dtb_filename=
  17 early_kernel_symbols=false
  18 enable_context_switch_stats_dump=false
  19 flags_addr=268435504
  20 gic_cpu_addr=520093952
  21 init_param=0
  22 kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
  23 load_addr_mask=268435455
  24 machine_type=RealView_PBX
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.physmem system.realview.nvmem
  28 multi_proc=true
  29 num_work_ids=16
  30 readfile=tests/halt.sh
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.bridge]
  42 type=Bridge
  43 clock=1000
  44 delay=50000
  45 ranges=268435456:520093695 1073741824:1610612735
  46 req_size=16
  47 resp_size=16
  48 master=system.iobus.slave[0]
  49 slave=system.membus.master[0]
  50
  51 [system.cf0]
  52 type=IdeDisk
  53 children=image
  54 delay=1000000
  55 driveID=master
  56 image=system.cf0.image
  57
  58 [system.cf0.image]
  59 type=CowDiskImage
  60 children=child
  61 child=system.cf0.image.child
  62 image_file=
  63 read_only=false
  64 table_size=65536
  65
  66 [system.cf0.image.child]
  67 type=RawDiskImage
  68 image_file=/gem5/dist/disks/linux-arm-ael.img
  69 read_only=true
  70
  71 [system.cpu]
  72 type=DerivO3CPU
  73 children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  74 BTBEntries=4096
  75 BTBTagSize=16
  76 LFSTSize=1024
  77 LQEntries=32
  78 LSQCheckLoads=true
  79 LSQDepCheckShift=4
  80 RASSize=16
  81 SQEntries=32
  82 SSITSize=1024
  83 activity=0
  84 backComSize=5
  85 cachePorts=200
  86 checker=Null
  87 choiceCtrBits=2
  88 choicePredictorSize=8192
  89 clock=500
  90 commitToDecodeDelay=1
  91 commitToFetchDelay=1
  92 commitToIEWDelay=1
  93 commitToRenameDelay=1
  94 commitWidth=8
  95 cpu_id=0
  96 decodeToFetchDelay=1
  97 decodeToRenameDelay=1
  98 decodeWidth=8
  99 dispatchWidth=8
 100 do_checkpoint_insts=true
 101 do_quiesce=true
 102 do_statistics_insts=true
 103 dtb=system.cpu.dtb
 104 fetchToDecodeDelay=1
 105 fetchTrapLatency=1
 106 fetchWidth=8
 107 forwardComSize=5
 108 fuPool=system.cpu.fuPool
 109 function_trace=false
 110 function_trace_start=0
 111 globalCtrBits=2
 112 globalHistoryBits=13
 113 globalPredictorSize=8192
 114 iewToCommitDelay=1
 115 iewToDecodeDelay=1
 116 iewToFetchDelay=1
 117 iewToRenameDelay=1
 118 instShiftAmt=2
 119 interrupts=system.cpu.interrupts
 120 isa=system.cpu.isa
 121 issueToExecuteDelay=1
 122 issueWidth=8
 123 itb=system.cpu.itb
 124 localCtrBits=2
 125 localHistoryBits=11
 126 localHistoryTableSize=2048
 127 localPredictorSize=2048
 128 max_insts_all_threads=0
 129 max_insts_any_thread=0
 130 max_loads_all_threads=0
 131 max_loads_any_thread=0
 132 needsTSO=false
 133 numIQEntries=64
 134 numPhysFloatRegs=256
 135 numPhysIntRegs=256
 136 numROBEntries=192
 137 numRobs=1
 138 numThreads=1
 139 predType=tournament
 140 profile=0
 141 progress_interval=0
 142 renameToDecodeDelay=1
 143 renameToFetchDelay=1
 144 renameToIEWDelay=2
 145 renameToROBDelay=1
 146 renameWidth=8
 147 smtCommitPolicy=RoundRobin
 148 smtFetchPolicy=SingleThread
 149 smtIQPolicy=Partitioned
 150 smtIQThreshold=100
 151 smtLSQPolicy=Partitioned
 152 smtLSQThreshold=100
 153 smtNumFetchingThreads=1
 154 smtROBPolicy=Partitioned
 155 smtROBThreshold=100
 156 squashWidth=8
 157 store_set_clear_period=250000
 158 switched_out=false
 159 system=system
 160 tracer=system.cpu.tracer
 161 trapLatency=13
 162 wbDepth=1
 163 wbWidth=8
 164 workload=
 165 dcache_port=system.cpu.dcache.cpu_side
 166 icache_port=system.cpu.icache.cpu_side
 167
 168 [system.cpu.dcache]
 169 type=BaseCache
 170 addr_ranges=0:18446744073709551615
 171 assoc=4
 172 block_size=64
 173 clock=500
 174 forward_snoops=true
 175 hit_latency=2
 176 is_top_level=true
 177 max_miss_count=0
 178 mshrs=4
 179 prefetch_on_access=false
 180 prefetcher=Null
 181 response_latency=2
 182 size=32768
 183 system=system
 184 tgts_per_mshr=20
 185 two_queue=false
 186 write_buffers=8
 187 cpu_side=system.cpu.dcache_port
 188 mem_side=system.cpu.toL2Bus.slave[1]
 189
 190 [system.cpu.dtb]
 191 type=ArmTLB
 192 children=walker
 193 size=64
 194 walker=system.cpu.dtb.walker
 195
 196 [system.cpu.dtb.walker]
 197 type=ArmTableWalker
 198 clock=500
 199 num_squash_per_cycle=2
 200 sys=system
 201 port=system.cpu.toL2Bus.slave[3]
 202
 203 [system.cpu.fuPool]
 204 type=FUPool
 205 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 206 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 207
 208 [system.cpu.fuPool.FUList0]
 209 type=FUDesc
 210 children=opList
 211 count=6
 212 opList=system.cpu.fuPool.FUList0.opList
 213
 214 [system.cpu.fuPool.FUList0.opList]
 215 type=OpDesc
 216 issueLat=1
 217 opClass=IntAlu
 218 opLat=1
 219
 220 [system.cpu.fuPool.FUList1]
 221 type=FUDesc
 222 children=opList0 opList1
 223 count=2
 224 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 225
 226 [system.cpu.fuPool.FUList1.opList0]
 227 type=OpDesc
 228 issueLat=1
 229 opClass=IntMult
 230 opLat=3
 231
 232 [system.cpu.fuPool.FUList1.opList1]
 233 type=OpDesc
 234 issueLat=19
 235 opClass=IntDiv
 236 opLat=20
 237
 238 [system.cpu.fuPool.FUList2]
 239 type=FUDesc
 240 children=opList0 opList1 opList2
 241 count=4
 242 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 243
 244 [system.cpu.fuPool.FUList2.opList0]
 245 type=OpDesc
 246 issueLat=1
 247 opClass=FloatAdd
 248 opLat=2
 249
 250 [system.cpu.fuPool.FUList2.opList1]
 251 type=OpDesc
 252 issueLat=1
 253 opClass=FloatCmp
 254 opLat=2
 255
 256 [system.cpu.fuPool.FUList2.opList2]
 257 type=OpDesc
 258 issueLat=1
 259 opClass=FloatCvt
 260 opLat=2
 261
 262 [system.cpu.fuPool.FUList3]
 263 type=FUDesc
 264 children=opList0 opList1 opList2
 265 count=2
 266 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 267
 268 [system.cpu.fuPool.FUList3.opList0]
 269 type=OpDesc
 270 issueLat=1
 271 opClass=FloatMult
 272 opLat=4
 273
 274 [system.cpu.fuPool.FUList3.opList1]
 275 type=OpDesc
 276 issueLat=12
 277 opClass=FloatDiv
 278 opLat=12
 279
 280 [system.cpu.fuPool.FUList3.opList2]
 281 type=OpDesc
 282 issueLat=24
 283 opClass=FloatSqrt
 284 opLat=24
 285
 286 [system.cpu.fuPool.FUList4]
 287 type=FUDesc
 288 children=opList
 289 count=0
 290 opList=system.cpu.fuPool.FUList4.opList
 291
 292 [system.cpu.fuPool.FUList4.opList]
 293 type=OpDesc
 294 issueLat=1
 295 opClass=MemRead
 296 opLat=1
 297
 298 [system.cpu.fuPool.FUList5]
 299 type=FUDesc
 300 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 301 count=4
 302 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 303
 304 [system.cpu.fuPool.FUList5.opList00]
 305 type=OpDesc
 306 issueLat=1
 307 opClass=SimdAdd
 308 opLat=1
 309
 310 [system.cpu.fuPool.FUList5.opList01]
 311 type=OpDesc
 312 issueLat=1
 313 opClass=SimdAddAcc
 314 opLat=1
 315
 316 [system.cpu.fuPool.FUList5.opList02]
 317 type=OpDesc
 318 issueLat=1
 319 opClass=SimdAlu
 320 opLat=1
 321
 322 [system.cpu.fuPool.FUList5.opList03]
 323 type=OpDesc
 324 issueLat=1
 325 opClass=SimdCmp
 326 opLat=1
 327
 328 [system.cpu.fuPool.FUList5.opList04]
 329 type=OpDesc
 330 issueLat=1
 331 opClass=SimdCvt
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList05]
 335 type=OpDesc
 336 issueLat=1
 337 opClass=SimdMisc
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList06]
 341 type=OpDesc
 342 issueLat=1
 343 opClass=SimdMult
 344 opLat=1
 345
 346 [system.cpu.fuPool.FUList5.opList07]
 347 type=OpDesc
 348 issueLat=1
 349 opClass=SimdMultAcc
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList08]
 353 type=OpDesc
 354 issueLat=1
 355 opClass=SimdShift
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList09]
 359 type=OpDesc
 360 issueLat=1
 361 opClass=SimdShiftAcc
 362 opLat=1
 363
 364 [system.cpu.fuPool.FUList5.opList10]
 365 type=OpDesc
 366 issueLat=1
 367 opClass=SimdSqrt
 368 opLat=1
 369
 370 [system.cpu.fuPool.FUList5.opList11]
 371 type=OpDesc
 372 issueLat=1
 373 opClass=SimdFloatAdd
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList5.opList12]
 377 type=OpDesc
 378 issueLat=1
 379 opClass=SimdFloatAlu
 380 opLat=1
 381
 382 [system.cpu.fuPool.FUList5.opList13]
 383 type=OpDesc
 384 issueLat=1
 385 opClass=SimdFloatCmp
 386 opLat=1
 387
 388 [system.cpu.fuPool.FUList5.opList14]
 389 type=OpDesc
 390 issueLat=1
 391 opClass=SimdFloatCvt
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList5.opList15]
 395 type=OpDesc
 396 issueLat=1
 397 opClass=SimdFloatDiv
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList5.opList16]
 401 type=OpDesc
 402 issueLat=1
 403 opClass=SimdFloatMisc
 404 opLat=1
 405
 406 [system.cpu.fuPool.FUList5.opList17]
 407 type=OpDesc
 408 issueLat=1
 409 opClass=SimdFloatMult
 410 opLat=1
 411
 412 [system.cpu.fuPool.FUList5.opList18]
 413 type=OpDesc
 414 issueLat=1
 415 opClass=SimdFloatMultAcc
 416 opLat=1
 417
 418 [system.cpu.fuPool.FUList5.opList19]
 419 type=OpDesc
 420 issueLat=1
 421 opClass=SimdFloatSqrt
 422 opLat=1
 423
 424 [system.cpu.fuPool.FUList6]
 425 type=FUDesc
 426 children=opList
 427 count=0
 428 opList=system.cpu.fuPool.FUList6.opList
 429
 430 [system.cpu.fuPool.FUList6.opList]
 431 type=OpDesc
 432 issueLat=1
 433 opClass=MemWrite
 434 opLat=1
 435
 436 [system.cpu.fuPool.FUList7]
 437 type=FUDesc
 438 children=opList0 opList1
 439 count=4
 440 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 441
 442 [system.cpu.fuPool.FUList7.opList0]
 443 type=OpDesc
 444 issueLat=1
 445 opClass=MemRead
 446 opLat=1
 447
 448 [system.cpu.fuPool.FUList7.opList1]
 449 type=OpDesc
 450 issueLat=1
 451 opClass=MemWrite
 452 opLat=1
 453
 454 [system.cpu.fuPool.FUList8]
 455 type=FUDesc
 456 children=opList
 457 count=1
 458 opList=system.cpu.fuPool.FUList8.opList
 459
 460 [system.cpu.fuPool.FUList8.opList]
 461 type=OpDesc
 462 issueLat=3
 463 opClass=IprAccess
 464 opLat=3
 465
 466 [system.cpu.icache]
 467 type=BaseCache
 468 addr_ranges=0:18446744073709551615
 469 assoc=1
 470 block_size=64
 471 clock=500
 472 forward_snoops=true
 473 hit_latency=2
 474 is_top_level=true
 475 max_miss_count=0
 476 mshrs=4
 477 prefetch_on_access=false
 478 prefetcher=Null
 479 response_latency=2
 480 size=32768
 481 system=system
 482 tgts_per_mshr=20
 483 two_queue=false
 484 write_buffers=8
 485 cpu_side=system.cpu.icache_port
 486 mem_side=system.cpu.toL2Bus.slave[0]
 487
 488 [system.cpu.interrupts]
 489 type=ArmInterrupts
 490
 491 [system.cpu.isa]
 492 type=ArmISA
 493 fpsid=1090793632
 494 id_isar0=34607377
 495 id_isar1=34677009
 496 id_isar2=555950401
 497 id_isar3=17899825
 498 id_isar4=268501314
 499 id_isar5=0
 500 id_mmfr0=3
 501 id_mmfr1=0
 502 id_mmfr2=19070976
 503 id_mmfr3=4027589137
 504 id_pfr0=49
 505 id_pfr1=1
 506 midr=890224640
 507
 508 [system.cpu.itb]
 509 type=ArmTLB
 510 children=walker
 511 size=64
 512 walker=system.cpu.itb.walker
 513
 514 [system.cpu.itb.walker]
 515 type=ArmTableWalker
 516 clock=500
 517 num_squash_per_cycle=2
 518 sys=system
 519 port=system.cpu.toL2Bus.slave[2]
 520
 521 [system.cpu.l2cache]
 522 type=BaseCache
 523 addr_ranges=0:18446744073709551615
 524 assoc=8
 525 block_size=64
 526 clock=500
 527 forward_snoops=true
 528 hit_latency=20
 529 is_top_level=false
 530 max_miss_count=0
 531 mshrs=20
 532 prefetch_on_access=false
 533 prefetcher=Null
 534 response_latency=20
 535 size=4194304
 536 system=system
 537 tgts_per_mshr=12
 538 two_queue=false
 539 write_buffers=8
 540 cpu_side=system.cpu.toL2Bus.master[0]
 541 mem_side=system.membus.slave[1]
 542
 543 [system.cpu.toL2Bus]
 544 type=CoherentBus
 545 block_size=64
 546 clock=500
 547 header_cycles=1
 548 use_default_range=false
 549 width=32
 550 master=system.cpu.l2cache.cpu_side
 551 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 552
 553 [system.cpu.tracer]
 554 type=ExeTracer
 555
 556 [system.intrctrl]
 557 type=IntrControl
 558 sys=system
 559
 560 [system.iobus]
 561 type=NoncoherentBus
 562 block_size=64
 563 clock=1000
 564 header_cycles=1
 565 use_default_range=false
 566 width=8
 567 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 568 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 569
 570 [system.iocache]
 571 type=BaseCache
 572 addr_ranges=0:134217727
 573 assoc=8
 574 block_size=64
 575 clock=1000
 576 forward_snoops=false
 577 hit_latency=50
 578 is_top_level=true
 579 max_miss_count=0
 580 mshrs=20
 581 prefetch_on_access=false
 582 prefetcher=Null
 583 response_latency=50
 584 size=1024
 585 system=system
 586 tgts_per_mshr=12
 587 two_queue=false
 588 write_buffers=8
 589 cpu_side=system.iobus.master[25]
 590 mem_side=system.membus.slave[2]
 591
 592 [system.membus]
 593 type=CoherentBus
 594 children=badaddr_responder
 595 block_size=64
 596 clock=1000
 597 header_cycles=1
 598 use_default_range=false
 599 width=8
 600 default=system.membus.badaddr_responder.pio
 601 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 602 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 603
 604 [system.membus.badaddr_responder]
 605 type=IsaFake
 606 clock=1000
 607 fake_mem=false
 608 pio_addr=0
 609 pio_latency=100000
 610 pio_size=8
 611 ret_bad_addr=true
 612 ret_data16=65535
 613 ret_data32=4294967295
 614 ret_data64=18446744073709551615
 615 ret_data8=255
 616 system=system
 617 update_data=false
 618 warn_access=warn
 619 pio=system.membus.default
 620
 621 [system.physmem]
 622 type=SimpleDRAM
 623 addr_mapping=openmap
 624 banks_per_rank=8
 625 clock=1000
 626 conf_table_reported=true
 627 in_addr_map=true
 628 lines_per_rowbuffer=64
 629 mem_sched_policy=fcfs
 630 null=false
 631 page_policy=open
 632 range=0:134217727
 633 ranks_per_channel=2
 634 read_buffer_size=32
 635 tBURST=4000
 636 tCL=14000
 637 tRCD=14000
 638 tREFI=7800000
 639 tRFC=300000
 640 tRP=14000
 641 tWTR=1000
 642 write_buffer_size=32
 643 write_thresh_perc=70
 644 zero=false
 645 port=system.membus.master[2]
 646
 647 [system.realview]
 648 type=RealView
 649 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 650 intrctrl=system.intrctrl
 651 max_mem_size=268435456
 652 mem_start_addr=0
 653 pci_cfg_base=0
 654 system=system
 655
 656 [system.realview.a9scu]
 657 type=A9SCU
 658 clock=1000
 659 pio_addr=520093696
 660 pio_latency=100000
 661 system=system
 662 pio=system.membus.master[5]
 663
 664 [system.realview.aaci_fake]
 665 type=AmbaFake
 666 amba_id=0
 667 clock=1000
 668 ignore_access=false
 669 pio_addr=268451840
 670 pio_latency=100000
 671 system=system
 672 pio=system.iobus.master[21]
 673
 674 [system.realview.cf_ctrl]
 675 type=IdeController
 676 BAR0=402653184
 677 BAR0LegacyIO=true
 678 BAR0Size=16
 679 BAR1=402653440
 680 BAR1LegacyIO=true
 681 BAR1Size=1
 682 BAR2=1
 683 BAR2LegacyIO=false
 684 BAR2Size=8
 685 BAR3=1
 686 BAR3LegacyIO=false
 687 BAR3Size=4
 688 BAR4=1
 689 BAR4LegacyIO=false
 690 BAR4Size=16
 691 BAR5=1
 692 BAR5LegacyIO=false
 693 BAR5Size=0
 694 BIST=0
 695 CacheLineSize=0
 696 CardbusCIS=0
 697 ClassCode=1
 698 Command=1
 699 DeviceID=28945
 700 ExpansionROM=0
 701 HeaderType=0
 702 InterruptLine=31
 703 InterruptPin=1
 704 LatencyTimer=0
 705 MaximumLatency=0
 706 MinimumGrant=0
 707 ProgIF=133
 708 Revision=0
 709 Status=640
 710 SubClassCode=1
 711 SubsystemID=0
 712 SubsystemVendorID=0
 713 VendorID=32902
 714 clock=1000
 715 config_latency=20000
 716 ctrl_offset=2
 717 disks=system.cf0
 718 io_shift=1
 719 pci_bus=2
 720 pci_dev=7
 721 pci_func=0
 722 pio_latency=30000
 723 platform=system.realview
 724 system=system
 725 config=system.iobus.master[8]
 726 dma=system.iobus.slave[2]
 727 pio=system.iobus.master[7]
 728
 729 [system.realview.clcd]
 730 type=Pl111
 731 amba_id=1315089
 732 clock=1000
 733 gic=system.realview.gic
 734 int_num=55
 735 pio_addr=268566528
 736 pio_latency=10000
 737 pixel_clock=41667
 738 system=system
 739 vnc=system.vncserver
 740 dma=system.iobus.slave[1]
 741 pio=system.iobus.master[4]
 742
 743 [system.realview.dmac_fake]
 744 type=AmbaFake
 745 amba_id=0
 746 clock=1000
 747 ignore_access=false
 748 pio_addr=268632064
 749 pio_latency=100000
 750 system=system
 751 pio=system.iobus.master[9]
 752
 753 [system.realview.flash_fake]
 754 type=IsaFake
 755 clock=1000
 756 fake_mem=true
 757 pio_addr=1073741824
 758 pio_latency=100000
 759 pio_size=536870912
 760 ret_bad_addr=false
 761 ret_data16=65535
 762 ret_data32=4294967295
 763 ret_data64=18446744073709551615
 764 ret_data8=255
 765 system=system
 766 update_data=false
 767 warn_access=
 768 pio=system.iobus.master[24]
 769
 770 [system.realview.gic]
 771 type=Gic
 772 clock=1000
 773 cpu_addr=520093952
 774 cpu_pio_delay=10000
 775 dist_addr=520097792
 776 dist_pio_delay=10000
 777 int_latency=10000
 778 it_lines=128
 779 platform=system.realview
 780 system=system
 781 pio=system.membus.master[3]
 782
 783 [system.realview.gpio0_fake]
 784 type=AmbaFake
 785 amba_id=0
 786 clock=1000
 787 ignore_access=false
 788 pio_addr=268513280
 789 pio_latency=100000
 790 system=system
 791 pio=system.iobus.master[16]
 792
 793 [system.realview.gpio1_fake]
 794 type=AmbaFake
 795 amba_id=0
 796 clock=1000
 797 ignore_access=false
 798 pio_addr=268517376
 799 pio_latency=100000
 800 system=system
 801 pio=system.iobus.master[17]
 802
 803 [system.realview.gpio2_fake]
 804 type=AmbaFake
 805 amba_id=0
 806 clock=1000
 807 ignore_access=false
 808 pio_addr=268521472
 809 pio_latency=100000
 810 system=system
 811 pio=system.iobus.master[18]
 812
 813 [system.realview.kmi0]
 814 type=Pl050
 815 amba_id=1314896
 816 clock=1000
 817 gic=system.realview.gic
 818 int_delay=1000000
 819 int_num=52
 820 is_mouse=false
 821 pio_addr=268460032
 822 pio_latency=100000
 823 system=system
 824 vnc=system.vncserver
 825 pio=system.iobus.master[5]
 826
 827 [system.realview.kmi1]
 828 type=Pl050
 829 amba_id=1314896
 830 clock=1000
 831 gic=system.realview.gic
 832 int_delay=1000000
 833 int_num=53
 834 is_mouse=true
 835 pio_addr=268464128
 836 pio_latency=100000
 837 system=system
 838 vnc=system.vncserver
 839 pio=system.iobus.master[6]
 840
 841 [system.realview.l2x0_fake]
 842 type=IsaFake
 843 clock=1000
 844 fake_mem=false
 845 pio_addr=520101888
 846 pio_latency=100000
 847 pio_size=4095
 848 ret_bad_addr=false
 849 ret_data16=65535
 850 ret_data32=4294967295
 851 ret_data64=18446744073709551615
 852 ret_data8=255
 853 system=system
 854 update_data=false
 855 warn_access=
 856 pio=system.membus.master[4]
 857
 858 [system.realview.local_cpu_timer]
 859 type=CpuLocalTimer
 860 clock=1000
 861 gic=system.realview.gic
 862 int_num_timer=29
 863 int_num_watchdog=30
 864 pio_addr=520095232
 865 pio_latency=100000
 866 system=system
 867 pio=system.membus.master[6]
 868
 869 [system.realview.mmc_fake]
 870 type=AmbaFake
 871 amba_id=0
 872 clock=1000
 873 ignore_access=false
 874 pio_addr=268455936
 875 pio_latency=100000
 876 system=system
 877 pio=system.iobus.master[22]
 878
 879 [system.realview.nvmem]
 880 type=SimpleMemory
 881 bandwidth=73.000000
 882 clock=1000
 883 conf_table_reported=false
 884 in_addr_map=true
 885 latency=30000
 886 latency_var=0
 887 null=false
 888 range=2147483648:2214592511
 889 zero=true
 890 port=system.membus.master[1]
 891
 892 [system.realview.realview_io]
 893 type=RealViewCtrl
 894 clock=1000
 895 idreg=0
 896 pio_addr=268435456
 897 pio_latency=100000
 898 proc_id0=201326592
 899 proc_id1=201327138
 900 system=system
 901 pio=system.iobus.master[1]
 902
 903 [system.realview.rtc]
 904 type=PL031
 905 amba_id=3412017
 906 clock=1000
 907 gic=system.realview.gic
 908 int_delay=100000
 909 int_num=42
 910 pio_addr=268529664
 911 pio_latency=100000
 912 system=system
 913 time=Thu Jan  1 00:00:00 2009
 914 pio=system.iobus.master[23]
 915
 916 [system.realview.sci_fake]
 917 type=AmbaFake
 918 amba_id=0
 919 clock=1000
 920 ignore_access=false
 921 pio_addr=268492800
 922 pio_latency=100000
 923 system=system
 924 pio=system.iobus.master[20]
 925
 926 [system.realview.smc_fake]
 927 type=AmbaFake
 928 amba_id=0
 929 clock=1000
 930 ignore_access=false
 931 pio_addr=269357056
 932 pio_latency=100000
 933 system=system
 934 pio=system.iobus.master[13]
 935
 936 [system.realview.sp810_fake]
 937 type=AmbaFake
 938 amba_id=0
 939 clock=1000
 940 ignore_access=true
 941 pio_addr=268439552
 942 pio_latency=100000
 943 system=system
 944 pio=system.iobus.master[14]
 945
 946 [system.realview.ssp_fake]
 947 type=AmbaFake
 948 amba_id=0
 949 clock=1000
 950 ignore_access=false
 951 pio_addr=268488704
 952 pio_latency=100000
 953 system=system
 954 pio=system.iobus.master[19]
 955
 956 [system.realview.timer0]
 957 type=Sp804
 958 amba_id=1316868
 959 clock=1000
 960 clock0=1000000
 961 clock1=1000000
 962 gic=system.realview.gic
 963 int_num0=36
 964 int_num1=36
 965 pio_addr=268505088
 966 pio_latency=100000
 967 system=system
 968 pio=system.iobus.master[2]
 969
 970 [system.realview.timer1]
 971 type=Sp804
 972 amba_id=1316868
 973 clock=1000
 974 clock0=1000000
 975 clock1=1000000
 976 gic=system.realview.gic
 977 int_num0=37
 978 int_num1=37
 979 pio_addr=268509184
 980 pio_latency=100000
 981 system=system
 982 pio=system.iobus.master[3]
 983
 984 [system.realview.uart]
 985 type=Pl011
 986 clock=1000
 987 end_on_eot=false
 988 gic=system.realview.gic
 989 int_delay=100000
 990 int_num=44
 991 pio_addr=268472320
 992 pio_latency=100000
 993 platform=system.realview
 994 system=system
 995 terminal=system.terminal
 996 pio=system.iobus.master[0]
 997
 998 [system.realview.uart1_fake]
 999 type=AmbaFake
1000 amba_id=0
1001 clock=1000
1002 ignore_access=false
1003 pio_addr=268476416
1004 pio_latency=100000
1005 system=system
1006 pio=system.iobus.master[10]
1007
1008 [system.realview.uart2_fake]
1009 type=AmbaFake
1010 amba_id=0
1011 clock=1000
1012 ignore_access=false
1013 pio_addr=268480512
1014 pio_latency=100000
1015 system=system
1016 pio=system.iobus.master[11]
1017
1018 [system.realview.uart3_fake]
1019 type=AmbaFake
1020 amba_id=0
1021 clock=1000
1022 ignore_access=false
1023 pio_addr=268484608
1024 pio_latency=100000
1025 system=system
1026 pio=system.iobus.master[12]
1027
1028 [system.realview.watchdog_fake]
1029 type=AmbaFake
1030 amba_id=0
1031 clock=1000
1032 ignore_access=false
1033 pio_addr=268500992
1034 pio_latency=100000
1035 system=system
1036 pio=system.iobus.master[15]
1037
1038 [system.terminal]
1039 type=Terminal
1040 intr_control=system.intrctrl
1041 number=0
1042 output=true
1043 port=3456
1044
1045 [system.vncserver]
1046 type=VncServer
1047 frame_capture=false
1048 number=0
1049 port=5900
1050