tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=DerivO3CPU
 115 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 LFSTSize=1024
 117 LQEntries=16
 118 LSQCheckLoads=true
 119 LSQDepCheckShift=0
 120 SQEntries=16
 121 SSITSize=1024
 122 activity=0
 123 backComSize=5
 124 branchPred=system.cpu.branchPred
 125 cachePorts=200
 126 checker=Null
 127 clk_domain=system.cpu_clk_domain
 128 commitToDecodeDelay=1
 129 commitToFetchDelay=1
 130 commitToIEWDelay=1
 131 commitToRenameDelay=1
 132 commitWidth=8
 133 cpu_id=0
 134 decodeToFetchDelay=1
 135 decodeToRenameDelay=2
 136 decodeWidth=3
 137 default_p_state=UNDEFINED
 138 dispatchWidth=6
 139 do_checkpoint_insts=true
 140 do_quiesce=true
 141 do_statistics_insts=true
 142 dstage2_mmu=system.cpu.dstage2_mmu
 143 dtb=system.cpu.dtb
 144 eventq_index=0
 145 fetchBufferSize=16
 146 fetchQueueSize=32
 147 fetchToDecodeDelay=3
 148 fetchTrapLatency=1
 149 fetchWidth=3
 150 forwardComSize=5
 151 fuPool=system.cpu.fuPool
 152 function_trace=false
 153 function_trace_start=0
 154 iewToCommitDelay=1
 155 iewToDecodeDelay=1
 156 iewToFetchDelay=1
 157 iewToRenameDelay=1
 158 interrupts=system.cpu.interrupts
 159 isa=system.cpu.isa
 160 issueToExecuteDelay=1
 161 issueWidth=8
 162 istage2_mmu=system.cpu.istage2_mmu
 163 itb=system.cpu.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 needsTSO=false
 169 numIQEntries=32
 170 numPhysCCRegs=640
 171 numPhysFloatRegs=192
 172 numPhysIntRegs=128
 173 numROBEntries=40
 174 numRobs=1
 175 numThreads=1
 176 p_state_clk_gate_bins=20
 177 p_state_clk_gate_max=1000000000000
 178 p_state_clk_gate_min=1000
 179 power_model=Null
 180 profile=0
 181 progress_interval=0
 182 renameToDecodeDelay=1
 183 renameToFetchDelay=1
 184 renameToIEWDelay=1
 185 renameToROBDelay=1
 186 renameWidth=3
 187 simpoint_start_insts=
 188 smtCommitPolicy=RoundRobin
 189 smtFetchPolicy=SingleThread
 190 smtIQPolicy=Partitioned
 191 smtIQThreshold=100
 192 smtLSQPolicy=Partitioned
 193 smtLSQThreshold=100
 194 smtNumFetchingThreads=1
 195 smtROBPolicy=Partitioned
 196 smtROBThreshold=100
 197 socket_id=0
 198 squashWidth=8
 199 store_set_clear_period=250000
 200 switched_out=false
 201 system=system
 202 tracer=system.cpu.tracer
 203 trapLatency=13
 204 wbWidth=8
 205 workload=
 206 dcache_port=system.cpu.dcache.cpu_side
 207 icache_port=system.cpu.icache.cpu_side
 208
 209 [system.cpu.branchPred]
 210 type=BiModeBP
 211 BTBEntries=2048
 212 BTBTagSize=18
 213 RASSize=16
 214 choiceCtrBits=2
 215 choicePredictorSize=8192
 216 eventq_index=0
 217 globalCtrBits=2
 218 globalPredictorSize=8192
 219 indirectHashGHR=true
 220 indirectHashTargets=true
 221 indirectPathLength=3
 222 indirectSets=256
 223 indirectTagSize=16
 224 indirectWays=2
 225 instShiftAmt=2
 226 numThreads=1
 227 useIndirect=true
 228
 229 [system.cpu.dcache]
 230 type=Cache
 231 children=tags
 232 addr_ranges=0:18446744073709551615
 233 assoc=4
 234 clk_domain=system.cpu_clk_domain
 235 clusivity=mostly_incl
 236 default_p_state=UNDEFINED
 237 demand_mshr_reserve=1
 238 eventq_index=0
 239 hit_latency=2
 240 is_read_only=false
 241 max_miss_count=0
 242 mshrs=4
 243 p_state_clk_gate_bins=20
 244 p_state_clk_gate_max=1000000000000
 245 p_state_clk_gate_min=1000
 246 power_model=Null
 247 prefetch_on_access=false
 248 prefetcher=Null
 249 response_latency=2
 250 sequential_access=false
 251 size=32768
 252 system=system
 253 tags=system.cpu.dcache.tags
 254 tgts_per_mshr=20
 255 write_buffers=8
 256 writeback_clean=false
 257 cpu_side=system.cpu.dcache_port
 258 mem_side=system.cpu.toL2Bus.slave[1]
 259
 260 [system.cpu.dcache.tags]
 261 type=LRU
 262 assoc=4
 263 block_size=64
 264 clk_domain=system.cpu_clk_domain
 265 default_p_state=UNDEFINED
 266 eventq_index=0
 267 hit_latency=2
 268 p_state_clk_gate_bins=20
 269 p_state_clk_gate_max=1000000000000
 270 p_state_clk_gate_min=1000
 271 power_model=Null
 272 sequential_access=false
 273 size=32768
 274
 275 [system.cpu.dstage2_mmu]
 276 type=ArmStage2MMU
 277 children=stage2_tlb
 278 eventq_index=0
 279 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 280 sys=system
 281 tlb=system.cpu.dtb
 282
 283 [system.cpu.dstage2_mmu.stage2_tlb]
 284 type=ArmTLB
 285 children=walker
 286 eventq_index=0
 287 is_stage2=true
 288 size=32
 289 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 290
 291 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 292 type=ArmTableWalker
 293 clk_domain=system.cpu_clk_domain
 294 default_p_state=UNDEFINED
 295 eventq_index=0
 296 is_stage2=true
 297 num_squash_per_cycle=2
 298 p_state_clk_gate_bins=20
 299 p_state_clk_gate_max=1000000000000
 300 p_state_clk_gate_min=1000
 301 power_model=Null
 302 sys=system
 303
 304 [system.cpu.dtb]
 305 type=ArmTLB
 306 children=walker
 307 eventq_index=0
 308 is_stage2=false
 309 size=64
 310 walker=system.cpu.dtb.walker
 311
 312 [system.cpu.dtb.walker]
 313 type=ArmTableWalker
 314 clk_domain=system.cpu_clk_domain
 315 default_p_state=UNDEFINED
 316 eventq_index=0
 317 is_stage2=false
 318 num_squash_per_cycle=2
 319 p_state_clk_gate_bins=20
 320 p_state_clk_gate_max=1000000000000
 321 p_state_clk_gate_min=1000
 322 power_model=Null
 323 sys=system
 324 port=system.cpu.toL2Bus.slave[3]
 325
 326 [system.cpu.fuPool]
 327 type=FUPool
 328 children=FUList0 FUList1 FUList2 FUList3 FUList4
 329 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 330 eventq_index=0
 331
 332 [system.cpu.fuPool.FUList0]
 333 type=FUDesc
 334 children=opList
 335 count=2
 336 eventq_index=0
 337 opList=system.cpu.fuPool.FUList0.opList
 338
 339 [system.cpu.fuPool.FUList0.opList]
 340 type=OpDesc
 341 eventq_index=0
 342 opClass=IntAlu
 343 opLat=1
 344 pipelined=true
 345
 346 [system.cpu.fuPool.FUList1]
 347 type=FUDesc
 348 children=opList0 opList1 opList2
 349 count=1
 350 eventq_index=0
 351 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 352
 353 [system.cpu.fuPool.FUList1.opList0]
 354 type=OpDesc
 355 eventq_index=0
 356 opClass=IntMult
 357 opLat=3
 358 pipelined=true
 359
 360 [system.cpu.fuPool.FUList1.opList1]
 361 type=OpDesc
 362 eventq_index=0
 363 opClass=IntDiv
 364 opLat=12
 365 pipelined=false
 366
 367 [system.cpu.fuPool.FUList1.opList2]
 368 type=OpDesc
 369 eventq_index=0
 370 opClass=IprAccess
 371 opLat=3
 372 pipelined=true
 373
 374 [system.cpu.fuPool.FUList2]
 375 type=FUDesc
 376 children=opList
 377 count=1
 378 eventq_index=0
 379 opList=system.cpu.fuPool.FUList2.opList
 380
 381 [system.cpu.fuPool.FUList2.opList]
 382 type=OpDesc
 383 eventq_index=0
 384 opClass=MemRead
 385 opLat=2
 386 pipelined=true
 387
 388 [system.cpu.fuPool.FUList3]
 389 type=FUDesc
 390 children=opList
 391 count=1
 392 eventq_index=0
 393 opList=system.cpu.fuPool.FUList3.opList
 394
 395 [system.cpu.fuPool.FUList3.opList]
 396 type=OpDesc
 397 eventq_index=0
 398 opClass=MemWrite
 399 opLat=2
 400 pipelined=true
 401
 402 [system.cpu.fuPool.FUList4]
 403 type=FUDesc
 404 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 405 count=2
 406 eventq_index=0
 407 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 408
 409 [system.cpu.fuPool.FUList4.opList00]
 410 type=OpDesc
 411 eventq_index=0
 412 opClass=SimdAdd
 413 opLat=4
 414 pipelined=true
 415
 416 [system.cpu.fuPool.FUList4.opList01]
 417 type=OpDesc
 418 eventq_index=0
 419 opClass=SimdAddAcc
 420 opLat=4
 421 pipelined=true
 422
 423 [system.cpu.fuPool.FUList4.opList02]
 424 type=OpDesc
 425 eventq_index=0
 426 opClass=SimdAlu
 427 opLat=4
 428 pipelined=true
 429
 430 [system.cpu.fuPool.FUList4.opList03]
 431 type=OpDesc
 432 eventq_index=0
 433 opClass=SimdCmp
 434 opLat=4
 435 pipelined=true
 436
 437 [system.cpu.fuPool.FUList4.opList04]
 438 type=OpDesc
 439 eventq_index=0
 440 opClass=SimdCvt
 441 opLat=3
 442 pipelined=true
 443
 444 [system.cpu.fuPool.FUList4.opList05]
 445 type=OpDesc
 446 eventq_index=0
 447 opClass=SimdMisc
 448 opLat=3
 449 pipelined=true
 450
 451 [system.cpu.fuPool.FUList4.opList06]
 452 type=OpDesc
 453 eventq_index=0
 454 opClass=SimdMult
 455 opLat=5
 456 pipelined=true
 457
 458 [system.cpu.fuPool.FUList4.opList07]
 459 type=OpDesc
 460 eventq_index=0
 461 opClass=SimdMultAcc
 462 opLat=5
 463 pipelined=true
 464
 465 [system.cpu.fuPool.FUList4.opList08]
 466 type=OpDesc
 467 eventq_index=0
 468 opClass=SimdShift
 469 opLat=3
 470 pipelined=true
 471
 472 [system.cpu.fuPool.FUList4.opList09]
 473 type=OpDesc
 474 eventq_index=0
 475 opClass=SimdShiftAcc
 476 opLat=3
 477 pipelined=true
 478
 479 [system.cpu.fuPool.FUList4.opList10]
 480 type=OpDesc
 481 eventq_index=0
 482 opClass=SimdSqrt
 483 opLat=9
 484 pipelined=true
 485
 486 [system.cpu.fuPool.FUList4.opList11]
 487 type=OpDesc
 488 eventq_index=0
 489 opClass=SimdFloatAdd
 490 opLat=5
 491 pipelined=true
 492
 493 [system.cpu.fuPool.FUList4.opList12]
 494 type=OpDesc
 495 eventq_index=0
 496 opClass=SimdFloatAlu
 497 opLat=5
 498 pipelined=true
 499
 500 [system.cpu.fuPool.FUList4.opList13]
 501 type=OpDesc
 502 eventq_index=0
 503 opClass=SimdFloatCmp
 504 opLat=3
 505 pipelined=true
 506
 507 [system.cpu.fuPool.FUList4.opList14]
 508 type=OpDesc
 509 eventq_index=0
 510 opClass=SimdFloatCvt
 511 opLat=3
 512 pipelined=true
 513
 514 [system.cpu.fuPool.FUList4.opList15]
 515 type=OpDesc
 516 eventq_index=0
 517 opClass=SimdFloatDiv
 518 opLat=3
 519 pipelined=true
 520
 521 [system.cpu.fuPool.FUList4.opList16]
 522 type=OpDesc
 523 eventq_index=0
 524 opClass=SimdFloatMisc
 525 opLat=3
 526 pipelined=true
 527
 528 [system.cpu.fuPool.FUList4.opList17]
 529 type=OpDesc
 530 eventq_index=0
 531 opClass=SimdFloatMult
 532 opLat=3
 533 pipelined=true
 534
 535 [system.cpu.fuPool.FUList4.opList18]
 536 type=OpDesc
 537 eventq_index=0
 538 opClass=SimdFloatMultAcc
 539 opLat=1
 540 pipelined=true
 541
 542 [system.cpu.fuPool.FUList4.opList19]
 543 type=OpDesc
 544 eventq_index=0
 545 opClass=SimdFloatSqrt
 546 opLat=9
 547 pipelined=true
 548
 549 [system.cpu.fuPool.FUList4.opList20]
 550 type=OpDesc
 551 eventq_index=0
 552 opClass=FloatAdd
 553 opLat=5
 554 pipelined=true
 555
 556 [system.cpu.fuPool.FUList4.opList21]
 557 type=OpDesc
 558 eventq_index=0
 559 opClass=FloatCmp
 560 opLat=5
 561 pipelined=true
 562
 563 [system.cpu.fuPool.FUList4.opList22]
 564 type=OpDesc
 565 eventq_index=0
 566 opClass=FloatCvt
 567 opLat=5
 568 pipelined=true
 569
 570 [system.cpu.fuPool.FUList4.opList23]
 571 type=OpDesc
 572 eventq_index=0
 573 opClass=FloatDiv
 574 opLat=9
 575 pipelined=false
 576
 577 [system.cpu.fuPool.FUList4.opList24]
 578 type=OpDesc
 579 eventq_index=0
 580 opClass=FloatSqrt
 581 opLat=33
 582 pipelined=false
 583
 584 [system.cpu.fuPool.FUList4.opList25]
 585 type=OpDesc
 586 eventq_index=0
 587 opClass=FloatMult
 588 opLat=4
 589 pipelined=true
 590
 591 [system.cpu.icache]
 592 type=Cache
 593 children=tags
 594 addr_ranges=0:18446744073709551615
 595 assoc=1
 596 clk_domain=system.cpu_clk_domain
 597 clusivity=mostly_incl
 598 default_p_state=UNDEFINED
 599 demand_mshr_reserve=1
 600 eventq_index=0
 601 hit_latency=2
 602 is_read_only=true
 603 max_miss_count=0
 604 mshrs=4
 605 p_state_clk_gate_bins=20
 606 p_state_clk_gate_max=1000000000000
 607 p_state_clk_gate_min=1000
 608 power_model=Null
 609 prefetch_on_access=false
 610 prefetcher=Null
 611 response_latency=2
 612 sequential_access=false
 613 size=32768
 614 system=system
 615 tags=system.cpu.icache.tags
 616 tgts_per_mshr=20
 617 write_buffers=8
 618 writeback_clean=true
 619 cpu_side=system.cpu.icache_port
 620 mem_side=system.cpu.toL2Bus.slave[0]
 621
 622 [system.cpu.icache.tags]
 623 type=LRU
 624 assoc=1
 625 block_size=64
 626 clk_domain=system.cpu_clk_domain
 627 default_p_state=UNDEFINED
 628 eventq_index=0
 629 hit_latency=2
 630 p_state_clk_gate_bins=20
 631 p_state_clk_gate_max=1000000000000
 632 p_state_clk_gate_min=1000
 633 power_model=Null
 634 sequential_access=false
 635 size=32768
 636
 637 [system.cpu.interrupts]
 638 type=ArmInterrupts
 639 eventq_index=0
 640
 641 [system.cpu.isa]
 642 type=ArmISA
 643 decoderFlavour=Generic
 644 eventq_index=0
 645 fpsid=1090793632
 646 id_aa64afr0_el1=0
 647 id_aa64afr1_el1=0
 648 id_aa64dfr0_el1=1052678
 649 id_aa64dfr1_el1=0
 650 id_aa64isar0_el1=0
 651 id_aa64isar1_el1=0
 652 id_aa64mmfr0_el1=15728642
 653 id_aa64mmfr1_el1=0
 654 id_aa64pfr0_el1=34
 655 id_aa64pfr1_el1=0
 656 id_isar0=34607377
 657 id_isar1=34677009
 658 id_isar2=555950401
 659 id_isar3=17899825
 660 id_isar4=268501314
 661 id_isar5=0
 662 id_mmfr0=270536963
 663 id_mmfr1=0
 664 id_mmfr2=19070976
 665 id_mmfr3=34611729
 666 id_pfr0=49
 667 id_pfr1=4113
 668 midr=1091551472
 669 pmu=Null
 670 system=system
 671
 672 [system.cpu.istage2_mmu]
 673 type=ArmStage2MMU
 674 children=stage2_tlb
 675 eventq_index=0
 676 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 677 sys=system
 678 tlb=system.cpu.itb
 679
 680 [system.cpu.istage2_mmu.stage2_tlb]
 681 type=ArmTLB
 682 children=walker
 683 eventq_index=0
 684 is_stage2=true
 685 size=32
 686 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 687
 688 [system.cpu.istage2_mmu.stage2_tlb.walker]
 689 type=ArmTableWalker
 690 clk_domain=system.cpu_clk_domain
 691 default_p_state=UNDEFINED
 692 eventq_index=0
 693 is_stage2=true
 694 num_squash_per_cycle=2
 695 p_state_clk_gate_bins=20
 696 p_state_clk_gate_max=1000000000000
 697 p_state_clk_gate_min=1000
 698 power_model=Null
 699 sys=system
 700
 701 [system.cpu.itb]
 702 type=ArmTLB
 703 children=walker
 704 eventq_index=0
 705 is_stage2=false
 706 size=64
 707 walker=system.cpu.itb.walker
 708
 709 [system.cpu.itb.walker]
 710 type=ArmTableWalker
 711 clk_domain=system.cpu_clk_domain
 712 default_p_state=UNDEFINED
 713 eventq_index=0
 714 is_stage2=false
 715 num_squash_per_cycle=2
 716 p_state_clk_gate_bins=20
 717 p_state_clk_gate_max=1000000000000
 718 p_state_clk_gate_min=1000
 719 power_model=Null
 720 sys=system
 721 port=system.cpu.toL2Bus.slave[2]
 722
 723 [system.cpu.l2cache]
 724 type=Cache
 725 children=tags
 726 addr_ranges=0:18446744073709551615
 727 assoc=8
 728 clk_domain=system.cpu_clk_domain
 729 clusivity=mostly_incl
 730 default_p_state=UNDEFINED
 731 demand_mshr_reserve=1
 732 eventq_index=0
 733 hit_latency=20
 734 is_read_only=false
 735 max_miss_count=0
 736 mshrs=20
 737 p_state_clk_gate_bins=20
 738 p_state_clk_gate_max=1000000000000
 739 p_state_clk_gate_min=1000
 740 power_model=Null
 741 prefetch_on_access=false
 742 prefetcher=Null
 743 response_latency=20
 744 sequential_access=false
 745 size=4194304
 746 system=system
 747 tags=system.cpu.l2cache.tags
 748 tgts_per_mshr=12
 749 write_buffers=8
 750 writeback_clean=false
 751 cpu_side=system.cpu.toL2Bus.master[0]
 752 mem_side=system.membus.slave[2]
 753
 754 [system.cpu.l2cache.tags]
 755 type=LRU
 756 assoc=8
 757 block_size=64
 758 clk_domain=system.cpu_clk_domain
 759 default_p_state=UNDEFINED
 760 eventq_index=0
 761 hit_latency=20
 762 p_state_clk_gate_bins=20
 763 p_state_clk_gate_max=1000000000000
 764 p_state_clk_gate_min=1000
 765 power_model=Null
 766 sequential_access=false
 767 size=4194304
 768
 769 [system.cpu.toL2Bus]
 770 type=CoherentXBar
 771 children=snoop_filter
 772 clk_domain=system.cpu_clk_domain
 773 default_p_state=UNDEFINED
 774 eventq_index=0
 775 forward_latency=0
 776 frontend_latency=1
 777 p_state_clk_gate_bins=20
 778 p_state_clk_gate_max=1000000000000
 779 p_state_clk_gate_min=1000
 780 point_of_coherency=false
 781 power_model=Null
 782 response_latency=1
 783 snoop_filter=system.cpu.toL2Bus.snoop_filter
 784 snoop_response_latency=1
 785 system=system
 786 use_default_range=false
 787 width=32
 788 master=system.cpu.l2cache.cpu_side
 789 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 790
 791 [system.cpu.toL2Bus.snoop_filter]
 792 type=SnoopFilter
 793 eventq_index=0
 794 lookup_latency=0
 795 max_capacity=8388608
 796 system=system
 797
 798 [system.cpu.tracer]
 799 type=ExeTracer
 800 eventq_index=0
 801
 802 [system.cpu_clk_domain]
 803 type=SrcClockDomain
 804 clock=500
 805 domain_id=-1
 806 eventq_index=0
 807 init_perf_level=0
 808 voltage_domain=system.voltage_domain
 809
 810 [system.dvfs_handler]
 811 type=DVFSHandler
 812 domains=
 813 enable=false
 814 eventq_index=0
 815 sys_clk_domain=system.clk_domain
 816 transition_latency=100000000
 817
 818 [system.intrctrl]
 819 type=IntrControl
 820 eventq_index=0
 821 sys=system
 822
 823 [system.iobus]
 824 type=NoncoherentXBar
 825 clk_domain=system.clk_domain
 826 default_p_state=UNDEFINED
 827 eventq_index=0
 828 forward_latency=1
 829 frontend_latency=2
 830 p_state_clk_gate_bins=20
 831 p_state_clk_gate_max=1000000000000
 832 p_state_clk_gate_min=1000
 833 power_model=Null
 834 response_latency=2
 835 use_default_range=false
 836 width=16
 837 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 838 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 839
 840 [system.iocache]
 841 type=Cache
 842 children=tags
 843 addr_ranges=2147483648:2415919103
 844 assoc=8
 845 clk_domain=system.clk_domain
 846 clusivity=mostly_incl
 847 default_p_state=UNDEFINED
 848 demand_mshr_reserve=1
 849 eventq_index=0
 850 hit_latency=50
 851 is_read_only=false
 852 max_miss_count=0
 853 mshrs=20
 854 p_state_clk_gate_bins=20
 855 p_state_clk_gate_max=1000000000000
 856 p_state_clk_gate_min=1000
 857 power_model=Null
 858 prefetch_on_access=false
 859 prefetcher=Null
 860 response_latency=50
 861 sequential_access=false
 862 size=1024
 863 system=system
 864 tags=system.iocache.tags
 865 tgts_per_mshr=12
 866 write_buffers=8
 867 writeback_clean=false
 868 cpu_side=system.iobus.master[25]
 869 mem_side=system.membus.slave[3]
 870
 871 [system.iocache.tags]
 872 type=LRU
 873 assoc=8
 874 block_size=64
 875 clk_domain=system.clk_domain
 876 default_p_state=UNDEFINED
 877 eventq_index=0
 878 hit_latency=50
 879 p_state_clk_gate_bins=20
 880 p_state_clk_gate_max=1000000000000
 881 p_state_clk_gate_min=1000
 882 power_model=Null
 883 sequential_access=false
 884 size=1024
 885
 886 [system.membus]
 887 type=CoherentXBar
 888 children=badaddr_responder
 889 clk_domain=system.clk_domain
 890 default_p_state=UNDEFINED
 891 eventq_index=0
 892 forward_latency=4
 893 frontend_latency=3
 894 p_state_clk_gate_bins=20
 895 p_state_clk_gate_max=1000000000000
 896 p_state_clk_gate_min=1000
 897 point_of_coherency=true
 898 power_model=Null
 899 response_latency=2
 900 snoop_filter=Null
 901 snoop_response_latency=4
 902 system=system
 903 use_default_range=false
 904 width=16
 905 default=system.membus.badaddr_responder.pio
 906 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 907 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 908
 909 [system.membus.badaddr_responder]
 910 type=IsaFake
 911 clk_domain=system.clk_domain
 912 default_p_state=UNDEFINED
 913 eventq_index=0
 914 fake_mem=false
 915 p_state_clk_gate_bins=20
 916 p_state_clk_gate_max=1000000000000
 917 p_state_clk_gate_min=1000
 918 pio_addr=0
 919 pio_latency=100000
 920 pio_size=8
 921 power_model=Null
 922 ret_bad_addr=true
 923 ret_data16=65535
 924 ret_data32=4294967295
 925 ret_data64=18446744073709551615
 926 ret_data8=255
 927 system=system
 928 update_data=false
 929 warn_access=warn
 930 pio=system.membus.default
 931
 932 [system.physmem]
 933 type=DRAMCtrl
 934 IDD0=0.075000
 935 IDD02=0.000000
 936 IDD2N=0.050000
 937 IDD2N2=0.000000
 938 IDD2P0=0.000000
 939 IDD2P02=0.000000
 940 IDD2P1=0.000000
 941 IDD2P12=0.000000
 942 IDD3N=0.057000
 943 IDD3N2=0.000000
 944 IDD3P0=0.000000
 945 IDD3P02=0.000000
 946 IDD3P1=0.000000
 947 IDD3P12=0.000000
 948 IDD4R=0.187000
 949 IDD4R2=0.000000
 950 IDD4W=0.165000
 951 IDD4W2=0.000000
 952 IDD5=0.220000
 953 IDD52=0.000000
 954 IDD6=0.000000
 955 IDD62=0.000000
 956 VDD=1.500000
 957 VDD2=0.000000
 958 activation_limit=4
 959 addr_mapping=RoRaBaCoCh
 960 bank_groups_per_rank=0
 961 banks_per_rank=8
 962 burst_length=8
 963 channels=1
 964 clk_domain=system.clk_domain
 965 conf_table_reported=true
 966 default_p_state=UNDEFINED
 967 device_bus_width=8
 968 device_rowbuffer_size=1024
 969 device_size=536870912
 970 devices_per_rank=8
 971 dll=true
 972 eventq_index=0
 973 in_addr_map=true
 974 max_accesses_per_row=16
 975 mem_sched_policy=frfcfs
 976 min_writes_per_switch=16
 977 null=false
 978 p_state_clk_gate_bins=20
 979 p_state_clk_gate_max=1000000000000
 980 p_state_clk_gate_min=1000
 981 page_policy=open_adaptive
 982 power_model=Null
 983 range=2147483648:2415919103
 984 ranks_per_channel=2
 985 read_buffer_size=32
 986 static_backend_latency=10000
 987 static_frontend_latency=10000
 988 tBURST=5000
 989 tCCD_L=0
 990 tCK=1250
 991 tCL=13750
 992 tCS=2500
 993 tRAS=35000
 994 tRCD=13750
 995 tREFI=7800000
 996 tRFC=260000
 997 tRP=13750
 998 tRRD=6000
 999 tRRD_L=0
1000 tRTP=7500
1001 tRTW=2500
1002 tWR=15000
1003 tWTR=7500
1004 tXAW=30000
1005 tXP=0
1006 tXPDLL=0
1007 tXS=0
1008 tXSDLL=0
1009 write_buffer_size=64
1010 write_high_thresh_perc=85
1011 write_low_thresh_perc=50
1012 port=system.membus.master[5]
1013
1014 [system.realview]
1015 type=RealView
1016 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1017 eventq_index=0
1018 intrctrl=system.intrctrl
1019 system=system
1020
1021 [system.realview.aaci_fake]
1022 type=AmbaFake
1023 amba_id=0
1024 clk_domain=system.clk_domain
1025 default_p_state=UNDEFINED
1026 eventq_index=0
1027 ignore_access=false
1028 p_state_clk_gate_bins=20
1029 p_state_clk_gate_max=1000000000000
1030 p_state_clk_gate_min=1000
1031 pio_addr=470024192
1032 pio_latency=100000
1033 power_model=Null
1034 system=system
1035 pio=system.iobus.master[18]
1036
1037 [system.realview.cf_ctrl]
1038 type=IdeController
1039 BAR0=471465984
1040 BAR0LegacyIO=true
1041 BAR0Size=256
1042 BAR1=471466240
1043 BAR1LegacyIO=true
1044 BAR1Size=4096
1045 BAR2=1
1046 BAR2LegacyIO=false
1047 BAR2Size=8
1048 BAR3=1
1049 BAR3LegacyIO=false
1050 BAR3Size=4
1051 BAR4=1
1052 BAR4LegacyIO=false
1053 BAR4Size=16
1054 BAR5=1
1055 BAR5LegacyIO=false
1056 BAR5Size=0
1057 BIST=0
1058 CacheLineSize=0
1059 CapabilityPtr=0
1060 CardbusCIS=0
1061 ClassCode=1
1062 Command=1
1063 DeviceID=28945
1064 ExpansionROM=0
1065 HeaderType=0
1066 InterruptLine=31
1067 InterruptPin=1
1068 LatencyTimer=0
1069 LegacyIOBase=0
1070 MSICAPBaseOffset=0
1071 MSICAPCapId=0
1072 MSICAPMaskBits=0
1073 MSICAPMsgAddr=0
1074 MSICAPMsgCtrl=0
1075 MSICAPMsgData=0
1076 MSICAPMsgUpperAddr=0
1077 MSICAPNextCapability=0
1078 MSICAPPendingBits=0
1079 MSIXCAPBaseOffset=0
1080 MSIXCAPCapId=0
1081 MSIXCAPNextCapability=0
1082 MSIXMsgCtrl=0
1083 MSIXPbaOffset=0
1084 MSIXTableOffset=0
1085 MaximumLatency=0
1086 MinimumGrant=0
1087 PMCAPBaseOffset=0
1088 PMCAPCapId=0
1089 PMCAPCapabilities=0
1090 PMCAPCtrlStatus=0
1091 PMCAPNextCapability=0
1092 PXCAPBaseOffset=0
1093 PXCAPCapId=0
1094 PXCAPCapabilities=0
1095 PXCAPDevCap2=0
1096 PXCAPDevCapabilities=0
1097 PXCAPDevCtrl=0
1098 PXCAPDevCtrl2=0
1099 PXCAPDevStatus=0
1100 PXCAPLinkCap=0
1101 PXCAPLinkCtrl=0
1102 PXCAPLinkStatus=0
1103 PXCAPNextCapability=0
1104 ProgIF=133
1105 Revision=0
1106 Status=640
1107 SubClassCode=1
1108 SubsystemID=0
1109 SubsystemVendorID=0
1110 VendorID=32902
1111 clk_domain=system.clk_domain
1112 config_latency=20000
1113 ctrl_offset=2
1114 default_p_state=UNDEFINED
1115 disks=
1116 eventq_index=0
1117 host=system.realview.pci_host
1118 io_shift=2
1119 p_state_clk_gate_bins=20
1120 p_state_clk_gate_max=1000000000000
1121 p_state_clk_gate_min=1000
1122 pci_bus=2
1123 pci_dev=0
1124 pci_func=0
1125 pio_latency=30000
1126 power_model=Null
1127 system=system
1128 dma=system.iobus.slave[2]
1129 pio=system.iobus.master[9]
1130
1131 [system.realview.clcd]
1132 type=Pl111
1133 amba_id=1315089
1134 clk_domain=system.clk_domain
1135 default_p_state=UNDEFINED
1136 enable_capture=true
1137 eventq_index=0
1138 gic=system.realview.gic
1139 int_num=46
1140 p_state_clk_gate_bins=20
1141 p_state_clk_gate_max=1000000000000
1142 p_state_clk_gate_min=1000
1143 pio_addr=471793664
1144 pio_latency=10000
1145 pixel_clock=41667
1146 power_model=Null
1147 system=system
1148 vnc=system.vncserver
1149 dma=system.iobus.slave[1]
1150 pio=system.iobus.master[5]
1151
1152 [system.realview.dcc]
1153 type=SubSystem
1154 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1155 eventq_index=0
1156 thermal_domain=Null
1157
1158 [system.realview.dcc.osc_cpu]
1159 type=RealViewOsc
1160 dcc=0
1161 device=0
1162 eventq_index=0
1163 freq=16667
1164 parent=system.realview.realview_io
1165 position=0
1166 site=1
1167 voltage_domain=system.voltage_domain
1168
1169 [system.realview.dcc.osc_ddr]
1170 type=RealViewOsc
1171 dcc=0
1172 device=8
1173 eventq_index=0
1174 freq=25000
1175 parent=system.realview.realview_io
1176 position=0
1177 site=1
1178 voltage_domain=system.voltage_domain
1179
1180 [system.realview.dcc.osc_hsbm]
1181 type=RealViewOsc
1182 dcc=0
1183 device=4
1184 eventq_index=0
1185 freq=25000
1186 parent=system.realview.realview_io
1187 position=0
1188 site=1
1189 voltage_domain=system.voltage_domain
1190
1191 [system.realview.dcc.osc_pxl]
1192 type=RealViewOsc
1193 dcc=0
1194 device=5
1195 eventq_index=0
1196 freq=42105
1197 parent=system.realview.realview_io
1198 position=0
1199 site=1
1200 voltage_domain=system.voltage_domain
1201
1202 [system.realview.dcc.osc_smb]
1203 type=RealViewOsc
1204 dcc=0
1205 device=6
1206 eventq_index=0
1207 freq=20000
1208 parent=system.realview.realview_io
1209 position=0
1210 site=1
1211 voltage_domain=system.voltage_domain
1212
1213 [system.realview.dcc.osc_sys]
1214 type=RealViewOsc
1215 dcc=0
1216 device=7
1217 eventq_index=0
1218 freq=16667
1219 parent=system.realview.realview_io
1220 position=0
1221 site=1
1222 voltage_domain=system.voltage_domain
1223
1224 [system.realview.energy_ctrl]
1225 type=EnergyCtrl
1226 clk_domain=system.clk_domain
1227 default_p_state=UNDEFINED
1228 dvfs_handler=system.dvfs_handler
1229 eventq_index=0
1230 p_state_clk_gate_bins=20
1231 p_state_clk_gate_max=1000000000000
1232 p_state_clk_gate_min=1000
1233 pio_addr=470286336
1234 pio_latency=100000
1235 power_model=Null
1236 system=system
1237 pio=system.iobus.master[22]
1238
1239 [system.realview.ethernet]
1240 type=IGbE
1241 BAR0=0
1242 BAR0LegacyIO=false
1243 BAR0Size=131072
1244 BAR1=0
1245 BAR1LegacyIO=false
1246 BAR1Size=0
1247 BAR2=0
1248 BAR2LegacyIO=false
1249 BAR2Size=0
1250 BAR3=0
1251 BAR3LegacyIO=false
1252 BAR3Size=0
1253 BAR4=0
1254 BAR4LegacyIO=false
1255 BAR4Size=0
1256 BAR5=0
1257 BAR5LegacyIO=false
1258 BAR5Size=0
1259 BIST=0
1260 CacheLineSize=0
1261 CapabilityPtr=0
1262 CardbusCIS=0
1263 ClassCode=2
1264 Command=0
1265 DeviceID=4213
1266 ExpansionROM=0
1267 HeaderType=0
1268 InterruptLine=1
1269 InterruptPin=1
1270 LatencyTimer=0
1271 LegacyIOBase=0
1272 MSICAPBaseOffset=0
1273 MSICAPCapId=0
1274 MSICAPMaskBits=0
1275 MSICAPMsgAddr=0
1276 MSICAPMsgCtrl=0
1277 MSICAPMsgData=0
1278 MSICAPMsgUpperAddr=0
1279 MSICAPNextCapability=0
1280 MSICAPPendingBits=0
1281 MSIXCAPBaseOffset=0
1282 MSIXCAPCapId=0
1283 MSIXCAPNextCapability=0
1284 MSIXMsgCtrl=0
1285 MSIXPbaOffset=0
1286 MSIXTableOffset=0
1287 MaximumLatency=0
1288 MinimumGrant=255
1289 PMCAPBaseOffset=0
1290 PMCAPCapId=0
1291 PMCAPCapabilities=0
1292 PMCAPCtrlStatus=0
1293 PMCAPNextCapability=0
1294 PXCAPBaseOffset=0
1295 PXCAPCapId=0
1296 PXCAPCapabilities=0
1297 PXCAPDevCap2=0
1298 PXCAPDevCapabilities=0
1299 PXCAPDevCtrl=0
1300 PXCAPDevCtrl2=0
1301 PXCAPDevStatus=0
1302 PXCAPLinkCap=0
1303 PXCAPLinkCtrl=0
1304 PXCAPLinkStatus=0
1305 PXCAPNextCapability=0
1306 ProgIF=0
1307 Revision=0
1308 Status=0
1309 SubClassCode=0
1310 SubsystemID=4104
1311 SubsystemVendorID=32902
1312 VendorID=32902
1313 clk_domain=system.clk_domain
1314 config_latency=20000
1315 default_p_state=UNDEFINED
1316 eventq_index=0
1317 fetch_comp_delay=10000
1318 fetch_delay=10000
1319 hardware_address=00:90:00:00:00:01
1320 host=system.realview.pci_host
1321 p_state_clk_gate_bins=20
1322 p_state_clk_gate_max=1000000000000
1323 p_state_clk_gate_min=1000
1324 pci_bus=0
1325 pci_dev=0
1326 pci_func=0
1327 phy_epid=896
1328 phy_pid=680
1329 pio_latency=30000
1330 power_model=Null
1331 rx_desc_cache_size=64
1332 rx_fifo_size=393216
1333 rx_write_delay=0
1334 system=system
1335 tx_desc_cache_size=64
1336 tx_fifo_size=393216
1337 tx_read_delay=0
1338 wb_comp_delay=10000
1339 wb_delay=10000
1340 dma=system.iobus.slave[4]
1341 pio=system.iobus.master[24]
1342
1343 [system.realview.generic_timer]
1344 type=GenericTimer
1345 eventq_index=0
1346 gic=system.realview.gic
1347 int_phys=29
1348 int_virt=27
1349 system=system
1350
1351 [system.realview.gic]
1352 type=Pl390
1353 clk_domain=system.clk_domain
1354 cpu_addr=738205696
1355 cpu_pio_delay=10000
1356 default_p_state=UNDEFINED
1357 dist_addr=738201600
1358 dist_pio_delay=10000
1359 eventq_index=0
1360 gem5_extensions=true
1361 int_latency=10000
1362 it_lines=128
1363 p_state_clk_gate_bins=20
1364 p_state_clk_gate_max=1000000000000
1365 p_state_clk_gate_min=1000
1366 platform=system.realview
1367 power_model=Null
1368 system=system
1369 pio=system.membus.master[2]
1370
1371 [system.realview.hdlcd]
1372 type=HDLcd
1373 amba_id=1314816
1374 clk_domain=system.clk_domain
1375 default_p_state=UNDEFINED
1376 enable_capture=true
1377 eventq_index=0
1378 gic=system.realview.gic
1379 int_num=117
1380 p_state_clk_gate_bins=20
1381 p_state_clk_gate_max=1000000000000
1382 p_state_clk_gate_min=1000
1383 pio_addr=721420288
1384 pio_latency=10000
1385 pixel_buffer_size=2048
1386 pixel_chunk=32
1387 power_model=Null
1388 pxl_clk=system.realview.dcc.osc_pxl
1389 system=system
1390 vnc=system.vncserver
1391 workaround_dma_line_count=true
1392 workaround_swap_rb=true
1393 dma=system.membus.slave[0]
1394 pio=system.iobus.master[6]
1395
1396 [system.realview.ide]
1397 type=IdeController
1398 BAR0=1
1399 BAR0LegacyIO=false
1400 BAR0Size=8
1401 BAR1=1
1402 BAR1LegacyIO=false
1403 BAR1Size=4
1404 BAR2=1
1405 BAR2LegacyIO=false
1406 BAR2Size=8
1407 BAR3=1
1408 BAR3LegacyIO=false
1409 BAR3Size=4
1410 BAR4=1
1411 BAR4LegacyIO=false
1412 BAR4Size=16
1413 BAR5=1
1414 BAR5LegacyIO=false
1415 BAR5Size=0
1416 BIST=0
1417 CacheLineSize=0
1418 CapabilityPtr=0
1419 CardbusCIS=0
1420 ClassCode=1
1421 Command=0
1422 DeviceID=28945
1423 ExpansionROM=0
1424 HeaderType=0
1425 InterruptLine=2
1426 InterruptPin=2
1427 LatencyTimer=0
1428 LegacyIOBase=0
1429 MSICAPBaseOffset=0
1430 MSICAPCapId=0
1431 MSICAPMaskBits=0
1432 MSICAPMsgAddr=0
1433 MSICAPMsgCtrl=0
1434 MSICAPMsgData=0
1435 MSICAPMsgUpperAddr=0
1436 MSICAPNextCapability=0
1437 MSICAPPendingBits=0
1438 MSIXCAPBaseOffset=0
1439 MSIXCAPCapId=0
1440 MSIXCAPNextCapability=0
1441 MSIXMsgCtrl=0
1442 MSIXPbaOffset=0
1443 MSIXTableOffset=0
1444 MaximumLatency=0
1445 MinimumGrant=0
1446 PMCAPBaseOffset=0
1447 PMCAPCapId=0
1448 PMCAPCapabilities=0
1449 PMCAPCtrlStatus=0
1450 PMCAPNextCapability=0
1451 PXCAPBaseOffset=0
1452 PXCAPCapId=0
1453 PXCAPCapabilities=0
1454 PXCAPDevCap2=0
1455 PXCAPDevCapabilities=0
1456 PXCAPDevCtrl=0
1457 PXCAPDevCtrl2=0
1458 PXCAPDevStatus=0
1459 PXCAPLinkCap=0
1460 PXCAPLinkCtrl=0
1461 PXCAPLinkStatus=0
1462 PXCAPNextCapability=0
1463 ProgIF=133
1464 Revision=0
1465 Status=640
1466 SubClassCode=1
1467 SubsystemID=0
1468 SubsystemVendorID=0
1469 VendorID=32902
1470 clk_domain=system.clk_domain
1471 config_latency=20000
1472 ctrl_offset=0
1473 default_p_state=UNDEFINED
1474 disks=system.cf0
1475 eventq_index=0
1476 host=system.realview.pci_host
1477 io_shift=0
1478 p_state_clk_gate_bins=20
1479 p_state_clk_gate_max=1000000000000
1480 p_state_clk_gate_min=1000
1481 pci_bus=0
1482 pci_dev=1
1483 pci_func=0
1484 pio_latency=30000
1485 power_model=Null
1486 system=system
1487 dma=system.iobus.slave[3]
1488 pio=system.iobus.master[23]
1489
1490 [system.realview.kmi0]
1491 type=Pl050
1492 amba_id=1314896
1493 clk_domain=system.clk_domain
1494 default_p_state=UNDEFINED
1495 eventq_index=0
1496 gic=system.realview.gic
1497 int_delay=1000000
1498 int_num=44
1499 is_mouse=false
1500 p_state_clk_gate_bins=20
1501 p_state_clk_gate_max=1000000000000
1502 p_state_clk_gate_min=1000
1503 pio_addr=470155264
1504 pio_latency=100000
1505 power_model=Null
1506 system=system
1507 vnc=system.vncserver
1508 pio=system.iobus.master[7]
1509
1510 [system.realview.kmi1]
1511 type=Pl050
1512 amba_id=1314896
1513 clk_domain=system.clk_domain
1514 default_p_state=UNDEFINED
1515 eventq_index=0
1516 gic=system.realview.gic
1517 int_delay=1000000
1518 int_num=45
1519 is_mouse=true
1520 p_state_clk_gate_bins=20
1521 p_state_clk_gate_max=1000000000000
1522 p_state_clk_gate_min=1000
1523 pio_addr=470220800
1524 pio_latency=100000
1525 power_model=Null
1526 system=system
1527 vnc=system.vncserver
1528 pio=system.iobus.master[8]
1529
1530 [system.realview.l2x0_fake]
1531 type=IsaFake
1532 clk_domain=system.clk_domain
1533 default_p_state=UNDEFINED
1534 eventq_index=0
1535 fake_mem=false
1536 p_state_clk_gate_bins=20
1537 p_state_clk_gate_max=1000000000000
1538 p_state_clk_gate_min=1000
1539 pio_addr=739246080
1540 pio_latency=100000
1541 pio_size=4095
1542 power_model=Null
1543 ret_bad_addr=false
1544 ret_data16=65535
1545 ret_data32=4294967295
1546 ret_data64=18446744073709551615
1547 ret_data8=255
1548 system=system
1549 update_data=false
1550 warn_access=
1551 pio=system.iobus.master[12]
1552
1553 [system.realview.lan_fake]
1554 type=IsaFake
1555 clk_domain=system.clk_domain
1556 default_p_state=UNDEFINED
1557 eventq_index=0
1558 fake_mem=false
1559 p_state_clk_gate_bins=20
1560 p_state_clk_gate_max=1000000000000
1561 p_state_clk_gate_min=1000
1562 pio_addr=436207616
1563 pio_latency=100000
1564 pio_size=65535
1565 power_model=Null
1566 ret_bad_addr=false
1567 ret_data16=65535
1568 ret_data32=4294967295
1569 ret_data64=18446744073709551615
1570 ret_data8=255
1571 system=system
1572 update_data=false
1573 warn_access=
1574 pio=system.iobus.master[19]
1575
1576 [system.realview.local_cpu_timer]
1577 type=CpuLocalTimer
1578 clk_domain=system.clk_domain
1579 default_p_state=UNDEFINED
1580 eventq_index=0
1581 gic=system.realview.gic
1582 int_num_timer=29
1583 int_num_watchdog=30
1584 p_state_clk_gate_bins=20
1585 p_state_clk_gate_max=1000000000000
1586 p_state_clk_gate_min=1000
1587 pio_addr=738721792
1588 pio_latency=100000
1589 power_model=Null
1590 system=system
1591 pio=system.membus.master[4]
1592
1593 [system.realview.mcc]
1594 type=SubSystem
1595 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1596 eventq_index=0
1597 thermal_domain=Null
1598
1599 [system.realview.mcc.osc_clcd]
1600 type=RealViewOsc
1601 dcc=0
1602 device=1
1603 eventq_index=0
1604 freq=42105
1605 parent=system.realview.realview_io
1606 position=0
1607 site=0
1608 voltage_domain=system.voltage_domain
1609
1610 [system.realview.mcc.osc_mcc]
1611 type=RealViewOsc
1612 dcc=0
1613 device=0
1614 eventq_index=0
1615 freq=20000
1616 parent=system.realview.realview_io
1617 position=0
1618 site=0
1619 voltage_domain=system.voltage_domain
1620
1621 [system.realview.mcc.osc_peripheral]
1622 type=RealViewOsc
1623 dcc=0
1624 device=2
1625 eventq_index=0
1626 freq=41667
1627 parent=system.realview.realview_io
1628 position=0
1629 site=0
1630 voltage_domain=system.voltage_domain
1631
1632 [system.realview.mcc.osc_system_bus]
1633 type=RealViewOsc
1634 dcc=0
1635 device=4
1636 eventq_index=0
1637 freq=41667
1638 parent=system.realview.realview_io
1639 position=0
1640 site=0
1641 voltage_domain=system.voltage_domain
1642
1643 [system.realview.mcc.temp_crtl]
1644 type=RealViewTemperatureSensor
1645 dcc=0
1646 device=0
1647 eventq_index=0
1648 parent=system.realview.realview_io
1649 position=0
1650 site=0
1651 system=system
1652
1653 [system.realview.mmc_fake]
1654 type=AmbaFake
1655 amba_id=0
1656 clk_domain=system.clk_domain
1657 default_p_state=UNDEFINED
1658 eventq_index=0
1659 ignore_access=false
1660 p_state_clk_gate_bins=20
1661 p_state_clk_gate_max=1000000000000
1662 p_state_clk_gate_min=1000
1663 pio_addr=470089728
1664 pio_latency=100000
1665 power_model=Null
1666 system=system
1667 pio=system.iobus.master[21]
1668
1669 [system.realview.nvmem]
1670 type=SimpleMemory
1671 bandwidth=73.000000
1672 clk_domain=system.clk_domain
1673 conf_table_reported=false
1674 default_p_state=UNDEFINED
1675 eventq_index=0
1676 in_addr_map=true
1677 latency=30000
1678 latency_var=0
1679 null=false
1680 p_state_clk_gate_bins=20
1681 p_state_clk_gate_max=1000000000000
1682 p_state_clk_gate_min=1000
1683 power_model=Null
1684 range=0:67108863
1685 port=system.membus.master[1]
1686
1687 [system.realview.pci_host]
1688 type=GenericPciHost
1689 clk_domain=system.clk_domain
1690 conf_base=805306368
1691 conf_device_bits=16
1692 conf_size=268435456
1693 default_p_state=UNDEFINED
1694 eventq_index=0
1695 p_state_clk_gate_bins=20
1696 p_state_clk_gate_max=1000000000000
1697 p_state_clk_gate_min=1000
1698 pci_dma_base=0
1699 pci_mem_base=0
1700 pci_pio_base=0
1701 platform=system.realview
1702 power_model=Null
1703 system=system
1704 pio=system.iobus.master[2]
1705
1706 [system.realview.realview_io]
1707 type=RealViewCtrl
1708 clk_domain=system.clk_domain
1709 default_p_state=UNDEFINED
1710 eventq_index=0
1711 idreg=35979264
1712 p_state_clk_gate_bins=20
1713 p_state_clk_gate_max=1000000000000
1714 p_state_clk_gate_min=1000
1715 pio_addr=469827584
1716 pio_latency=100000
1717 power_model=Null
1718 proc_id0=335544320
1719 proc_id1=335544320
1720 system=system
1721 pio=system.iobus.master[1]
1722
1723 [system.realview.rtc]
1724 type=PL031
1725 amba_id=3412017
1726 clk_domain=system.clk_domain
1727 default_p_state=UNDEFINED
1728 eventq_index=0
1729 gic=system.realview.gic
1730 int_delay=100000
1731 int_num=36
1732 p_state_clk_gate_bins=20
1733 p_state_clk_gate_max=1000000000000
1734 p_state_clk_gate_min=1000
1735 pio_addr=471269376
1736 pio_latency=100000
1737 power_model=Null
1738 system=system
1739 time=Thu Jan  1 00:00:00 2009
1740 pio=system.iobus.master[10]
1741
1742 [system.realview.sp810_fake]
1743 type=AmbaFake
1744 amba_id=0
1745 clk_domain=system.clk_domain
1746 default_p_state=UNDEFINED
1747 eventq_index=0
1748 ignore_access=true
1749 p_state_clk_gate_bins=20
1750 p_state_clk_gate_max=1000000000000
1751 p_state_clk_gate_min=1000
1752 pio_addr=469893120
1753 pio_latency=100000
1754 power_model=Null
1755 system=system
1756 pio=system.iobus.master[16]
1757
1758 [system.realview.timer0]
1759 type=Sp804
1760 amba_id=1316868
1761 clk_domain=system.clk_domain
1762 clock0=1000000
1763 clock1=1000000
1764 default_p_state=UNDEFINED
1765 eventq_index=0
1766 gic=system.realview.gic
1767 int_num0=34
1768 int_num1=34
1769 p_state_clk_gate_bins=20
1770 p_state_clk_gate_max=1000000000000
1771 p_state_clk_gate_min=1000
1772 pio_addr=470876160
1773 pio_latency=100000
1774 power_model=Null
1775 system=system
1776 pio=system.iobus.master[3]
1777
1778 [system.realview.timer1]
1779 type=Sp804
1780 amba_id=1316868
1781 clk_domain=system.clk_domain
1782 clock0=1000000
1783 clock1=1000000
1784 default_p_state=UNDEFINED
1785 eventq_index=0
1786 gic=system.realview.gic
1787 int_num0=35
1788 int_num1=35
1789 p_state_clk_gate_bins=20
1790 p_state_clk_gate_max=1000000000000
1791 p_state_clk_gate_min=1000
1792 pio_addr=470941696
1793 pio_latency=100000
1794 power_model=Null
1795 system=system
1796 pio=system.iobus.master[4]
1797
1798 [system.realview.uart]
1799 type=Pl011
1800 clk_domain=system.clk_domain
1801 default_p_state=UNDEFINED
1802 end_on_eot=false
1803 eventq_index=0
1804 gic=system.realview.gic
1805 int_delay=100000
1806 int_num=37
1807 p_state_clk_gate_bins=20
1808 p_state_clk_gate_max=1000000000000
1809 p_state_clk_gate_min=1000
1810 pio_addr=470351872
1811 pio_latency=100000
1812 platform=system.realview
1813 power_model=Null
1814 system=system
1815 terminal=system.terminal
1816 pio=system.iobus.master[0]
1817
1818 [system.realview.uart1_fake]
1819 type=AmbaFake
1820 amba_id=0
1821 clk_domain=system.clk_domain
1822 default_p_state=UNDEFINED
1823 eventq_index=0
1824 ignore_access=false
1825 p_state_clk_gate_bins=20
1826 p_state_clk_gate_max=1000000000000
1827 p_state_clk_gate_min=1000
1828 pio_addr=470417408
1829 pio_latency=100000
1830 power_model=Null
1831 system=system
1832 pio=system.iobus.master[13]
1833
1834 [system.realview.uart2_fake]
1835 type=AmbaFake
1836 amba_id=0
1837 clk_domain=system.clk_domain
1838 default_p_state=UNDEFINED
1839 eventq_index=0
1840 ignore_access=false
1841 p_state_clk_gate_bins=20
1842 p_state_clk_gate_max=1000000000000
1843 p_state_clk_gate_min=1000
1844 pio_addr=470482944
1845 pio_latency=100000
1846 power_model=Null
1847 system=system
1848 pio=system.iobus.master[14]
1849
1850 [system.realview.uart3_fake]
1851 type=AmbaFake
1852 amba_id=0
1853 clk_domain=system.clk_domain
1854 default_p_state=UNDEFINED
1855 eventq_index=0
1856 ignore_access=false
1857 p_state_clk_gate_bins=20
1858 p_state_clk_gate_max=1000000000000
1859 p_state_clk_gate_min=1000
1860 pio_addr=470548480
1861 pio_latency=100000
1862 power_model=Null
1863 system=system
1864 pio=system.iobus.master[15]
1865
1866 [system.realview.usb_fake]
1867 type=IsaFake
1868 clk_domain=system.clk_domain
1869 default_p_state=UNDEFINED
1870 eventq_index=0
1871 fake_mem=false
1872 p_state_clk_gate_bins=20
1873 p_state_clk_gate_max=1000000000000
1874 p_state_clk_gate_min=1000
1875 pio_addr=452984832
1876 pio_latency=100000
1877 pio_size=131071
1878 power_model=Null
1879 ret_bad_addr=false
1880 ret_data16=65535
1881 ret_data32=4294967295
1882 ret_data64=18446744073709551615
1883 ret_data8=255
1884 system=system
1885 update_data=false
1886 warn_access=
1887 pio=system.iobus.master[20]
1888
1889 [system.realview.vgic]
1890 type=VGic
1891 clk_domain=system.clk_domain
1892 default_p_state=UNDEFINED
1893 eventq_index=0
1894 gic=system.realview.gic
1895 hv_addr=738213888
1896 p_state_clk_gate_bins=20
1897 p_state_clk_gate_max=1000000000000
1898 p_state_clk_gate_min=1000
1899 pio_delay=10000
1900 platform=system.realview
1901 power_model=Null
1902 ppint=25
1903 system=system
1904 vcpu_addr=738222080
1905 pio=system.membus.master[3]
1906
1907 [system.realview.vram]
1908 type=SimpleMemory
1909 bandwidth=73.000000
1910 clk_domain=system.clk_domain
1911 conf_table_reported=false
1912 default_p_state=UNDEFINED
1913 eventq_index=0
1914 in_addr_map=true
1915 latency=30000
1916 latency_var=0
1917 null=false
1918 p_state_clk_gate_bins=20
1919 p_state_clk_gate_max=1000000000000
1920 p_state_clk_gate_min=1000
1921 power_model=Null
1922 range=402653184:436207615
1923 port=system.iobus.master[11]
1924
1925 [system.realview.watchdog_fake]
1926 type=AmbaFake
1927 amba_id=0
1928 clk_domain=system.clk_domain
1929 default_p_state=UNDEFINED
1930 eventq_index=0
1931 ignore_access=false
1932 p_state_clk_gate_bins=20
1933 p_state_clk_gate_max=1000000000000
1934 p_state_clk_gate_min=1000
1935 pio_addr=470745088
1936 pio_latency=100000
1937 power_model=Null
1938 system=system
1939 pio=system.iobus.master[17]
1940
1941 [system.terminal]
1942 type=Terminal
1943 eventq_index=0
1944 intr_control=system.intrctrl
1945 number=0
1946 output=true
1947 port=3456
1948
1949 [system.vncserver]
1950 type=VncServer
1951 eventq_index=0
1952 frame_capture=false
1953 number=0
1954 port=5900
1955
1956 [system.voltage_domain]
1957 type=VoltageDomain
1958 eventq_index=0
1959 voltage=1.000000
1960