8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
15 boot_loader=/work/gem5/dist/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
24 gic_cpu_addr=738205696
25 have_large_asid_64=false
28 have_virtualization=false
29 highest_el_is_64=false
31 kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
32 kernel_addr_check=true
33 load_addr_mask=268435455
34 load_offset=2147483648
35 machine_type=VExpress_EMM
37 mem_ranges=2147483648:2415919103
38 memories=system.physmem system.realview.nvmem system.realview.vram
39 mmap_using_noreserve=false
46 readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
49 work_begin_ckpt_count=0
50 work_begin_cpu_id_exit=-1
51 work_begin_exit_count=0
52 work_cpus_ckpt_count=0
56 system_port=system.membus.slave[1]
60 clk_domain=system.clk_domain
63 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
66 master=system.iobus.slave[0]
67 slave=system.membus.master[0]
75 image=system.cf0.image
80 child=system.cf0.image.child
86 [system.cf0.image.child]
89 image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
98 voltage_domain=system.voltage_domain
102 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
111 branchPred=system.cpu.branchPred
114 clk_domain=system.cpu_clk_domain
115 commitToDecodeDelay=1
118 commitToRenameDelay=1
122 decodeToRenameDelay=2
125 do_checkpoint_insts=true
127 do_statistics_insts=true
128 dstage2_mmu=system.cpu.dstage2_mmu
137 fuPool=system.cpu.fuPool
139 function_trace_start=0
144 interrupts=system.cpu.interrupts
146 issueToExecuteDelay=1
148 istage2_mmu=system.cpu.istage2_mmu
150 max_insts_all_threads=0
151 max_insts_any_thread=0
152 max_loads_all_threads=0
153 max_loads_any_thread=0
164 renameToDecodeDelay=1
169 simpoint_start_insts=
170 smtCommitPolicy=RoundRobin
171 smtFetchPolicy=SingleThread
172 smtIQPolicy=Partitioned
174 smtLSQPolicy=Partitioned
176 smtNumFetchingThreads=1
177 smtROBPolicy=Partitioned
181 store_set_clear_period=250000
184 tracer=system.cpu.tracer
188 dcache_port=system.cpu.dcache.cpu_side
189 icache_port=system.cpu.icache.cpu_side
191 [system.cpu.branchPred]
197 choicePredictorSize=8192
200 globalPredictorSize=8192
207 addr_ranges=0:18446744073709551615
209 clk_domain=system.cpu_clk_domain
210 clusivity=mostly_incl
211 demand_mshr_reserve=1
218 prefetch_on_access=false
221 sequential_access=false
224 tags=system.cpu.dcache.tags
227 writeback_clean=false
228 cpu_side=system.cpu.dcache_port
229 mem_side=system.cpu.toL2Bus.slave[1]
231 [system.cpu.dcache.tags]
235 clk_domain=system.cpu_clk_domain
238 sequential_access=false
241 [system.cpu.dstage2_mmu]
245 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
249 [system.cpu.dstage2_mmu.stage2_tlb]
255 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
257 [system.cpu.dstage2_mmu.stage2_tlb.walker]
259 clk_domain=system.cpu_clk_domain
262 num_squash_per_cycle=2
271 walker=system.cpu.dtb.walker
273 [system.cpu.dtb.walker]
275 clk_domain=system.cpu_clk_domain
278 num_squash_per_cycle=2
280 port=system.cpu.toL2Bus.slave[3]
284 children=FUList0 FUList1 FUList2 FUList3 FUList4
285 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
288 [system.cpu.fuPool.FUList0]
293 opList=system.cpu.fuPool.FUList0.opList
295 [system.cpu.fuPool.FUList0.opList]
302 [system.cpu.fuPool.FUList1]
304 children=opList0 opList1 opList2
307 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
309 [system.cpu.fuPool.FUList1.opList0]
316 [system.cpu.fuPool.FUList1.opList1]
323 [system.cpu.fuPool.FUList1.opList2]
330 [system.cpu.fuPool.FUList2]
335 opList=system.cpu.fuPool.FUList2.opList
337 [system.cpu.fuPool.FUList2.opList]
344 [system.cpu.fuPool.FUList3]
349 opList=system.cpu.fuPool.FUList3.opList
351 [system.cpu.fuPool.FUList3.opList]
358 [system.cpu.fuPool.FUList4]
360 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
363 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
365 [system.cpu.fuPool.FUList4.opList00]
372 [system.cpu.fuPool.FUList4.opList01]
379 [system.cpu.fuPool.FUList4.opList02]
386 [system.cpu.fuPool.FUList4.opList03]
393 [system.cpu.fuPool.FUList4.opList04]
400 [system.cpu.fuPool.FUList4.opList05]
407 [system.cpu.fuPool.FUList4.opList06]
414 [system.cpu.fuPool.FUList4.opList07]
421 [system.cpu.fuPool.FUList4.opList08]
428 [system.cpu.fuPool.FUList4.opList09]
435 [system.cpu.fuPool.FUList4.opList10]
442 [system.cpu.fuPool.FUList4.opList11]
449 [system.cpu.fuPool.FUList4.opList12]
456 [system.cpu.fuPool.FUList4.opList13]
463 [system.cpu.fuPool.FUList4.opList14]
470 [system.cpu.fuPool.FUList4.opList15]
477 [system.cpu.fuPool.FUList4.opList16]
480 opClass=SimdFloatMisc
484 [system.cpu.fuPool.FUList4.opList17]
487 opClass=SimdFloatMult
491 [system.cpu.fuPool.FUList4.opList18]
494 opClass=SimdFloatMultAcc
498 [system.cpu.fuPool.FUList4.opList19]
501 opClass=SimdFloatSqrt
505 [system.cpu.fuPool.FUList4.opList20]
512 [system.cpu.fuPool.FUList4.opList21]
519 [system.cpu.fuPool.FUList4.opList22]
526 [system.cpu.fuPool.FUList4.opList23]
533 [system.cpu.fuPool.FUList4.opList24]
540 [system.cpu.fuPool.FUList4.opList25]
550 addr_ranges=0:18446744073709551615
552 clk_domain=system.cpu_clk_domain
553 clusivity=mostly_incl
554 demand_mshr_reserve=1
561 prefetch_on_access=false
564 sequential_access=false
567 tags=system.cpu.icache.tags
571 cpu_side=system.cpu.icache_port
572 mem_side=system.cpu.toL2Bus.slave[0]
574 [system.cpu.icache.tags]
578 clk_domain=system.cpu_clk_domain
581 sequential_access=false
584 [system.cpu.interrupts]
590 decoderFlavour=Generic
595 id_aa64dfr0_el1=1052678
599 id_aa64mmfr0_el1=15728642
619 [system.cpu.istage2_mmu]
623 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
627 [system.cpu.istage2_mmu.stage2_tlb]
633 walker=system.cpu.istage2_mmu.stage2_tlb.walker
635 [system.cpu.istage2_mmu.stage2_tlb.walker]
637 clk_domain=system.cpu_clk_domain
640 num_squash_per_cycle=2
649 walker=system.cpu.itb.walker
651 [system.cpu.itb.walker]
653 clk_domain=system.cpu_clk_domain
656 num_squash_per_cycle=2
658 port=system.cpu.toL2Bus.slave[2]
663 addr_ranges=0:18446744073709551615
665 clk_domain=system.cpu_clk_domain
666 clusivity=mostly_incl
667 demand_mshr_reserve=1
674 prefetch_on_access=false
677 sequential_access=false
680 tags=system.cpu.l2cache.tags
683 writeback_clean=false
684 cpu_side=system.cpu.toL2Bus.master[0]
685 mem_side=system.membus.slave[2]
687 [system.cpu.l2cache.tags]
691 clk_domain=system.cpu_clk_domain
694 sequential_access=false
699 children=snoop_filter
700 clk_domain=system.cpu_clk_domain
705 snoop_filter=system.cpu.toL2Bus.snoop_filter
706 snoop_response_latency=1
708 use_default_range=false
710 master=system.cpu.l2cache.cpu_side
711 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
713 [system.cpu.toL2Bus.snoop_filter]
724 [system.cpu_clk_domain]
730 voltage_domain=system.voltage_domain
732 [system.dvfs_handler]
737 sys_clk_domain=system.clk_domain
738 transition_latency=100000000
747 clk_domain=system.clk_domain
752 use_default_range=false
754 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
755 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
760 addr_ranges=2147483648:2415919103
762 clk_domain=system.clk_domain
763 clusivity=mostly_incl
764 demand_mshr_reserve=1
771 prefetch_on_access=false
774 sequential_access=false
777 tags=system.iocache.tags
780 writeback_clean=false
781 cpu_side=system.iobus.master[25]
782 mem_side=system.membus.slave[3]
784 [system.iocache.tags]
788 clk_domain=system.clk_domain
791 sequential_access=false
796 children=badaddr_responder
797 clk_domain=system.clk_domain
803 snoop_response_latency=4
805 use_default_range=false
807 default=system.membus.badaddr_responder.pio
808 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
809 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
811 [system.membus.badaddr_responder]
813 clk_domain=system.clk_domain
821 ret_data32=4294967295
822 ret_data64=18446744073709551615
827 pio=system.membus.default
856 addr_mapping=RoRaBaCoCh
857 bank_groups_per_rank=0
861 clk_domain=system.clk_domain
862 conf_table_reported=true
864 device_rowbuffer_size=1024
865 device_size=536870912
870 max_accesses_per_row=16
871 mem_sched_policy=frfcfs
872 min_writes_per_switch=16
874 page_policy=open_adaptive
875 range=2147483648:2415919103
878 static_backend_latency=10000
879 static_frontend_latency=10000
902 write_high_thresh_perc=85
903 write_low_thresh_perc=50
904 port=system.membus.master[5]
908 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
910 intrctrl=system.intrctrl
913 [system.realview.aaci_fake]
916 clk_domain=system.clk_domain
922 pio=system.iobus.master[18]
924 [system.realview.cf_ctrl]
964 MSICAPNextCapability=0
968 MSIXCAPNextCapability=0
978 PMCAPNextCapability=0
983 PXCAPDevCapabilities=0
990 PXCAPNextCapability=0
998 clk_domain=system.clk_domain
1003 host=system.realview.pci_host
1010 dma=system.iobus.slave[2]
1011 pio=system.iobus.master[9]
1013 [system.realview.clcd]
1016 clk_domain=system.clk_domain
1019 gic=system.realview.gic
1025 vnc=system.vncserver
1026 dma=system.iobus.slave[1]
1027 pio=system.iobus.master[5]
1029 [system.realview.dcc]
1031 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1034 [system.realview.dcc.osc_cpu]
1040 parent=system.realview.realview_io
1043 voltage_domain=system.voltage_domain
1045 [system.realview.dcc.osc_ddr]
1051 parent=system.realview.realview_io
1054 voltage_domain=system.voltage_domain
1056 [system.realview.dcc.osc_hsbm]
1062 parent=system.realview.realview_io
1065 voltage_domain=system.voltage_domain
1067 [system.realview.dcc.osc_pxl]
1073 parent=system.realview.realview_io
1076 voltage_domain=system.voltage_domain
1078 [system.realview.dcc.osc_smb]
1084 parent=system.realview.realview_io
1087 voltage_domain=system.voltage_domain
1089 [system.realview.dcc.osc_sys]
1095 parent=system.realview.realview_io
1098 voltage_domain=system.voltage_domain
1100 [system.realview.energy_ctrl]
1102 clk_domain=system.clk_domain
1103 dvfs_handler=system.dvfs_handler
1108 pio=system.iobus.master[22]
1110 [system.realview.ethernet]
1149 MSICAPMsgUpperAddr=0
1150 MSICAPNextCapability=0
1154 MSIXCAPNextCapability=0
1164 PMCAPNextCapability=0
1169 PXCAPDevCapabilities=0
1176 PXCAPNextCapability=0
1182 SubsystemVendorID=32902
1184 clk_domain=system.clk_domain
1185 config_latency=20000
1187 fetch_comp_delay=10000
1189 hardware_address=00:90:00:00:00:01
1190 host=system.realview.pci_host
1197 rx_desc_cache_size=64
1201 tx_desc_cache_size=64
1206 dma=system.iobus.slave[4]
1207 pio=system.iobus.master[24]
1209 [system.realview.generic_timer]
1212 gic=system.realview.gic
1217 [system.realview.gic]
1219 clk_domain=system.clk_domain
1223 dist_pio_delay=10000
1227 platform=system.realview
1229 pio=system.membus.master[2]
1231 [system.realview.hdlcd]
1234 clk_domain=system.clk_domain
1237 gic=system.realview.gic
1241 pixel_buffer_size=2048
1243 pxl_clk=system.realview.dcc.osc_pxl
1245 vnc=system.vncserver
1246 workaround_dma_line_count=true
1247 workaround_swap_rb=true
1248 dma=system.membus.slave[0]
1249 pio=system.iobus.master[6]
1251 [system.realview.ide]
1290 MSICAPMsgUpperAddr=0
1291 MSICAPNextCapability=0
1295 MSIXCAPNextCapability=0
1305 PMCAPNextCapability=0
1310 PXCAPDevCapabilities=0
1317 PXCAPNextCapability=0
1325 clk_domain=system.clk_domain
1326 config_latency=20000
1330 host=system.realview.pci_host
1337 dma=system.iobus.slave[3]
1338 pio=system.iobus.master[23]
1340 [system.realview.kmi0]
1343 clk_domain=system.clk_domain
1345 gic=system.realview.gic
1352 vnc=system.vncserver
1353 pio=system.iobus.master[7]
1355 [system.realview.kmi1]
1358 clk_domain=system.clk_domain
1360 gic=system.realview.gic
1367 vnc=system.vncserver
1368 pio=system.iobus.master[8]
1370 [system.realview.l2x0_fake]
1372 clk_domain=system.clk_domain
1380 ret_data32=4294967295
1381 ret_data64=18446744073709551615
1386 pio=system.iobus.master[12]
1388 [system.realview.lan_fake]
1390 clk_domain=system.clk_domain
1398 ret_data32=4294967295
1399 ret_data64=18446744073709551615
1404 pio=system.iobus.master[19]
1406 [system.realview.local_cpu_timer]
1408 clk_domain=system.clk_domain
1410 gic=system.realview.gic
1416 pio=system.membus.master[4]
1418 [system.realview.mcc]
1420 children=osc_clcd osc_mcc osc_peripheral osc_system_bus
1423 [system.realview.mcc.osc_clcd]
1429 parent=system.realview.realview_io
1432 voltage_domain=system.voltage_domain
1434 [system.realview.mcc.osc_mcc]
1440 parent=system.realview.realview_io
1443 voltage_domain=system.voltage_domain
1445 [system.realview.mcc.osc_peripheral]
1451 parent=system.realview.realview_io
1454 voltage_domain=system.voltage_domain
1456 [system.realview.mcc.osc_system_bus]
1462 parent=system.realview.realview_io
1465 voltage_domain=system.voltage_domain
1467 [system.realview.mmc_fake]
1470 clk_domain=system.clk_domain
1476 pio=system.iobus.master[21]
1478 [system.realview.nvmem]
1481 clk_domain=system.clk_domain
1482 conf_table_reported=false
1489 port=system.membus.master[1]
1491 [system.realview.pci_host]
1493 clk_domain=system.clk_domain
1501 platform=system.realview
1503 pio=system.iobus.master[2]
1505 [system.realview.realview_io]
1507 clk_domain=system.clk_domain
1515 pio=system.iobus.master[1]
1517 [system.realview.rtc]
1520 clk_domain=system.clk_domain
1522 gic=system.realview.gic
1528 time=Thu Jan 1 00:00:00 2009
1529 pio=system.iobus.master[10]
1531 [system.realview.sp810_fake]
1534 clk_domain=system.clk_domain
1540 pio=system.iobus.master[16]
1542 [system.realview.timer0]
1545 clk_domain=system.clk_domain
1549 gic=system.realview.gic
1555 pio=system.iobus.master[3]
1557 [system.realview.timer1]
1560 clk_domain=system.clk_domain
1564 gic=system.realview.gic
1570 pio=system.iobus.master[4]
1572 [system.realview.uart]
1574 clk_domain=system.clk_domain
1577 gic=system.realview.gic
1582 platform=system.realview
1584 terminal=system.terminal
1585 pio=system.iobus.master[0]
1587 [system.realview.uart1_fake]
1590 clk_domain=system.clk_domain
1596 pio=system.iobus.master[13]
1598 [system.realview.uart2_fake]
1601 clk_domain=system.clk_domain
1607 pio=system.iobus.master[14]
1609 [system.realview.uart3_fake]
1612 clk_domain=system.clk_domain
1618 pio=system.iobus.master[15]
1620 [system.realview.usb_fake]
1622 clk_domain=system.clk_domain
1630 ret_data32=4294967295
1631 ret_data64=18446744073709551615
1636 pio=system.iobus.master[20]
1638 [system.realview.vgic]
1640 clk_domain=system.clk_domain
1642 gic=system.realview.gic
1645 platform=system.realview
1649 pio=system.membus.master[3]
1651 [system.realview.vram]
1654 clk_domain=system.clk_domain
1655 conf_table_reported=false
1661 range=402653184:436207615
1662 port=system.iobus.master[11]
1664 [system.realview.watchdog_fake]
1667 clk_domain=system.clk_domain
1673 pio=system.iobus.master[17]
1678 intr_control=system.intrctrl
1690 [system.voltage_domain]