tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/dist/binaries/boot.arm
  16 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 load_addr_mask=268435455
  35 load_offset=0
  36 machine_type=RealView_PBX
  37 mem_mode=timing
  38 mem_ranges=0:134217727
  39 memories=system.physmem system.realview.nvmem
  40 multi_proc=true
  41 num_work_ids=16
  42 panic_on_oops=true
  43 panic_on_panic=true
  44 phys_addr_range_64=40
  45 readfile=tests/halt.sh
  46 reset_addr_64=0
  47 symbolfile=
  48 work_begin_ckpt_count=0
  49 work_begin_cpu_id_exit=-1
  50 work_begin_exit_count=0
  51 work_cpus_ckpt_count=0
  52 work_end_ckpt_count=0
  53 work_end_exit_count=0
  54 work_item_id=-1
  55 system_port=system.membus.slave[0]
  56
  57 [system.bridge]
  58 type=Bridge
  59 clk_domain=system.clk_domain
  60 delay=50000
  61 eventq_index=0
  62 ranges=268435456:520093695 1073741824:1610612735
  63 req_size=16
  64 resp_size=16
  65 master=system.iobus.slave[0]
  66 slave=system.membus.master[0]
  67
  68 [system.cf0]
  69 type=IdeDisk
  70 children=image
  71 delay=1000000
  72 driveID=master
  73 eventq_index=0
  74 image=system.cf0.image
  75
  76 [system.cf0.image]
  77 type=CowDiskImage
  78 children=child
  79 child=system.cf0.image.child
  80 eventq_index=0
  81 image_file=
  82 read_only=false
  83 table_size=65536
  84
  85 [system.cf0.image.child]
  86 type=RawDiskImage
  87 eventq_index=0
  88 image_file=/dist/disks/linux-arm-ael.img
  89 read_only=true
  90
  91 [system.clk_domain]
  92 type=SrcClockDomain
  93 clock=1000
  94 eventq_index=0
  95 voltage_domain=system.voltage_domain
  96
  97 [system.cpu]
  98 type=DerivO3CPU
  99 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 100 LFSTSize=1024
 101 LQEntries=32
 102 LSQCheckLoads=true
 103 LSQDepCheckShift=4
 104 SQEntries=32
 105 SSITSize=1024
 106 activity=0
 107 backComSize=5
 108 branchPred=system.cpu.branchPred
 109 cachePorts=200
 110 checker=Null
 111 clk_domain=system.cpu_clk_domain
 112 commitToDecodeDelay=1
 113 commitToFetchDelay=1
 114 commitToIEWDelay=1
 115 commitToRenameDelay=1
 116 commitWidth=8
 117 cpu_id=0
 118 decodeToFetchDelay=1
 119 decodeToRenameDelay=1
 120 decodeWidth=8
 121 dispatchWidth=8
 122 do_checkpoint_insts=true
 123 do_quiesce=true
 124 do_statistics_insts=true
 125 dstage2_mmu=system.cpu.dstage2_mmu
 126 dtb=system.cpu.dtb
 127 eventq_index=0
 128 fetchBufferSize=64
 129 fetchToDecodeDelay=1
 130 fetchTrapLatency=1
 131 fetchWidth=8
 132 forwardComSize=5
 133 fuPool=system.cpu.fuPool
 134 function_trace=false
 135 function_trace_start=0
 136 iewToCommitDelay=1
 137 iewToDecodeDelay=1
 138 iewToFetchDelay=1
 139 iewToRenameDelay=1
 140 interrupts=system.cpu.interrupts
 141 isa=system.cpu.isa
 142 issueToExecuteDelay=1
 143 issueWidth=8
 144 istage2_mmu=system.cpu.istage2_mmu
 145 itb=system.cpu.itb
 146 max_insts_all_threads=0
 147 max_insts_any_thread=0
 148 max_loads_all_threads=0
 149 max_loads_any_thread=0
 150 needsTSO=false
 151 numIQEntries=64
 152 numPhysCCRegs=0
 153 numPhysFloatRegs=256
 154 numPhysIntRegs=256
 155 numROBEntries=192
 156 numRobs=1
 157 numThreads=1
 158 profile=0
 159 progress_interval=0
 160 renameToDecodeDelay=1
 161 renameToFetchDelay=1
 162 renameToIEWDelay=2
 163 renameToROBDelay=1
 164 renameWidth=8
 165 simpoint_start_insts=
 166 smtCommitPolicy=RoundRobin
 167 smtFetchPolicy=SingleThread
 168 smtIQPolicy=Partitioned
 169 smtIQThreshold=100
 170 smtLSQPolicy=Partitioned
 171 smtLSQThreshold=100
 172 smtNumFetchingThreads=1
 173 smtROBPolicy=Partitioned
 174 smtROBThreshold=100
 175 squashWidth=8
 176 store_set_clear_period=250000
 177 switched_out=false
 178 system=system
 179 tracer=system.cpu.tracer
 180 trapLatency=13
 181 wbDepth=1
 182 wbWidth=8
 183 workload=
 184 dcache_port=system.cpu.dcache.cpu_side
 185 icache_port=system.cpu.icache.cpu_side
 186
 187 [system.cpu.branchPred]
 188 type=BranchPredictor
 189 BTBEntries=4096
 190 BTBTagSize=16
 191 RASSize=16
 192 choiceCtrBits=2
 193 choicePredictorSize=8192
 194 eventq_index=0
 195 globalCtrBits=2
 196 globalPredictorSize=8192
 197 instShiftAmt=2
 198 localCtrBits=2
 199 localHistoryTableSize=2048
 200 localPredictorSize=2048
 201 numThreads=1
 202 predType=tournament
 203
 204 [system.cpu.dcache]
 205 type=BaseCache
 206 children=tags
 207 addr_ranges=0:18446744073709551615
 208 assoc=4
 209 clk_domain=system.cpu_clk_domain
 210 eventq_index=0
 211 forward_snoops=true
 212 hit_latency=2
 213 is_top_level=true
 214 max_miss_count=0
 215 mshrs=4
 216 prefetch_on_access=false
 217 prefetcher=Null
 218 response_latency=2
 219 sequential_access=false
 220 size=32768
 221 system=system
 222 tags=system.cpu.dcache.tags
 223 tgts_per_mshr=20
 224 two_queue=false
 225 write_buffers=8
 226 cpu_side=system.cpu.dcache_port
 227 mem_side=system.cpu.toL2Bus.slave[1]
 228
 229 [system.cpu.dcache.tags]
 230 type=LRU
 231 assoc=4
 232 block_size=64
 233 clk_domain=system.cpu_clk_domain
 234 eventq_index=0
 235 hit_latency=2
 236 sequential_access=false
 237 size=32768
 238
 239 [system.cpu.dstage2_mmu]
 240 type=ArmStage2MMU
 241 children=stage2_tlb
 242 eventq_index=0
 243 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 244 tlb=system.cpu.dtb
 245
 246 [system.cpu.dstage2_mmu.stage2_tlb]
 247 type=ArmTLB
 248 children=walker
 249 eventq_index=0
 250 is_stage2=true
 251 size=32
 252 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 253
 254 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 255 type=ArmTableWalker
 256 clk_domain=system.cpu_clk_domain
 257 eventq_index=0
 258 is_stage2=true
 259 num_squash_per_cycle=2
 260 sys=system
 261 port=system.cpu.toL2Bus.slave[5]
 262
 263 [system.cpu.dtb]
 264 type=ArmTLB
 265 children=walker
 266 eventq_index=0
 267 is_stage2=false
 268 size=64
 269 walker=system.cpu.dtb.walker
 270
 271 [system.cpu.dtb.walker]
 272 type=ArmTableWalker
 273 clk_domain=system.cpu_clk_domain
 274 eventq_index=0
 275 is_stage2=false
 276 num_squash_per_cycle=2
 277 sys=system
 278 port=system.cpu.toL2Bus.slave[3]
 279
 280 [system.cpu.fuPool]
 281 type=FUPool
 282 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 283 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 284 eventq_index=0
 285
 286 [system.cpu.fuPool.FUList0]
 287 type=FUDesc
 288 children=opList
 289 count=6
 290 eventq_index=0
 291 opList=system.cpu.fuPool.FUList0.opList
 292
 293 [system.cpu.fuPool.FUList0.opList]
 294 type=OpDesc
 295 eventq_index=0
 296 issueLat=1
 297 opClass=IntAlu
 298 opLat=1
 299
 300 [system.cpu.fuPool.FUList1]
 301 type=FUDesc
 302 children=opList0 opList1
 303 count=2
 304 eventq_index=0
 305 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 306
 307 [system.cpu.fuPool.FUList1.opList0]
 308 type=OpDesc
 309 eventq_index=0
 310 issueLat=1
 311 opClass=IntMult
 312 opLat=3
 313
 314 [system.cpu.fuPool.FUList1.opList1]
 315 type=OpDesc
 316 eventq_index=0
 317 issueLat=19
 318 opClass=IntDiv
 319 opLat=20
 320
 321 [system.cpu.fuPool.FUList2]
 322 type=FUDesc
 323 children=opList0 opList1 opList2
 324 count=4
 325 eventq_index=0
 326 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 327
 328 [system.cpu.fuPool.FUList2.opList0]
 329 type=OpDesc
 330 eventq_index=0
 331 issueLat=1
 332 opClass=FloatAdd
 333 opLat=2
 334
 335 [system.cpu.fuPool.FUList2.opList1]
 336 type=OpDesc
 337 eventq_index=0
 338 issueLat=1
 339 opClass=FloatCmp
 340 opLat=2
 341
 342 [system.cpu.fuPool.FUList2.opList2]
 343 type=OpDesc
 344 eventq_index=0
 345 issueLat=1
 346 opClass=FloatCvt
 347 opLat=2
 348
 349 [system.cpu.fuPool.FUList3]
 350 type=FUDesc
 351 children=opList0 opList1 opList2
 352 count=2
 353 eventq_index=0
 354 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 355
 356 [system.cpu.fuPool.FUList3.opList0]
 357 type=OpDesc
 358 eventq_index=0
 359 issueLat=1
 360 opClass=FloatMult
 361 opLat=4
 362
 363 [system.cpu.fuPool.FUList3.opList1]
 364 type=OpDesc
 365 eventq_index=0
 366 issueLat=12
 367 opClass=FloatDiv
 368 opLat=12
 369
 370 [system.cpu.fuPool.FUList3.opList2]
 371 type=OpDesc
 372 eventq_index=0
 373 issueLat=24
 374 opClass=FloatSqrt
 375 opLat=24
 376
 377 [system.cpu.fuPool.FUList4]
 378 type=FUDesc
 379 children=opList
 380 count=0
 381 eventq_index=0
 382 opList=system.cpu.fuPool.FUList4.opList
 383
 384 [system.cpu.fuPool.FUList4.opList]
 385 type=OpDesc
 386 eventq_index=0
 387 issueLat=1
 388 opClass=MemRead
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList5]
 392 type=FUDesc
 393 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 394 count=4
 395 eventq_index=0
 396 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 397
 398 [system.cpu.fuPool.FUList5.opList00]
 399 type=OpDesc
 400 eventq_index=0
 401 issueLat=1
 402 opClass=SimdAdd
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList5.opList01]
 406 type=OpDesc
 407 eventq_index=0
 408 issueLat=1
 409 opClass=SimdAddAcc
 410 opLat=1
 411
 412 [system.cpu.fuPool.FUList5.opList02]
 413 type=OpDesc
 414 eventq_index=0
 415 issueLat=1
 416 opClass=SimdAlu
 417 opLat=1
 418
 419 [system.cpu.fuPool.FUList5.opList03]
 420 type=OpDesc
 421 eventq_index=0
 422 issueLat=1
 423 opClass=SimdCmp
 424 opLat=1
 425
 426 [system.cpu.fuPool.FUList5.opList04]
 427 type=OpDesc
 428 eventq_index=0
 429 issueLat=1
 430 opClass=SimdCvt
 431 opLat=1
 432
 433 [system.cpu.fuPool.FUList5.opList05]
 434 type=OpDesc
 435 eventq_index=0
 436 issueLat=1
 437 opClass=SimdMisc
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList5.opList06]
 441 type=OpDesc
 442 eventq_index=0
 443 issueLat=1
 444 opClass=SimdMult
 445 opLat=1
 446
 447 [system.cpu.fuPool.FUList5.opList07]
 448 type=OpDesc
 449 eventq_index=0
 450 issueLat=1
 451 opClass=SimdMultAcc
 452 opLat=1
 453
 454 [system.cpu.fuPool.FUList5.opList08]
 455 type=OpDesc
 456 eventq_index=0
 457 issueLat=1
 458 opClass=SimdShift
 459 opLat=1
 460
 461 [system.cpu.fuPool.FUList5.opList09]
 462 type=OpDesc
 463 eventq_index=0
 464 issueLat=1
 465 opClass=SimdShiftAcc
 466 opLat=1
 467
 468 [system.cpu.fuPool.FUList5.opList10]
 469 type=OpDesc
 470 eventq_index=0
 471 issueLat=1
 472 opClass=SimdSqrt
 473 opLat=1
 474
 475 [system.cpu.fuPool.FUList5.opList11]
 476 type=OpDesc
 477 eventq_index=0
 478 issueLat=1
 479 opClass=SimdFloatAdd
 480 opLat=1
 481
 482 [system.cpu.fuPool.FUList5.opList12]
 483 type=OpDesc
 484 eventq_index=0
 485 issueLat=1
 486 opClass=SimdFloatAlu
 487 opLat=1
 488
 489 [system.cpu.fuPool.FUList5.opList13]
 490 type=OpDesc
 491 eventq_index=0
 492 issueLat=1
 493 opClass=SimdFloatCmp
 494 opLat=1
 495
 496 [system.cpu.fuPool.FUList5.opList14]
 497 type=OpDesc
 498 eventq_index=0
 499 issueLat=1
 500 opClass=SimdFloatCvt
 501 opLat=1
 502
 503 [system.cpu.fuPool.FUList5.opList15]
 504 type=OpDesc
 505 eventq_index=0
 506 issueLat=1
 507 opClass=SimdFloatDiv
 508 opLat=1
 509
 510 [system.cpu.fuPool.FUList5.opList16]
 511 type=OpDesc
 512 eventq_index=0
 513 issueLat=1
 514 opClass=SimdFloatMisc
 515 opLat=1
 516
 517 [system.cpu.fuPool.FUList5.opList17]
 518 type=OpDesc
 519 eventq_index=0
 520 issueLat=1
 521 opClass=SimdFloatMult
 522 opLat=1
 523
 524 [system.cpu.fuPool.FUList5.opList18]
 525 type=OpDesc
 526 eventq_index=0
 527 issueLat=1
 528 opClass=SimdFloatMultAcc
 529 opLat=1
 530
 531 [system.cpu.fuPool.FUList5.opList19]
 532 type=OpDesc
 533 eventq_index=0
 534 issueLat=1
 535 opClass=SimdFloatSqrt
 536 opLat=1
 537
 538 [system.cpu.fuPool.FUList6]
 539 type=FUDesc
 540 children=opList
 541 count=0
 542 eventq_index=0
 543 opList=system.cpu.fuPool.FUList6.opList
 544
 545 [system.cpu.fuPool.FUList6.opList]
 546 type=OpDesc
 547 eventq_index=0
 548 issueLat=1
 549 opClass=MemWrite
 550 opLat=1
 551
 552 [system.cpu.fuPool.FUList7]
 553 type=FUDesc
 554 children=opList0 opList1
 555 count=4
 556 eventq_index=0
 557 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 558
 559 [system.cpu.fuPool.FUList7.opList0]
 560 type=OpDesc
 561 eventq_index=0
 562 issueLat=1
 563 opClass=MemRead
 564 opLat=1
 565
 566 [system.cpu.fuPool.FUList7.opList1]
 567 type=OpDesc
 568 eventq_index=0
 569 issueLat=1
 570 opClass=MemWrite
 571 opLat=1
 572
 573 [system.cpu.fuPool.FUList8]
 574 type=FUDesc
 575 children=opList
 576 count=1
 577 eventq_index=0
 578 opList=system.cpu.fuPool.FUList8.opList
 579
 580 [system.cpu.fuPool.FUList8.opList]
 581 type=OpDesc
 582 eventq_index=0
 583 issueLat=3
 584 opClass=IprAccess
 585 opLat=3
 586
 587 [system.cpu.icache]
 588 type=BaseCache
 589 children=tags
 590 addr_ranges=0:18446744073709551615
 591 assoc=1
 592 clk_domain=system.cpu_clk_domain
 593 eventq_index=0
 594 forward_snoops=true
 595 hit_latency=2
 596 is_top_level=true
 597 max_miss_count=0
 598 mshrs=4
 599 prefetch_on_access=false
 600 prefetcher=Null
 601 response_latency=2
 602 sequential_access=false
 603 size=32768
 604 system=system
 605 tags=system.cpu.icache.tags
 606 tgts_per_mshr=20
 607 two_queue=false
 608 write_buffers=8
 609 cpu_side=system.cpu.icache_port
 610 mem_side=system.cpu.toL2Bus.slave[0]
 611
 612 [system.cpu.icache.tags]
 613 type=LRU
 614 assoc=1
 615 block_size=64
 616 clk_domain=system.cpu_clk_domain
 617 eventq_index=0
 618 hit_latency=2
 619 sequential_access=false
 620 size=32768
 621
 622 [system.cpu.interrupts]
 623 type=ArmInterrupts
 624 eventq_index=0
 625
 626 [system.cpu.isa]
 627 type=ArmISA
 628 eventq_index=0
 629 fpsid=1090793632
 630 id_aa64afr0_el1=0
 631 id_aa64afr1_el1=0
 632 id_aa64dfr0_el1=1052678
 633 id_aa64dfr1_el1=0
 634 id_aa64isar0_el1=0
 635 id_aa64isar1_el1=0
 636 id_aa64mmfr0_el1=15728642
 637 id_aa64mmfr1_el1=0
 638 id_aa64pfr0_el1=17
 639 id_aa64pfr1_el1=0
 640 id_isar0=34607377
 641 id_isar1=34677009
 642 id_isar2=555950401
 643 id_isar3=17899825
 644 id_isar4=268501314
 645 id_isar5=0
 646 id_mmfr0=270536963
 647 id_mmfr1=0
 648 id_mmfr2=19070976
 649 id_mmfr3=34611729
 650 id_pfr0=49
 651 id_pfr1=4113
 652 midr=1091551472
 653 system=system
 654
 655 [system.cpu.istage2_mmu]
 656 type=ArmStage2MMU
 657 children=stage2_tlb
 658 eventq_index=0
 659 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 660 tlb=system.cpu.itb
 661
 662 [system.cpu.istage2_mmu.stage2_tlb]
 663 type=ArmTLB
 664 children=walker
 665 eventq_index=0
 666 is_stage2=true
 667 size=32
 668 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 669
 670 [system.cpu.istage2_mmu.stage2_tlb.walker]
 671 type=ArmTableWalker
 672 clk_domain=system.cpu_clk_domain
 673 eventq_index=0
 674 is_stage2=true
 675 num_squash_per_cycle=2
 676 sys=system
 677 port=system.cpu.toL2Bus.slave[4]
 678
 679 [system.cpu.itb]
 680 type=ArmTLB
 681 children=walker
 682 eventq_index=0
 683 is_stage2=false
 684 size=64
 685 walker=system.cpu.itb.walker
 686
 687 [system.cpu.itb.walker]
 688 type=ArmTableWalker
 689 clk_domain=system.cpu_clk_domain
 690 eventq_index=0
 691 is_stage2=false
 692 num_squash_per_cycle=2
 693 sys=system
 694 port=system.cpu.toL2Bus.slave[2]
 695
 696 [system.cpu.l2cache]
 697 type=BaseCache
 698 children=tags
 699 addr_ranges=0:18446744073709551615
 700 assoc=8
 701 clk_domain=system.cpu_clk_domain
 702 eventq_index=0
 703 forward_snoops=true
 704 hit_latency=20
 705 is_top_level=false
 706 max_miss_count=0
 707 mshrs=20
 708 prefetch_on_access=false
 709 prefetcher=Null
 710 response_latency=20
 711 sequential_access=false
 712 size=4194304
 713 system=system
 714 tags=system.cpu.l2cache.tags
 715 tgts_per_mshr=12
 716 two_queue=false
 717 write_buffers=8
 718 cpu_side=system.cpu.toL2Bus.master[0]
 719 mem_side=system.membus.slave[1]
 720
 721 [system.cpu.l2cache.tags]
 722 type=LRU
 723 assoc=8
 724 block_size=64
 725 clk_domain=system.cpu_clk_domain
 726 eventq_index=0
 727 hit_latency=20
 728 sequential_access=false
 729 size=4194304
 730
 731 [system.cpu.toL2Bus]
 732 type=CoherentBus
 733 clk_domain=system.cpu_clk_domain
 734 eventq_index=0
 735 header_cycles=1
 736 system=system
 737 use_default_range=false
 738 width=32
 739 master=system.cpu.l2cache.cpu_side
 740 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 741
 742 [system.cpu.tracer]
 743 type=ExeTracer
 744 eventq_index=0
 745
 746 [system.cpu_clk_domain]
 747 type=SrcClockDomain
 748 clock=500
 749 eventq_index=0
 750 voltage_domain=system.voltage_domain
 751
 752 [system.intrctrl]
 753 type=IntrControl
 754 eventq_index=0
 755 sys=system
 756
 757 [system.iobus]
 758 type=NoncoherentBus
 759 clk_domain=system.clk_domain
 760 eventq_index=0
 761 header_cycles=1
 762 use_default_range=false
 763 width=8
 764 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 765 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 766
 767 [system.iocache]
 768 type=BaseCache
 769 children=tags
 770 addr_ranges=0:134217727
 771 assoc=8
 772 clk_domain=system.clk_domain
 773 eventq_index=0
 774 forward_snoops=false
 775 hit_latency=50
 776 is_top_level=true
 777 max_miss_count=0
 778 mshrs=20
 779 prefetch_on_access=false
 780 prefetcher=Null
 781 response_latency=50
 782 sequential_access=false
 783 size=1024
 784 system=system
 785 tags=system.iocache.tags
 786 tgts_per_mshr=12
 787 two_queue=false
 788 write_buffers=8
 789 cpu_side=system.iobus.master[25]
 790 mem_side=system.membus.slave[2]
 791
 792 [system.iocache.tags]
 793 type=LRU
 794 assoc=8
 795 block_size=64
 796 clk_domain=system.clk_domain
 797 eventq_index=0
 798 hit_latency=50
 799 sequential_access=false
 800 size=1024
 801
 802 [system.membus]
 803 type=CoherentBus
 804 children=badaddr_responder
 805 clk_domain=system.clk_domain
 806 eventq_index=0
 807 header_cycles=1
 808 system=system
 809 use_default_range=false
 810 width=8
 811 default=system.membus.badaddr_responder.pio
 812 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 813 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 814
 815 [system.membus.badaddr_responder]
 816 type=IsaFake
 817 clk_domain=system.clk_domain
 818 eventq_index=0
 819 fake_mem=false
 820 pio_addr=0
 821 pio_latency=100000
 822 pio_size=8
 823 ret_bad_addr=true
 824 ret_data16=65535
 825 ret_data32=4294967295
 826 ret_data64=18446744073709551615
 827 ret_data8=255
 828 system=system
 829 update_data=false
 830 warn_access=warn
 831 pio=system.membus.default
 832
 833 [system.physmem]
 834 type=SimpleDRAM
 835 activation_limit=4
 836 addr_mapping=RaBaChCo
 837 banks_per_rank=8
 838 burst_length=8
 839 channels=1
 840 clk_domain=system.clk_domain
 841 conf_table_reported=true
 842 device_bus_width=8
 843 device_rowbuffer_size=1024
 844 devices_per_rank=8
 845 eventq_index=0
 846 in_addr_map=true
 847 mem_sched_policy=frfcfs
 848 null=false
 849 page_policy=open
 850 range=0:134217727
 851 ranks_per_channel=2
 852 read_buffer_size=32
 853 static_backend_latency=10000
 854 static_frontend_latency=10000
 855 tBURST=5000
 856 tCL=13750
 857 tRAS=35000
 858 tRCD=13750
 859 tREFI=7800000
 860 tRFC=300000
 861 tRP=13750
 862 tRRD=6250
 863 tWTR=7500
 864 tXAW=40000
 865 write_buffer_size=32
 866 write_high_thresh_perc=70
 867 write_low_thresh_perc=0
 868 port=system.membus.master[6]
 869
 870 [system.realview]
 871 type=RealView
 872 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 873 eventq_index=0
 874 intrctrl=system.intrctrl
 875 max_mem_size=268435456
 876 mem_start_addr=0
 877 pci_cfg_base=0
 878 system=system
 879
 880 [system.realview.a9scu]
 881 type=A9SCU
 882 clk_domain=system.clk_domain
 883 eventq_index=0
 884 pio_addr=520093696
 885 pio_latency=100000
 886 system=system
 887 pio=system.membus.master[4]
 888
 889 [system.realview.aaci_fake]
 890 type=AmbaFake
 891 amba_id=0
 892 clk_domain=system.clk_domain
 893 eventq_index=0
 894 ignore_access=false
 895 pio_addr=268451840
 896 pio_latency=100000
 897 system=system
 898 pio=system.iobus.master[21]
 899
 900 [system.realview.cf_ctrl]
 901 type=IdeController
 902 BAR0=402653184
 903 BAR0LegacyIO=true
 904 BAR0Size=16
 905 BAR1=402653440
 906 BAR1LegacyIO=true
 907 BAR1Size=1
 908 BAR2=1
 909 BAR2LegacyIO=false
 910 BAR2Size=8
 911 BAR3=1
 912 BAR3LegacyIO=false
 913 BAR3Size=4
 914 BAR4=1
 915 BAR4LegacyIO=false
 916 BAR4Size=16
 917 BAR5=1
 918 BAR5LegacyIO=false
 919 BAR5Size=0
 920 BIST=0
 921 CacheLineSize=0
 922 CapabilityPtr=0
 923 CardbusCIS=0
 924 ClassCode=1
 925 Command=1
 926 DeviceID=28945
 927 ExpansionROM=0
 928 HeaderType=0
 929 InterruptLine=31
 930 InterruptPin=1
 931 LatencyTimer=0
 932 MSICAPBaseOffset=0
 933 MSICAPCapId=0
 934 MSICAPMaskBits=0
 935 MSICAPMsgAddr=0
 936 MSICAPMsgCtrl=0
 937 MSICAPMsgData=0
 938 MSICAPMsgUpperAddr=0
 939 MSICAPNextCapability=0
 940 MSICAPPendingBits=0
 941 MSIXCAPBaseOffset=0
 942 MSIXCAPCapId=0
 943 MSIXCAPNextCapability=0
 944 MSIXMsgCtrl=0
 945 MSIXPbaOffset=0
 946 MSIXTableOffset=0
 947 MaximumLatency=0
 948 MinimumGrant=0
 949 PMCAPBaseOffset=0
 950 PMCAPCapId=0
 951 PMCAPCapabilities=0
 952 PMCAPCtrlStatus=0
 953 PMCAPNextCapability=0
 954 PXCAPBaseOffset=0
 955 PXCAPCapId=0
 956 PXCAPCapabilities=0
 957 PXCAPDevCap2=0
 958 PXCAPDevCapabilities=0
 959 PXCAPDevCtrl=0
 960 PXCAPDevCtrl2=0
 961 PXCAPDevStatus=0
 962 PXCAPLinkCap=0
 963 PXCAPLinkCtrl=0
 964 PXCAPLinkStatus=0
 965 PXCAPNextCapability=0
 966 ProgIF=133
 967 Revision=0
 968 Status=640
 969 SubClassCode=1
 970 SubsystemID=0
 971 SubsystemVendorID=0
 972 VendorID=32902
 973 clk_domain=system.clk_domain
 974 config_latency=20000
 975 ctrl_offset=2
 976 disks=system.cf0
 977 eventq_index=0
 978 io_shift=1
 979 pci_bus=2
 980 pci_dev=7
 981 pci_func=0
 982 pio_latency=30000
 983 platform=system.realview
 984 system=system
 985 config=system.iobus.master[8]
 986 dma=system.iobus.slave[2]
 987 pio=system.iobus.master[7]
 988
 989 [system.realview.clcd]
 990 type=Pl111
 991 amba_id=1315089
 992 clk_domain=system.clk_domain
 993 enable_capture=true
 994 eventq_index=0
 995 gic=system.realview.gic
 996 int_num=55
 997 pio_addr=268566528
 998 pio_latency=10000
 999 pixel_clock=41667
1000 system=system
1001 vnc=system.vncserver
1002 dma=system.iobus.slave[1]
1003 pio=system.iobus.master[4]
1004
1005 [system.realview.dmac_fake]
1006 type=AmbaFake
1007 amba_id=0
1008 clk_domain=system.clk_domain
1009 eventq_index=0
1010 ignore_access=false
1011 pio_addr=268632064
1012 pio_latency=100000
1013 system=system
1014 pio=system.iobus.master[9]
1015
1016 [system.realview.flash_fake]
1017 type=IsaFake
1018 clk_domain=system.clk_domain
1019 eventq_index=0
1020 fake_mem=true
1021 pio_addr=1073741824
1022 pio_latency=100000
1023 pio_size=536870912
1024 ret_bad_addr=false
1025 ret_data16=65535
1026 ret_data32=4294967295
1027 ret_data64=18446744073709551615
1028 ret_data8=255
1029 system=system
1030 update_data=false
1031 warn_access=
1032 pio=system.iobus.master[24]
1033
1034 [system.realview.gic]
1035 type=Pl390
1036 clk_domain=system.clk_domain
1037 cpu_addr=520093952
1038 cpu_pio_delay=10000
1039 dist_addr=520097792
1040 dist_pio_delay=10000
1041 eventq_index=0
1042 int_latency=10000
1043 it_lines=128
1044 msix_addr=0
1045 platform=system.realview
1046 system=system
1047 pio=system.membus.master[2]
1048
1049 [system.realview.gpio0_fake]
1050 type=AmbaFake
1051 amba_id=0
1052 clk_domain=system.clk_domain
1053 eventq_index=0
1054 ignore_access=false
1055 pio_addr=268513280
1056 pio_latency=100000
1057 system=system
1058 pio=system.iobus.master[16]
1059
1060 [system.realview.gpio1_fake]
1061 type=AmbaFake
1062 amba_id=0
1063 clk_domain=system.clk_domain
1064 eventq_index=0
1065 ignore_access=false
1066 pio_addr=268517376
1067 pio_latency=100000
1068 system=system
1069 pio=system.iobus.master[17]
1070
1071 [system.realview.gpio2_fake]
1072 type=AmbaFake
1073 amba_id=0
1074 clk_domain=system.clk_domain
1075 eventq_index=0
1076 ignore_access=false
1077 pio_addr=268521472
1078 pio_latency=100000
1079 system=system
1080 pio=system.iobus.master[18]
1081
1082 [system.realview.kmi0]
1083 type=Pl050
1084 amba_id=1314896
1085 clk_domain=system.clk_domain
1086 eventq_index=0
1087 gic=system.realview.gic
1088 int_delay=1000000
1089 int_num=52
1090 is_mouse=false
1091 pio_addr=268460032
1092 pio_latency=100000
1093 system=system
1094 vnc=system.vncserver
1095 pio=system.iobus.master[5]
1096
1097 [system.realview.kmi1]
1098 type=Pl050
1099 amba_id=1314896
1100 clk_domain=system.clk_domain
1101 eventq_index=0
1102 gic=system.realview.gic
1103 int_delay=1000000
1104 int_num=53
1105 is_mouse=true
1106 pio_addr=268464128
1107 pio_latency=100000
1108 system=system
1109 vnc=system.vncserver
1110 pio=system.iobus.master[6]
1111
1112 [system.realview.l2x0_fake]
1113 type=IsaFake
1114 clk_domain=system.clk_domain
1115 eventq_index=0
1116 fake_mem=false
1117 pio_addr=520101888
1118 pio_latency=100000
1119 pio_size=4095
1120 ret_bad_addr=false
1121 ret_data16=65535
1122 ret_data32=4294967295
1123 ret_data64=18446744073709551615
1124 ret_data8=255
1125 system=system
1126 update_data=false
1127 warn_access=
1128 pio=system.membus.master[3]
1129
1130 [system.realview.local_cpu_timer]
1131 type=CpuLocalTimer
1132 clk_domain=system.clk_domain
1133 eventq_index=0
1134 gic=system.realview.gic
1135 int_num_timer=29
1136 int_num_watchdog=30
1137 pio_addr=520095232
1138 pio_latency=100000
1139 system=system
1140 pio=system.membus.master[5]
1141
1142 [system.realview.mmc_fake]
1143 type=AmbaFake
1144 amba_id=0
1145 clk_domain=system.clk_domain
1146 eventq_index=0
1147 ignore_access=false
1148 pio_addr=268455936
1149 pio_latency=100000
1150 system=system
1151 pio=system.iobus.master[22]
1152
1153 [system.realview.nvmem]
1154 type=SimpleMemory
1155 bandwidth=73.000000
1156 clk_domain=system.clk_domain
1157 conf_table_reported=false
1158 eventq_index=0
1159 in_addr_map=true
1160 latency=30000
1161 latency_var=0
1162 null=false
1163 range=2147483648:2214592511
1164 port=system.membus.master[1]
1165
1166 [system.realview.realview_io]
1167 type=RealViewCtrl
1168 clk_domain=system.clk_domain
1169 eventq_index=0
1170 idreg=0
1171 pio_addr=268435456
1172 pio_latency=100000
1173 proc_id0=201326592
1174 proc_id1=201327138
1175 system=system
1176 pio=system.iobus.master[1]
1177
1178 [system.realview.rtc]
1179 type=PL031
1180 amba_id=3412017
1181 clk_domain=system.clk_domain
1182 eventq_index=0
1183 gic=system.realview.gic
1184 int_delay=100000
1185 int_num=42
1186 pio_addr=268529664
1187 pio_latency=100000
1188 system=system
1189 time=Thu Jan  1 00:00:00 2009
1190 pio=system.iobus.master[23]
1191
1192 [system.realview.sci_fake]
1193 type=AmbaFake
1194 amba_id=0
1195 clk_domain=system.clk_domain
1196 eventq_index=0
1197 ignore_access=false
1198 pio_addr=268492800
1199 pio_latency=100000
1200 system=system
1201 pio=system.iobus.master[20]
1202
1203 [system.realview.smc_fake]
1204 type=AmbaFake
1205 amba_id=0
1206 clk_domain=system.clk_domain
1207 eventq_index=0
1208 ignore_access=false
1209 pio_addr=269357056
1210 pio_latency=100000
1211 system=system
1212 pio=system.iobus.master[13]
1213
1214 [system.realview.sp810_fake]
1215 type=AmbaFake
1216 amba_id=0
1217 clk_domain=system.clk_domain
1218 eventq_index=0
1219 ignore_access=true
1220 pio_addr=268439552
1221 pio_latency=100000
1222 system=system
1223 pio=system.iobus.master[14]
1224
1225 [system.realview.ssp_fake]
1226 type=AmbaFake
1227 amba_id=0
1228 clk_domain=system.clk_domain
1229 eventq_index=0
1230 ignore_access=false
1231 pio_addr=268488704
1232 pio_latency=100000
1233 system=system
1234 pio=system.iobus.master[19]
1235
1236 [system.realview.timer0]
1237 type=Sp804
1238 amba_id=1316868
1239 clk_domain=system.clk_domain
1240 clock0=1000000
1241 clock1=1000000
1242 eventq_index=0
1243 gic=system.realview.gic
1244 int_num0=36
1245 int_num1=36
1246 pio_addr=268505088
1247 pio_latency=100000
1248 system=system
1249 pio=system.iobus.master[2]
1250
1251 [system.realview.timer1]
1252 type=Sp804
1253 amba_id=1316868
1254 clk_domain=system.clk_domain
1255 clock0=1000000
1256 clock1=1000000
1257 eventq_index=0
1258 gic=system.realview.gic
1259 int_num0=37
1260 int_num1=37
1261 pio_addr=268509184
1262 pio_latency=100000
1263 system=system
1264 pio=system.iobus.master[3]
1265
1266 [system.realview.uart]
1267 type=Pl011
1268 clk_domain=system.clk_domain
1269 end_on_eot=false
1270 eventq_index=0
1271 gic=system.realview.gic
1272 int_delay=100000
1273 int_num=44
1274 pio_addr=268472320
1275 pio_latency=100000
1276 platform=system.realview
1277 system=system
1278 terminal=system.terminal
1279 pio=system.iobus.master[0]
1280
1281 [system.realview.uart1_fake]
1282 type=AmbaFake
1283 amba_id=0
1284 clk_domain=system.clk_domain
1285 eventq_index=0
1286 ignore_access=false
1287 pio_addr=268476416
1288 pio_latency=100000
1289 system=system
1290 pio=system.iobus.master[10]
1291
1292 [system.realview.uart2_fake]
1293 type=AmbaFake
1294 amba_id=0
1295 clk_domain=system.clk_domain
1296 eventq_index=0
1297 ignore_access=false
1298 pio_addr=268480512
1299 pio_latency=100000
1300 system=system
1301 pio=system.iobus.master[11]
1302
1303 [system.realview.uart3_fake]
1304 type=AmbaFake
1305 amba_id=0
1306 clk_domain=system.clk_domain
1307 eventq_index=0
1308 ignore_access=false
1309 pio_addr=268484608
1310 pio_latency=100000
1311 system=system
1312 pio=system.iobus.master[12]
1313
1314 [system.realview.watchdog_fake]
1315 type=AmbaFake
1316 amba_id=0
1317 clk_domain=system.clk_domain
1318 eventq_index=0
1319 ignore_access=false
1320 pio_addr=268500992
1321 pio_latency=100000
1322 system=system
1323 pio=system.iobus.master[15]
1324
1325 [system.terminal]
1326 type=Terminal
1327 eventq_index=0
1328 intr_control=system.intrctrl
1329 number=0
1330 output=true
1331 port=3456
1332
1333 [system.vncserver]
1334 type=VncServer
1335 eventq_index=0
1336 frame_capture=false
1337 number=0
1338 port=5900
1339
1340 [system.voltage_domain]
1341 type=VoltageDomain
1342 eventq_index=0
1343 voltage=1.000000
1344