tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
  12 atags_addr=256
  13 boot_loader=/dist/m5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 clock=1000
  16 dtb_filename=False
  17 early_kernel_symbols=false
  18 enable_context_switch_stats_dump=false
  19 flags_addr=268435504
  20 gic_cpu_addr=520093952
  21 init_param=0
  22 kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  23 load_addr_mask=268435455
  24 machine_type=RealView_PBX
  25 mem_mode=timing
  26 mem_ranges=0:134217727
  27 memories=system.physmem system.realview.nvmem
  28 multi_proc=true
  29 num_work_ids=16
  30 panic_on_oops=true
  31 panic_on_panic=true
  32 readfile=tests/halt.sh
  33 symbolfile=
  34 work_begin_ckpt_count=0
  35 work_begin_cpu_id_exit=-1
  36 work_begin_exit_count=0
  37 work_cpus_ckpt_count=0
  38 work_end_ckpt_count=0
  39 work_end_exit_count=0
  40 work_item_id=-1
  41 system_port=system.membus.slave[0]
  42
  43 [system.bridge]
  44 type=Bridge
  45 clock=1000
  46 delay=50000
  47 ranges=268435456:520093695 1073741824:1610612735
  48 req_size=16
  49 resp_size=16
  50 master=system.iobus.slave[0]
  51 slave=system.membus.master[0]
  52
  53 [system.cf0]
  54 type=IdeDisk
  55 children=image
  56 delay=1000000
  57 driveID=master
  58 image=system.cf0.image
  59
  60 [system.cf0.image]
  61 type=CowDiskImage
  62 children=child
  63 child=system.cf0.image.child
  64 image_file=
  65 read_only=false
  66 table_size=65536
  67
  68 [system.cf0.image.child]
  69 type=RawDiskImage
  70 image_file=/dist/m5/system/disks/linux-arm-ael.img
  71 read_only=true
  72
  73 [system.cpu]
  74 type=DerivO3CPU
  75 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  76 LFSTSize=1024
  77 LQEntries=32
  78 LSQCheckLoads=true
  79 LSQDepCheckShift=4
  80 SQEntries=32
  81 SSITSize=1024
  82 activity=0
  83 backComSize=5
  84 branchPred=system.cpu.branchPred
  85 cachePorts=200
  86 checker=Null
  87 clock=500
  88 commitToDecodeDelay=1
  89 commitToFetchDelay=1
  90 commitToIEWDelay=1
  91 commitToRenameDelay=1
  92 commitWidth=8
  93 cpu_id=0
  94 decodeToFetchDelay=1
  95 decodeToRenameDelay=1
  96 decodeWidth=8
  97 dispatchWidth=8
  98 do_checkpoint_insts=true
  99 do_quiesce=true
 100 do_statistics_insts=true
 101 dtb=system.cpu.dtb
 102 fetchToDecodeDelay=1
 103 fetchTrapLatency=1
 104 fetchWidth=8
 105 forwardComSize=5
 106 fuPool=system.cpu.fuPool
 107 function_trace=false
 108 function_trace_start=0
 109 iewToCommitDelay=1
 110 iewToDecodeDelay=1
 111 iewToFetchDelay=1
 112 iewToRenameDelay=1
 113 interrupts=system.cpu.interrupts
 114 isa=system.cpu.isa
 115 issueToExecuteDelay=1
 116 issueWidth=8
 117 itb=system.cpu.itb
 118 max_insts_all_threads=0
 119 max_insts_any_thread=0
 120 max_loads_all_threads=0
 121 max_loads_any_thread=0
 122 needsTSO=false
 123 numIQEntries=64
 124 numPhysFloatRegs=256
 125 numPhysIntRegs=256
 126 numROBEntries=192
 127 numRobs=1
 128 numThreads=1
 129 profile=0
 130 progress_interval=0
 131 renameToDecodeDelay=1
 132 renameToFetchDelay=1
 133 renameToIEWDelay=2
 134 renameToROBDelay=1
 135 renameWidth=8
 136 simpoint_start_insts=
 137 smtCommitPolicy=RoundRobin
 138 smtFetchPolicy=SingleThread
 139 smtIQPolicy=Partitioned
 140 smtIQThreshold=100
 141 smtLSQPolicy=Partitioned
 142 smtLSQThreshold=100
 143 smtNumFetchingThreads=1
 144 smtROBPolicy=Partitioned
 145 smtROBThreshold=100
 146 squashWidth=8
 147 store_set_clear_period=250000
 148 switched_out=false
 149 system=system
 150 tracer=system.cpu.tracer
 151 trapLatency=13
 152 wbDepth=1
 153 wbWidth=8
 154 workload=
 155 dcache_port=system.cpu.dcache.cpu_side
 156 icache_port=system.cpu.icache.cpu_side
 157
 158 [system.cpu.branchPred]
 159 type=BranchPredictor
 160 BTBEntries=4096
 161 BTBTagSize=16
 162 RASSize=16
 163 choiceCtrBits=2
 164 choicePredictorSize=8192
 165 globalCtrBits=2
 166 globalHistoryBits=13
 167 globalPredictorSize=8192
 168 instShiftAmt=2
 169 localCtrBits=2
 170 localHistoryBits=11
 171 localHistoryTableSize=2048
 172 localPredictorSize=2048
 173 numThreads=1
 174 predType=tournament
 175
 176 [system.cpu.dcache]
 177 type=BaseCache
 178 addr_ranges=0:18446744073709551615
 179 assoc=4
 180 block_size=64
 181 clock=500
 182 forward_snoops=true
 183 hit_latency=2
 184 is_top_level=true
 185 max_miss_count=0
 186 mshrs=4
 187 prefetch_on_access=false
 188 prefetcher=Null
 189 response_latency=2
 190 size=32768
 191 system=system
 192 tgts_per_mshr=20
 193 two_queue=false
 194 write_buffers=8
 195 cpu_side=system.cpu.dcache_port
 196 mem_side=system.cpu.toL2Bus.slave[1]
 197
 198 [system.cpu.dtb]
 199 type=ArmTLB
 200 children=walker
 201 size=64
 202 walker=system.cpu.dtb.walker
 203
 204 [system.cpu.dtb.walker]
 205 type=ArmTableWalker
 206 clock=500
 207 num_squash_per_cycle=2
 208 sys=system
 209 port=system.cpu.toL2Bus.slave[3]
 210
 211 [system.cpu.fuPool]
 212 type=FUPool
 213 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 214 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 215
 216 [system.cpu.fuPool.FUList0]
 217 type=FUDesc
 218 children=opList
 219 count=6
 220 opList=system.cpu.fuPool.FUList0.opList
 221
 222 [system.cpu.fuPool.FUList0.opList]
 223 type=OpDesc
 224 issueLat=1
 225 opClass=IntAlu
 226 opLat=1
 227
 228 [system.cpu.fuPool.FUList1]
 229 type=FUDesc
 230 children=opList0 opList1
 231 count=2
 232 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 233
 234 [system.cpu.fuPool.FUList1.opList0]
 235 type=OpDesc
 236 issueLat=1
 237 opClass=IntMult
 238 opLat=3
 239
 240 [system.cpu.fuPool.FUList1.opList1]
 241 type=OpDesc
 242 issueLat=19
 243 opClass=IntDiv
 244 opLat=20
 245
 246 [system.cpu.fuPool.FUList2]
 247 type=FUDesc
 248 children=opList0 opList1 opList2
 249 count=4
 250 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 251
 252 [system.cpu.fuPool.FUList2.opList0]
 253 type=OpDesc
 254 issueLat=1
 255 opClass=FloatAdd
 256 opLat=2
 257
 258 [system.cpu.fuPool.FUList2.opList1]
 259 type=OpDesc
 260 issueLat=1
 261 opClass=FloatCmp
 262 opLat=2
 263
 264 [system.cpu.fuPool.FUList2.opList2]
 265 type=OpDesc
 266 issueLat=1
 267 opClass=FloatCvt
 268 opLat=2
 269
 270 [system.cpu.fuPool.FUList3]
 271 type=FUDesc
 272 children=opList0 opList1 opList2
 273 count=2
 274 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 275
 276 [system.cpu.fuPool.FUList3.opList0]
 277 type=OpDesc
 278 issueLat=1
 279 opClass=FloatMult
 280 opLat=4
 281
 282 [system.cpu.fuPool.FUList3.opList1]
 283 type=OpDesc
 284 issueLat=12
 285 opClass=FloatDiv
 286 opLat=12
 287
 288 [system.cpu.fuPool.FUList3.opList2]
 289 type=OpDesc
 290 issueLat=24
 291 opClass=FloatSqrt
 292 opLat=24
 293
 294 [system.cpu.fuPool.FUList4]
 295 type=FUDesc
 296 children=opList
 297 count=0
 298 opList=system.cpu.fuPool.FUList4.opList
 299
 300 [system.cpu.fuPool.FUList4.opList]
 301 type=OpDesc
 302 issueLat=1
 303 opClass=MemRead
 304 opLat=1
 305
 306 [system.cpu.fuPool.FUList5]
 307 type=FUDesc
 308 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 309 count=4
 310 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 311
 312 [system.cpu.fuPool.FUList5.opList00]
 313 type=OpDesc
 314 issueLat=1
 315 opClass=SimdAdd
 316 opLat=1
 317
 318 [system.cpu.fuPool.FUList5.opList01]
 319 type=OpDesc
 320 issueLat=1
 321 opClass=SimdAddAcc
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList02]
 325 type=OpDesc
 326 issueLat=1
 327 opClass=SimdAlu
 328 opLat=1
 329
 330 [system.cpu.fuPool.FUList5.opList03]
 331 type=OpDesc
 332 issueLat=1
 333 opClass=SimdCmp
 334 opLat=1
 335
 336 [system.cpu.fuPool.FUList5.opList04]
 337 type=OpDesc
 338 issueLat=1
 339 opClass=SimdCvt
 340 opLat=1
 341
 342 [system.cpu.fuPool.FUList5.opList05]
 343 type=OpDesc
 344 issueLat=1
 345 opClass=SimdMisc
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList06]
 349 type=OpDesc
 350 issueLat=1
 351 opClass=SimdMult
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList07]
 355 type=OpDesc
 356 issueLat=1
 357 opClass=SimdMultAcc
 358 opLat=1
 359
 360 [system.cpu.fuPool.FUList5.opList08]
 361 type=OpDesc
 362 issueLat=1
 363 opClass=SimdShift
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList09]
 367 type=OpDesc
 368 issueLat=1
 369 opClass=SimdShiftAcc
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList5.opList10]
 373 type=OpDesc
 374 issueLat=1
 375 opClass=SimdSqrt
 376 opLat=1
 377
 378 [system.cpu.fuPool.FUList5.opList11]
 379 type=OpDesc
 380 issueLat=1
 381 opClass=SimdFloatAdd
 382 opLat=1
 383
 384 [system.cpu.fuPool.FUList5.opList12]
 385 type=OpDesc
 386 issueLat=1
 387 opClass=SimdFloatAlu
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList5.opList13]
 391 type=OpDesc
 392 issueLat=1
 393 opClass=SimdFloatCmp
 394 opLat=1
 395
 396 [system.cpu.fuPool.FUList5.opList14]
 397 type=OpDesc
 398 issueLat=1
 399 opClass=SimdFloatCvt
 400 opLat=1
 401
 402 [system.cpu.fuPool.FUList5.opList15]
 403 type=OpDesc
 404 issueLat=1
 405 opClass=SimdFloatDiv
 406 opLat=1
 407
 408 [system.cpu.fuPool.FUList5.opList16]
 409 type=OpDesc
 410 issueLat=1
 411 opClass=SimdFloatMisc
 412 opLat=1
 413
 414 [system.cpu.fuPool.FUList5.opList17]
 415 type=OpDesc
 416 issueLat=1
 417 opClass=SimdFloatMult
 418 opLat=1
 419
 420 [system.cpu.fuPool.FUList5.opList18]
 421 type=OpDesc
 422 issueLat=1
 423 opClass=SimdFloatMultAcc
 424 opLat=1
 425
 426 [system.cpu.fuPool.FUList5.opList19]
 427 type=OpDesc
 428 issueLat=1
 429 opClass=SimdFloatSqrt
 430 opLat=1
 431
 432 [system.cpu.fuPool.FUList6]
 433 type=FUDesc
 434 children=opList
 435 count=0
 436 opList=system.cpu.fuPool.FUList6.opList
 437
 438 [system.cpu.fuPool.FUList6.opList]
 439 type=OpDesc
 440 issueLat=1
 441 opClass=MemWrite
 442 opLat=1
 443
 444 [system.cpu.fuPool.FUList7]
 445 type=FUDesc
 446 children=opList0 opList1
 447 count=4
 448 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 449
 450 [system.cpu.fuPool.FUList7.opList0]
 451 type=OpDesc
 452 issueLat=1
 453 opClass=MemRead
 454 opLat=1
 455
 456 [system.cpu.fuPool.FUList7.opList1]
 457 type=OpDesc
 458 issueLat=1
 459 opClass=MemWrite
 460 opLat=1
 461
 462 [system.cpu.fuPool.FUList8]
 463 type=FUDesc
 464 children=opList
 465 count=1
 466 opList=system.cpu.fuPool.FUList8.opList
 467
 468 [system.cpu.fuPool.FUList8.opList]
 469 type=OpDesc
 470 issueLat=3
 471 opClass=IprAccess
 472 opLat=3
 473
 474 [system.cpu.icache]
 475 type=BaseCache
 476 addr_ranges=0:18446744073709551615
 477 assoc=1
 478 block_size=64
 479 clock=500
 480 forward_snoops=true
 481 hit_latency=2
 482 is_top_level=true
 483 max_miss_count=0
 484 mshrs=4
 485 prefetch_on_access=false
 486 prefetcher=Null
 487 response_latency=2
 488 size=32768
 489 system=system
 490 tgts_per_mshr=20
 491 two_queue=false
 492 write_buffers=8
 493 cpu_side=system.cpu.icache_port
 494 mem_side=system.cpu.toL2Bus.slave[0]
 495
 496 [system.cpu.interrupts]
 497 type=ArmInterrupts
 498
 499 [system.cpu.isa]
 500 type=ArmISA
 501 fpsid=1090793632
 502 id_isar0=34607377
 503 id_isar1=34677009
 504 id_isar2=555950401
 505 id_isar3=17899825
 506 id_isar4=268501314
 507 id_isar5=0
 508 id_mmfr0=3
 509 id_mmfr1=0
 510 id_mmfr2=19070976
 511 id_mmfr3=4027589137
 512 id_pfr0=49
 513 id_pfr1=1
 514 midr=890224640
 515
 516 [system.cpu.itb]
 517 type=ArmTLB
 518 children=walker
 519 size=64
 520 walker=system.cpu.itb.walker
 521
 522 [system.cpu.itb.walker]
 523 type=ArmTableWalker
 524 clock=500
 525 num_squash_per_cycle=2
 526 sys=system
 527 port=system.cpu.toL2Bus.slave[2]
 528
 529 [system.cpu.l2cache]
 530 type=BaseCache
 531 addr_ranges=0:18446744073709551615
 532 assoc=8
 533 block_size=64
 534 clock=500
 535 forward_snoops=true
 536 hit_latency=20
 537 is_top_level=false
 538 max_miss_count=0
 539 mshrs=20
 540 prefetch_on_access=false
 541 prefetcher=Null
 542 response_latency=20
 543 size=4194304
 544 system=system
 545 tgts_per_mshr=12
 546 two_queue=false
 547 write_buffers=8
 548 cpu_side=system.cpu.toL2Bus.master[0]
 549 mem_side=system.membus.slave[1]
 550
 551 [system.cpu.toL2Bus]
 552 type=CoherentBus
 553 block_size=64
 554 clock=500
 555 header_cycles=1
 556 system=system
 557 use_default_range=false
 558 width=32
 559 master=system.cpu.l2cache.cpu_side
 560 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 561
 562 [system.cpu.tracer]
 563 type=ExeTracer
 564
 565 [system.intrctrl]
 566 type=IntrControl
 567 sys=system
 568
 569 [system.iobus]
 570 type=NoncoherentBus
 571 block_size=64
 572 clock=1000
 573 header_cycles=1
 574 use_default_range=false
 575 width=8
 576 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 577 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 578
 579 [system.iocache]
 580 type=BaseCache
 581 addr_ranges=0:134217727
 582 assoc=8
 583 block_size=64
 584 clock=1000
 585 forward_snoops=false
 586 hit_latency=50
 587 is_top_level=true
 588 max_miss_count=0
 589 mshrs=20
 590 prefetch_on_access=false
 591 prefetcher=Null
 592 response_latency=50
 593 size=1024
 594 system=system
 595 tgts_per_mshr=12
 596 two_queue=false
 597 write_buffers=8
 598 cpu_side=system.iobus.master[25]
 599 mem_side=system.membus.slave[2]
 600
 601 [system.membus]
 602 type=CoherentBus
 603 children=badaddr_responder
 604 block_size=64
 605 clock=1000
 606 header_cycles=1
 607 system=system
 608 use_default_range=false
 609 width=8
 610 default=system.membus.badaddr_responder.pio
 611 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 612 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 613
 614 [system.membus.badaddr_responder]
 615 type=IsaFake
 616 clock=1000
 617 fake_mem=false
 618 pio_addr=0
 619 pio_latency=100000
 620 pio_size=8
 621 ret_bad_addr=true
 622 ret_data16=65535
 623 ret_data32=4294967295
 624 ret_data64=18446744073709551615
 625 ret_data8=255
 626 system=system
 627 update_data=false
 628 warn_access=warn
 629 pio=system.membus.default
 630
 631 [system.physmem]
 632 type=SimpleDRAM
 633 activation_limit=4
 634 addr_mapping=openmap
 635 banks_per_rank=8
 636 channels=1
 637 clock=1000
 638 conf_table_reported=true
 639 in_addr_map=true
 640 lines_per_rowbuffer=32
 641 mem_sched_policy=frfcfs
 642 null=false
 643 page_policy=open
 644 range=0:134217727
 645 ranks_per_channel=2
 646 read_buffer_size=32
 647 tBURST=5000
 648 tCL=13750
 649 tRCD=13750
 650 tREFI=7800000
 651 tRFC=300000
 652 tRP=13750
 653 tWTR=7500
 654 tXAW=40000
 655 write_buffer_size=32
 656 write_thresh_perc=70
 657 zero=false
 658 port=system.membus.master[2]
 659
 660 [system.realview]
 661 type=RealView
 662 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 663 intrctrl=system.intrctrl
 664 max_mem_size=268435456
 665 mem_start_addr=0
 666 pci_cfg_base=0
 667 system=system
 668
 669 [system.realview.a9scu]
 670 type=A9SCU
 671 clock=1000
 672 pio_addr=520093696
 673 pio_latency=100000
 674 system=system
 675 pio=system.membus.master[5]
 676
 677 [system.realview.aaci_fake]
 678 type=AmbaFake
 679 amba_id=0
 680 clock=1000
 681 ignore_access=false
 682 pio_addr=268451840
 683 pio_latency=100000
 684 system=system
 685 pio=system.iobus.master[21]
 686
 687 [system.realview.cf_ctrl]
 688 type=IdeController
 689 BAR0=402653184
 690 BAR0LegacyIO=true
 691 BAR0Size=16
 692 BAR1=402653440
 693 BAR1LegacyIO=true
 694 BAR1Size=1
 695 BAR2=1
 696 BAR2LegacyIO=false
 697 BAR2Size=8
 698 BAR3=1
 699 BAR3LegacyIO=false
 700 BAR3Size=4
 701 BAR4=1
 702 BAR4LegacyIO=false
 703 BAR4Size=16
 704 BAR5=1
 705 BAR5LegacyIO=false
 706 BAR5Size=0
 707 BIST=0
 708 CacheLineSize=0
 709 CardbusCIS=0
 710 ClassCode=1
 711 Command=1
 712 DeviceID=28945
 713 ExpansionROM=0
 714 HeaderType=0
 715 InterruptLine=31
 716 InterruptPin=1
 717 LatencyTimer=0
 718 MaximumLatency=0
 719 MinimumGrant=0
 720 ProgIF=133
 721 Revision=0
 722 Status=640
 723 SubClassCode=1
 724 SubsystemID=0
 725 SubsystemVendorID=0
 726 VendorID=32902
 727 clock=1000
 728 config_latency=20000
 729 ctrl_offset=2
 730 disks=system.cf0
 731 io_shift=1
 732 pci_bus=2
 733 pci_dev=7
 734 pci_func=0
 735 pio_latency=30000
 736 platform=system.realview
 737 system=system
 738 config=system.iobus.master[8]
 739 dma=system.iobus.slave[2]
 740 pio=system.iobus.master[7]
 741
 742 [system.realview.clcd]
 743 type=Pl111
 744 amba_id=1315089
 745 clock=1000
 746 gic=system.realview.gic
 747 int_num=55
 748 pio_addr=268566528
 749 pio_latency=10000
 750 pixel_clock=41667
 751 system=system
 752 vnc=system.vncserver
 753 dma=system.iobus.slave[1]
 754 pio=system.iobus.master[4]
 755
 756 [system.realview.dmac_fake]
 757 type=AmbaFake
 758 amba_id=0
 759 clock=1000
 760 ignore_access=false
 761 pio_addr=268632064
 762 pio_latency=100000
 763 system=system
 764 pio=system.iobus.master[9]
 765
 766 [system.realview.flash_fake]
 767 type=IsaFake
 768 clock=1000
 769 fake_mem=true
 770 pio_addr=1073741824
 771 pio_latency=100000
 772 pio_size=536870912
 773 ret_bad_addr=false
 774 ret_data16=65535
 775 ret_data32=4294967295
 776 ret_data64=18446744073709551615
 777 ret_data8=255
 778 system=system
 779 update_data=false
 780 warn_access=
 781 pio=system.iobus.master[24]
 782
 783 [system.realview.gic]
 784 type=Pl390
 785 clock=1000
 786 cpu_addr=520093952
 787 cpu_pio_delay=10000
 788 dist_addr=520097792
 789 dist_pio_delay=10000
 790 int_latency=10000
 791 it_lines=128
 792 platform=system.realview
 793 system=system
 794 pio=system.membus.master[3]
 795
 796 [system.realview.gpio0_fake]
 797 type=AmbaFake
 798 amba_id=0
 799 clock=1000
 800 ignore_access=false
 801 pio_addr=268513280
 802 pio_latency=100000
 803 system=system
 804 pio=system.iobus.master[16]
 805
 806 [system.realview.gpio1_fake]
 807 type=AmbaFake
 808 amba_id=0
 809 clock=1000
 810 ignore_access=false
 811 pio_addr=268517376
 812 pio_latency=100000
 813 system=system
 814 pio=system.iobus.master[17]
 815
 816 [system.realview.gpio2_fake]
 817 type=AmbaFake
 818 amba_id=0
 819 clock=1000
 820 ignore_access=false
 821 pio_addr=268521472
 822 pio_latency=100000
 823 system=system
 824 pio=system.iobus.master[18]
 825
 826 [system.realview.kmi0]
 827 type=Pl050
 828 amba_id=1314896
 829 clock=1000
 830 gic=system.realview.gic
 831 int_delay=1000000
 832 int_num=52
 833 is_mouse=false
 834 pio_addr=268460032
 835 pio_latency=100000
 836 system=system
 837 vnc=system.vncserver
 838 pio=system.iobus.master[5]
 839
 840 [system.realview.kmi1]
 841 type=Pl050
 842 amba_id=1314896
 843 clock=1000
 844 gic=system.realview.gic
 845 int_delay=1000000
 846 int_num=53
 847 is_mouse=true
 848 pio_addr=268464128
 849 pio_latency=100000
 850 system=system
 851 vnc=system.vncserver
 852 pio=system.iobus.master[6]
 853
 854 [system.realview.l2x0_fake]
 855 type=IsaFake
 856 clock=1000
 857 fake_mem=false
 858 pio_addr=520101888
 859 pio_latency=100000
 860 pio_size=4095
 861 ret_bad_addr=false
 862 ret_data16=65535
 863 ret_data32=4294967295
 864 ret_data64=18446744073709551615
 865 ret_data8=255
 866 system=system
 867 update_data=false
 868 warn_access=
 869 pio=system.membus.master[4]
 870
 871 [system.realview.local_cpu_timer]
 872 type=CpuLocalTimer
 873 clock=1000
 874 gic=system.realview.gic
 875 int_num_timer=29
 876 int_num_watchdog=30
 877 pio_addr=520095232
 878 pio_latency=100000
 879 system=system
 880 pio=system.membus.master[6]
 881
 882 [system.realview.mmc_fake]
 883 type=AmbaFake
 884 amba_id=0
 885 clock=1000
 886 ignore_access=false
 887 pio_addr=268455936
 888 pio_latency=100000
 889 system=system
 890 pio=system.iobus.master[22]
 891
 892 [system.realview.nvmem]
 893 type=SimpleMemory
 894 bandwidth=73.000000
 895 clock=1000
 896 conf_table_reported=false
 897 in_addr_map=true
 898 latency=30000
 899 latency_var=0
 900 null=false
 901 range=2147483648:2214592511
 902 zero=true
 903 port=system.membus.master[1]
 904
 905 [system.realview.realview_io]
 906 type=RealViewCtrl
 907 clock=1000
 908 idreg=0
 909 pio_addr=268435456
 910 pio_latency=100000
 911 proc_id0=201326592
 912 proc_id1=201327138
 913 system=system
 914 pio=system.iobus.master[1]
 915
 916 [system.realview.rtc]
 917 type=PL031
 918 amba_id=3412017
 919 clock=1000
 920 gic=system.realview.gic
 921 int_delay=100000
 922 int_num=42
 923 pio_addr=268529664
 924 pio_latency=100000
 925 system=system
 926 time=Thu Jan  1 00:00:00 2009
 927 pio=system.iobus.master[23]
 928
 929 [system.realview.sci_fake]
 930 type=AmbaFake
 931 amba_id=0
 932 clock=1000
 933 ignore_access=false
 934 pio_addr=268492800
 935 pio_latency=100000
 936 system=system
 937 pio=system.iobus.master[20]
 938
 939 [system.realview.smc_fake]
 940 type=AmbaFake
 941 amba_id=0
 942 clock=1000
 943 ignore_access=false
 944 pio_addr=269357056
 945 pio_latency=100000
 946 system=system
 947 pio=system.iobus.master[13]
 948
 949 [system.realview.sp810_fake]
 950 type=AmbaFake
 951 amba_id=0
 952 clock=1000
 953 ignore_access=true
 954 pio_addr=268439552
 955 pio_latency=100000
 956 system=system
 957 pio=system.iobus.master[14]
 958
 959 [system.realview.ssp_fake]
 960 type=AmbaFake
 961 amba_id=0
 962 clock=1000
 963 ignore_access=false
 964 pio_addr=268488704
 965 pio_latency=100000
 966 system=system
 967 pio=system.iobus.master[19]
 968
 969 [system.realview.timer0]
 970 type=Sp804
 971 amba_id=1316868
 972 clock=1000
 973 clock0=1000000
 974 clock1=1000000
 975 gic=system.realview.gic
 976 int_num0=36
 977 int_num1=36
 978 pio_addr=268505088
 979 pio_latency=100000
 980 system=system
 981 pio=system.iobus.master[2]
 982
 983 [system.realview.timer1]
 984 type=Sp804
 985 amba_id=1316868
 986 clock=1000
 987 clock0=1000000
 988 clock1=1000000
 989 gic=system.realview.gic
 990 int_num0=37
 991 int_num1=37
 992 pio_addr=268509184
 993 pio_latency=100000
 994 system=system
 995 pio=system.iobus.master[3]
 996
 997 [system.realview.uart]
 998 type=Pl011
 999 clock=1000
1000 end_on_eot=false
1001 gic=system.realview.gic
1002 int_delay=100000
1003 int_num=44
1004 pio_addr=268472320
1005 pio_latency=100000
1006 platform=system.realview
1007 system=system
1008 terminal=system.terminal
1009 pio=system.iobus.master[0]
1010
1011 [system.realview.uart1_fake]
1012 type=AmbaFake
1013 amba_id=0
1014 clock=1000
1015 ignore_access=false
1016 pio_addr=268476416
1017 pio_latency=100000
1018 system=system
1019 pio=system.iobus.master[10]
1020
1021 [system.realview.uart2_fake]
1022 type=AmbaFake
1023 amba_id=0
1024 clock=1000
1025 ignore_access=false
1026 pio_addr=268480512
1027 pio_latency=100000
1028 system=system
1029 pio=system.iobus.master[11]
1030
1031 [system.realview.uart3_fake]
1032 type=AmbaFake
1033 amba_id=0
1034 clock=1000
1035 ignore_access=false
1036 pio_addr=268484608
1037 pio_latency=100000
1038 system=system
1039 pio=system.iobus.master[12]
1040
1041 [system.realview.watchdog_fake]
1042 type=AmbaFake
1043 amba_id=0
1044 clock=1000
1045 ignore_access=false
1046 pio_addr=268500992
1047 pio_latency=100000
1048 system=system
1049 pio=system.iobus.master[15]
1050
1051 [system.terminal]
1052 type=Terminal
1053 intr_control=system.intrctrl
1054 number=0
1055 output=true
1056 port=3456
1057
1058 [system.vncserver]
1059 type=VncServer
1060 frame_capture=false
1061 number=0
1062 port=5900
1063