8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
15 boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
23 exit_on_work_items=false
25 gic_cpu_addr=738205696
26 have_large_asid_64=false
29 have_virtualization=false
30 highest_el_is_64=false
32 kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
33 kernel_addr_check=true
34 load_addr_mask=268435455
35 load_offset=2147483648
36 machine_type=VExpress_EMM
38 mem_ranges=2147483648:2415919103
39 memories=system.physmem system.realview.nvmem system.realview.vram
40 mmap_using_noreserve=false
47 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
50 work_begin_ckpt_count=0
51 work_begin_cpu_id_exit=-1
52 work_begin_exit_count=0
53 work_cpus_ckpt_count=0
57 system_port=system.membus.slave[1]
61 clk_domain=system.clk_domain
64 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
67 master=system.iobus.slave[0]
68 slave=system.membus.master[0]
76 image=system.cf0.image
81 child=system.cf0.image.child
87 [system.cf0.image.child]
90 image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
99 voltage_domain=system.voltage_domain
103 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
112 branchPred=system.cpu.branchPred
115 clk_domain=system.cpu_clk_domain
116 commitToDecodeDelay=1
119 commitToRenameDelay=1
123 decodeToRenameDelay=2
126 do_checkpoint_insts=true
128 do_statistics_insts=true
129 dstage2_mmu=system.cpu.dstage2_mmu
138 fuPool=system.cpu.fuPool
140 function_trace_start=0
145 interrupts=system.cpu.interrupts
147 issueToExecuteDelay=1
149 istage2_mmu=system.cpu.istage2_mmu
151 max_insts_all_threads=0
152 max_insts_any_thread=0
153 max_loads_all_threads=0
154 max_loads_any_thread=0
165 renameToDecodeDelay=1
170 simpoint_start_insts=
171 smtCommitPolicy=RoundRobin
172 smtFetchPolicy=SingleThread
173 smtIQPolicy=Partitioned
175 smtLSQPolicy=Partitioned
177 smtNumFetchingThreads=1
178 smtROBPolicy=Partitioned
182 store_set_clear_period=250000
185 tracer=system.cpu.tracer
189 dcache_port=system.cpu.dcache.cpu_side
190 icache_port=system.cpu.icache.cpu_side
192 [system.cpu.branchPred]
198 choicePredictorSize=8192
201 globalPredictorSize=8192
208 addr_ranges=0:18446744073709551615
210 clk_domain=system.cpu_clk_domain
211 clusivity=mostly_incl
212 demand_mshr_reserve=1
218 prefetch_on_access=false
221 sequential_access=false
224 tags=system.cpu.dcache.tags
227 writeback_clean=false
228 cpu_side=system.cpu.dcache_port
229 mem_side=system.cpu.toL2Bus.slave[1]
231 [system.cpu.dcache.tags]
235 clk_domain=system.cpu_clk_domain
238 sequential_access=false
241 [system.cpu.dstage2_mmu]
245 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
249 [system.cpu.dstage2_mmu.stage2_tlb]
255 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
257 [system.cpu.dstage2_mmu.stage2_tlb.walker]
259 clk_domain=system.cpu_clk_domain
262 num_squash_per_cycle=2
271 walker=system.cpu.dtb.walker
273 [system.cpu.dtb.walker]
275 clk_domain=system.cpu_clk_domain
278 num_squash_per_cycle=2
280 port=system.cpu.toL2Bus.slave[3]
284 children=FUList0 FUList1 FUList2 FUList3 FUList4
285 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
288 [system.cpu.fuPool.FUList0]
293 opList=system.cpu.fuPool.FUList0.opList
295 [system.cpu.fuPool.FUList0.opList]
302 [system.cpu.fuPool.FUList1]
304 children=opList0 opList1 opList2
307 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
309 [system.cpu.fuPool.FUList1.opList0]
316 [system.cpu.fuPool.FUList1.opList1]
323 [system.cpu.fuPool.FUList1.opList2]
330 [system.cpu.fuPool.FUList2]
335 opList=system.cpu.fuPool.FUList2.opList
337 [system.cpu.fuPool.FUList2.opList]
344 [system.cpu.fuPool.FUList3]
349 opList=system.cpu.fuPool.FUList3.opList
351 [system.cpu.fuPool.FUList3.opList]
358 [system.cpu.fuPool.FUList4]
360 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
363 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
365 [system.cpu.fuPool.FUList4.opList00]
372 [system.cpu.fuPool.FUList4.opList01]
379 [system.cpu.fuPool.FUList4.opList02]
386 [system.cpu.fuPool.FUList4.opList03]
393 [system.cpu.fuPool.FUList4.opList04]
400 [system.cpu.fuPool.FUList4.opList05]
407 [system.cpu.fuPool.FUList4.opList06]
414 [system.cpu.fuPool.FUList4.opList07]
421 [system.cpu.fuPool.FUList4.opList08]
428 [system.cpu.fuPool.FUList4.opList09]
435 [system.cpu.fuPool.FUList4.opList10]
442 [system.cpu.fuPool.FUList4.opList11]
449 [system.cpu.fuPool.FUList4.opList12]
456 [system.cpu.fuPool.FUList4.opList13]
463 [system.cpu.fuPool.FUList4.opList14]
470 [system.cpu.fuPool.FUList4.opList15]
477 [system.cpu.fuPool.FUList4.opList16]
480 opClass=SimdFloatMisc
484 [system.cpu.fuPool.FUList4.opList17]
487 opClass=SimdFloatMult
491 [system.cpu.fuPool.FUList4.opList18]
494 opClass=SimdFloatMultAcc
498 [system.cpu.fuPool.FUList4.opList19]
501 opClass=SimdFloatSqrt
505 [system.cpu.fuPool.FUList4.opList20]
512 [system.cpu.fuPool.FUList4.opList21]
519 [system.cpu.fuPool.FUList4.opList22]
526 [system.cpu.fuPool.FUList4.opList23]
533 [system.cpu.fuPool.FUList4.opList24]
540 [system.cpu.fuPool.FUList4.opList25]
550 addr_ranges=0:18446744073709551615
552 clk_domain=system.cpu_clk_domain
553 clusivity=mostly_incl
554 demand_mshr_reserve=1
560 prefetch_on_access=false
563 sequential_access=false
566 tags=system.cpu.icache.tags
570 cpu_side=system.cpu.icache_port
571 mem_side=system.cpu.toL2Bus.slave[0]
573 [system.cpu.icache.tags]
577 clk_domain=system.cpu_clk_domain
580 sequential_access=false
583 [system.cpu.interrupts]
589 decoderFlavour=Generic
594 id_aa64dfr0_el1=1052678
598 id_aa64mmfr0_el1=15728642
618 [system.cpu.istage2_mmu]
622 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
626 [system.cpu.istage2_mmu.stage2_tlb]
632 walker=system.cpu.istage2_mmu.stage2_tlb.walker
634 [system.cpu.istage2_mmu.stage2_tlb.walker]
636 clk_domain=system.cpu_clk_domain
639 num_squash_per_cycle=2
648 walker=system.cpu.itb.walker
650 [system.cpu.itb.walker]
652 clk_domain=system.cpu_clk_domain
655 num_squash_per_cycle=2
657 port=system.cpu.toL2Bus.slave[2]
662 addr_ranges=0:18446744073709551615
664 clk_domain=system.cpu_clk_domain
665 clusivity=mostly_incl
666 demand_mshr_reserve=1
672 prefetch_on_access=false
675 sequential_access=false
678 tags=system.cpu.l2cache.tags
681 writeback_clean=false
682 cpu_side=system.cpu.toL2Bus.master[0]
683 mem_side=system.membus.slave[2]
685 [system.cpu.l2cache.tags]
689 clk_domain=system.cpu_clk_domain
692 sequential_access=false
697 children=snoop_filter
698 clk_domain=system.cpu_clk_domain
702 point_of_coherency=false
704 snoop_filter=system.cpu.toL2Bus.snoop_filter
705 snoop_response_latency=1
707 use_default_range=false
709 master=system.cpu.l2cache.cpu_side
710 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
712 [system.cpu.toL2Bus.snoop_filter]
723 [system.cpu_clk_domain]
729 voltage_domain=system.voltage_domain
731 [system.dvfs_handler]
736 sys_clk_domain=system.clk_domain
737 transition_latency=100000000
746 clk_domain=system.clk_domain
751 use_default_range=false
753 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
754 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
759 addr_ranges=2147483648:2415919103
761 clk_domain=system.clk_domain
762 clusivity=mostly_incl
763 demand_mshr_reserve=1
769 prefetch_on_access=false
772 sequential_access=false
775 tags=system.iocache.tags
778 writeback_clean=false
779 cpu_side=system.iobus.master[25]
780 mem_side=system.membus.slave[3]
782 [system.iocache.tags]
786 clk_domain=system.clk_domain
789 sequential_access=false
794 children=badaddr_responder
795 clk_domain=system.clk_domain
799 point_of_coherency=true
802 snoop_response_latency=4
804 use_default_range=false
806 default=system.membus.badaddr_responder.pio
807 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
808 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
810 [system.membus.badaddr_responder]
812 clk_domain=system.clk_domain
820 ret_data32=4294967295
821 ret_data64=18446744073709551615
826 pio=system.membus.default
855 addr_mapping=RoRaBaCoCh
856 bank_groups_per_rank=0
860 clk_domain=system.clk_domain
861 conf_table_reported=true
863 device_rowbuffer_size=1024
864 device_size=536870912
869 max_accesses_per_row=16
870 mem_sched_policy=frfcfs
871 min_writes_per_switch=16
873 page_policy=open_adaptive
874 range=2147483648:2415919103
877 static_backend_latency=10000
878 static_frontend_latency=10000
901 write_high_thresh_perc=85
902 write_low_thresh_perc=50
903 port=system.membus.master[5]
907 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
909 intrctrl=system.intrctrl
912 [system.realview.aaci_fake]
915 clk_domain=system.clk_domain
921 pio=system.iobus.master[18]
923 [system.realview.cf_ctrl]
963 MSICAPNextCapability=0
967 MSIXCAPNextCapability=0
977 PMCAPNextCapability=0
982 PXCAPDevCapabilities=0
989 PXCAPNextCapability=0
997 clk_domain=system.clk_domain
1002 host=system.realview.pci_host
1009 dma=system.iobus.slave[2]
1010 pio=system.iobus.master[9]
1012 [system.realview.clcd]
1015 clk_domain=system.clk_domain
1018 gic=system.realview.gic
1024 vnc=system.vncserver
1025 dma=system.iobus.slave[1]
1026 pio=system.iobus.master[5]
1028 [system.realview.dcc]
1030 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1033 [system.realview.dcc.osc_cpu]
1039 parent=system.realview.realview_io
1042 voltage_domain=system.voltage_domain
1044 [system.realview.dcc.osc_ddr]
1050 parent=system.realview.realview_io
1053 voltage_domain=system.voltage_domain
1055 [system.realview.dcc.osc_hsbm]
1061 parent=system.realview.realview_io
1064 voltage_domain=system.voltage_domain
1066 [system.realview.dcc.osc_pxl]
1072 parent=system.realview.realview_io
1075 voltage_domain=system.voltage_domain
1077 [system.realview.dcc.osc_smb]
1083 parent=system.realview.realview_io
1086 voltage_domain=system.voltage_domain
1088 [system.realview.dcc.osc_sys]
1094 parent=system.realview.realview_io
1097 voltage_domain=system.voltage_domain
1099 [system.realview.energy_ctrl]
1101 clk_domain=system.clk_domain
1102 dvfs_handler=system.dvfs_handler
1107 pio=system.iobus.master[22]
1109 [system.realview.ethernet]
1148 MSICAPMsgUpperAddr=0
1149 MSICAPNextCapability=0
1153 MSIXCAPNextCapability=0
1163 PMCAPNextCapability=0
1168 PXCAPDevCapabilities=0
1175 PXCAPNextCapability=0
1181 SubsystemVendorID=32902
1183 clk_domain=system.clk_domain
1184 config_latency=20000
1186 fetch_comp_delay=10000
1188 hardware_address=00:90:00:00:00:01
1189 host=system.realview.pci_host
1196 rx_desc_cache_size=64
1200 tx_desc_cache_size=64
1205 dma=system.iobus.slave[4]
1206 pio=system.iobus.master[24]
1208 [system.realview.generic_timer]
1211 gic=system.realview.gic
1216 [system.realview.gic]
1218 clk_domain=system.clk_domain
1222 dist_pio_delay=10000
1226 platform=system.realview
1228 pio=system.membus.master[2]
1230 [system.realview.hdlcd]
1233 clk_domain=system.clk_domain
1236 gic=system.realview.gic
1240 pixel_buffer_size=2048
1242 pxl_clk=system.realview.dcc.osc_pxl
1244 vnc=system.vncserver
1245 workaround_dma_line_count=true
1246 workaround_swap_rb=true
1247 dma=system.membus.slave[0]
1248 pio=system.iobus.master[6]
1250 [system.realview.ide]
1289 MSICAPMsgUpperAddr=0
1290 MSICAPNextCapability=0
1294 MSIXCAPNextCapability=0
1304 PMCAPNextCapability=0
1309 PXCAPDevCapabilities=0
1316 PXCAPNextCapability=0
1324 clk_domain=system.clk_domain
1325 config_latency=20000
1329 host=system.realview.pci_host
1336 dma=system.iobus.slave[3]
1337 pio=system.iobus.master[23]
1339 [system.realview.kmi0]
1342 clk_domain=system.clk_domain
1344 gic=system.realview.gic
1351 vnc=system.vncserver
1352 pio=system.iobus.master[7]
1354 [system.realview.kmi1]
1357 clk_domain=system.clk_domain
1359 gic=system.realview.gic
1366 vnc=system.vncserver
1367 pio=system.iobus.master[8]
1369 [system.realview.l2x0_fake]
1371 clk_domain=system.clk_domain
1379 ret_data32=4294967295
1380 ret_data64=18446744073709551615
1385 pio=system.iobus.master[12]
1387 [system.realview.lan_fake]
1389 clk_domain=system.clk_domain
1397 ret_data32=4294967295
1398 ret_data64=18446744073709551615
1403 pio=system.iobus.master[19]
1405 [system.realview.local_cpu_timer]
1407 clk_domain=system.clk_domain
1409 gic=system.realview.gic
1415 pio=system.membus.master[4]
1417 [system.realview.mcc]
1419 children=osc_clcd osc_mcc osc_peripheral osc_system_bus
1422 [system.realview.mcc.osc_clcd]
1428 parent=system.realview.realview_io
1431 voltage_domain=system.voltage_domain
1433 [system.realview.mcc.osc_mcc]
1439 parent=system.realview.realview_io
1442 voltage_domain=system.voltage_domain
1444 [system.realview.mcc.osc_peripheral]
1450 parent=system.realview.realview_io
1453 voltage_domain=system.voltage_domain
1455 [system.realview.mcc.osc_system_bus]
1461 parent=system.realview.realview_io
1464 voltage_domain=system.voltage_domain
1466 [system.realview.mmc_fake]
1469 clk_domain=system.clk_domain
1475 pio=system.iobus.master[21]
1477 [system.realview.nvmem]
1480 clk_domain=system.clk_domain
1481 conf_table_reported=false
1488 port=system.membus.master[1]
1490 [system.realview.pci_host]
1492 clk_domain=system.clk_domain
1500 platform=system.realview
1502 pio=system.iobus.master[2]
1504 [system.realview.realview_io]
1506 clk_domain=system.clk_domain
1514 pio=system.iobus.master[1]
1516 [system.realview.rtc]
1519 clk_domain=system.clk_domain
1521 gic=system.realview.gic
1527 time=Thu Jan 1 00:00:00 2009
1528 pio=system.iobus.master[10]
1530 [system.realview.sp810_fake]
1533 clk_domain=system.clk_domain
1539 pio=system.iobus.master[16]
1541 [system.realview.timer0]
1544 clk_domain=system.clk_domain
1548 gic=system.realview.gic
1554 pio=system.iobus.master[3]
1556 [system.realview.timer1]
1559 clk_domain=system.clk_domain
1563 gic=system.realview.gic
1569 pio=system.iobus.master[4]
1571 [system.realview.uart]
1573 clk_domain=system.clk_domain
1576 gic=system.realview.gic
1581 platform=system.realview
1583 terminal=system.terminal
1584 pio=system.iobus.master[0]
1586 [system.realview.uart1_fake]
1589 clk_domain=system.clk_domain
1595 pio=system.iobus.master[13]
1597 [system.realview.uart2_fake]
1600 clk_domain=system.clk_domain
1606 pio=system.iobus.master[14]
1608 [system.realview.uart3_fake]
1611 clk_domain=system.clk_domain
1617 pio=system.iobus.master[15]
1619 [system.realview.usb_fake]
1621 clk_domain=system.clk_domain
1629 ret_data32=4294967295
1630 ret_data64=18446744073709551615
1635 pio=system.iobus.master[20]
1637 [system.realview.vgic]
1639 clk_domain=system.clk_domain
1641 gic=system.realview.gic
1644 platform=system.realview
1648 pio=system.membus.master[3]
1650 [system.realview.vram]
1653 clk_domain=system.clk_domain
1654 conf_table_reported=false
1660 range=402653184:436207615
1661 port=system.iobus.master[11]
1663 [system.realview.watchdog_fake]
1666 clk_domain=system.clk_domain
1672 pio=system.iobus.master[17]
1677 intr_control=system.intrctrl
1689 [system.voltage_domain]