tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=0
  37 machine_type=RealView_PBX
  38 mem_mode=timing
  39 mem_ranges=0:134217727
  40 memories=system.physmem system.realview.nvmem
  41 multi_proc=true
  42 num_work_ids=16
  43 panic_on_oops=true
  44 panic_on_panic=true
  45 phys_addr_range_64=40
  46 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  47 reset_addr_64=0
  48 symbolfile=
  49 work_begin_ckpt_count=0
  50 work_begin_cpu_id_exit=-1
  51 work_begin_exit_count=0
  52 work_cpus_ckpt_count=0
  53 work_end_ckpt_count=0
  54 work_end_exit_count=0
  55 work_item_id=-1
  56 system_port=system.membus.slave[0]
  57
  58 [system.bridge]
  59 type=Bridge
  60 clk_domain=system.clk_domain
  61 delay=50000
  62 eventq_index=0
  63 ranges=268435456:520093695 1073741824:1610612735
  64 req_size=16
  65 resp_size=16
  66 master=system.iobus.slave[0]
  67 slave=system.membus.master[0]
  68
  69 [system.cf0]
  70 type=IdeDisk
  71 children=image
  72 delay=1000000
  73 driveID=master
  74 eventq_index=0
  75 image=system.cf0.image
  76
  77 [system.cf0.image]
  78 type=CowDiskImage
  79 children=child
  80 child=system.cf0.image.child
  81 eventq_index=0
  82 image_file=
  83 read_only=false
  84 table_size=65536
  85
  86 [system.cf0.image.child]
  87 type=RawDiskImage
  88 eventq_index=0
  89 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  90 read_only=true
  91
  92 [system.clk_domain]
  93 type=SrcClockDomain
  94 clock=1000
  95 domain_id=-1
  96 eventq_index=0
  97 init_perf_level=0
  98 voltage_domain=system.voltage_domain
  99
 100 [system.cpu]
 101 type=DerivO3CPU
 102 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 103 LFSTSize=1024
 104 LQEntries=32
 105 LSQCheckLoads=true
 106 LSQDepCheckShift=4
 107 SQEntries=32
 108 SSITSize=1024
 109 activity=0
 110 backComSize=5
 111 branchPred=system.cpu.branchPred
 112 cachePorts=200
 113 checker=Null
 114 clk_domain=system.cpu_clk_domain
 115 commitToDecodeDelay=1
 116 commitToFetchDelay=1
 117 commitToIEWDelay=1
 118 commitToRenameDelay=1
 119 commitWidth=8
 120 cpu_id=0
 121 decodeToFetchDelay=1
 122 decodeToRenameDelay=1
 123 decodeWidth=8
 124 dispatchWidth=8
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu.dstage2_mmu
 129 dtb=system.cpu.dtb
 130 eventq_index=0
 131 fetchBufferSize=64
 132 fetchToDecodeDelay=1
 133 fetchTrapLatency=1
 134 fetchWidth=8
 135 forwardComSize=5
 136 fuPool=system.cpu.fuPool
 137 function_trace=false
 138 function_trace_start=0
 139 iewToCommitDelay=1
 140 iewToDecodeDelay=1
 141 iewToFetchDelay=1
 142 iewToRenameDelay=1
 143 interrupts=system.cpu.interrupts
 144 isa=system.cpu.isa
 145 issueToExecuteDelay=1
 146 issueWidth=8
 147 istage2_mmu=system.cpu.istage2_mmu
 148 itb=system.cpu.itb
 149 max_insts_all_threads=0
 150 max_insts_any_thread=0
 151 max_loads_all_threads=0
 152 max_loads_any_thread=0
 153 needsTSO=false
 154 numIQEntries=64
 155 numPhysCCRegs=0
 156 numPhysFloatRegs=256
 157 numPhysIntRegs=256
 158 numROBEntries=192
 159 numRobs=1
 160 numThreads=1
 161 profile=0
 162 progress_interval=0
 163 renameToDecodeDelay=1
 164 renameToFetchDelay=1
 165 renameToIEWDelay=2
 166 renameToROBDelay=1
 167 renameWidth=8
 168 simpoint_start_insts=
 169 smtCommitPolicy=RoundRobin
 170 smtFetchPolicy=SingleThread
 171 smtIQPolicy=Partitioned
 172 smtIQThreshold=100
 173 smtLSQPolicy=Partitioned
 174 smtLSQThreshold=100
 175 smtNumFetchingThreads=1
 176 smtROBPolicy=Partitioned
 177 smtROBThreshold=100
 178 socket_id=0
 179 squashWidth=8
 180 store_set_clear_period=250000
 181 switched_out=false
 182 system=system
 183 tracer=system.cpu.tracer
 184 trapLatency=13
 185 wbDepth=1
 186 wbWidth=8
 187 workload=
 188 dcache_port=system.cpu.dcache.cpu_side
 189 icache_port=system.cpu.icache.cpu_side
 190
 191 [system.cpu.branchPred]
 192 type=BranchPredictor
 193 BTBEntries=4096
 194 BTBTagSize=16
 195 RASSize=16
 196 choiceCtrBits=2
 197 choicePredictorSize=8192
 198 eventq_index=0
 199 globalCtrBits=2
 200 globalPredictorSize=8192
 201 instShiftAmt=2
 202 localCtrBits=2
 203 localHistoryTableSize=2048
 204 localPredictorSize=2048
 205 numThreads=1
 206 predType=tournament
 207
 208 [system.cpu.dcache]
 209 type=BaseCache
 210 children=tags
 211 addr_ranges=0:18446744073709551615
 212 assoc=4
 213 clk_domain=system.cpu_clk_domain
 214 eventq_index=0
 215 forward_snoops=true
 216 hit_latency=2
 217 is_top_level=true
 218 max_miss_count=0
 219 mshrs=4
 220 prefetch_on_access=false
 221 prefetcher=Null
 222 response_latency=2
 223 sequential_access=false
 224 size=32768
 225 system=system
 226 tags=system.cpu.dcache.tags
 227 tgts_per_mshr=20
 228 two_queue=false
 229 write_buffers=8
 230 cpu_side=system.cpu.dcache_port
 231 mem_side=system.cpu.toL2Bus.slave[1]
 232
 233 [system.cpu.dcache.tags]
 234 type=LRU
 235 assoc=4
 236 block_size=64
 237 clk_domain=system.cpu_clk_domain
 238 eventq_index=0
 239 hit_latency=2
 240 sequential_access=false
 241 size=32768
 242
 243 [system.cpu.dstage2_mmu]
 244 type=ArmStage2MMU
 245 children=stage2_tlb
 246 eventq_index=0
 247 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 248 tlb=system.cpu.dtb
 249
 250 [system.cpu.dstage2_mmu.stage2_tlb]
 251 type=ArmTLB
 252 children=walker
 253 eventq_index=0
 254 is_stage2=true
 255 size=32
 256 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 257
 258 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 259 type=ArmTableWalker
 260 clk_domain=system.cpu_clk_domain
 261 eventq_index=0
 262 is_stage2=true
 263 num_squash_per_cycle=2
 264 sys=system
 265 port=system.cpu.toL2Bus.slave[5]
 266
 267 [system.cpu.dtb]
 268 type=ArmTLB
 269 children=walker
 270 eventq_index=0
 271 is_stage2=false
 272 size=64
 273 walker=system.cpu.dtb.walker
 274
 275 [system.cpu.dtb.walker]
 276 type=ArmTableWalker
 277 clk_domain=system.cpu_clk_domain
 278 eventq_index=0
 279 is_stage2=false
 280 num_squash_per_cycle=2
 281 sys=system
 282 port=system.cpu.toL2Bus.slave[3]
 283
 284 [system.cpu.fuPool]
 285 type=FUPool
 286 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 287 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 288 eventq_index=0
 289
 290 [system.cpu.fuPool.FUList0]
 291 type=FUDesc
 292 children=opList
 293 count=6
 294 eventq_index=0
 295 opList=system.cpu.fuPool.FUList0.opList
 296
 297 [system.cpu.fuPool.FUList0.opList]
 298 type=OpDesc
 299 eventq_index=0
 300 issueLat=1
 301 opClass=IntAlu
 302 opLat=1
 303
 304 [system.cpu.fuPool.FUList1]
 305 type=FUDesc
 306 children=opList0 opList1
 307 count=2
 308 eventq_index=0
 309 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 310
 311 [system.cpu.fuPool.FUList1.opList0]
 312 type=OpDesc
 313 eventq_index=0
 314 issueLat=1
 315 opClass=IntMult
 316 opLat=3
 317
 318 [system.cpu.fuPool.FUList1.opList1]
 319 type=OpDesc
 320 eventq_index=0
 321 issueLat=19
 322 opClass=IntDiv
 323 opLat=20
 324
 325 [system.cpu.fuPool.FUList2]
 326 type=FUDesc
 327 children=opList0 opList1 opList2
 328 count=4
 329 eventq_index=0
 330 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 331
 332 [system.cpu.fuPool.FUList2.opList0]
 333 type=OpDesc
 334 eventq_index=0
 335 issueLat=1
 336 opClass=FloatAdd
 337 opLat=2
 338
 339 [system.cpu.fuPool.FUList2.opList1]
 340 type=OpDesc
 341 eventq_index=0
 342 issueLat=1
 343 opClass=FloatCmp
 344 opLat=2
 345
 346 [system.cpu.fuPool.FUList2.opList2]
 347 type=OpDesc
 348 eventq_index=0
 349 issueLat=1
 350 opClass=FloatCvt
 351 opLat=2
 352
 353 [system.cpu.fuPool.FUList3]
 354 type=FUDesc
 355 children=opList0 opList1 opList2
 356 count=2
 357 eventq_index=0
 358 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 359
 360 [system.cpu.fuPool.FUList3.opList0]
 361 type=OpDesc
 362 eventq_index=0
 363 issueLat=1
 364 opClass=FloatMult
 365 opLat=4
 366
 367 [system.cpu.fuPool.FUList3.opList1]
 368 type=OpDesc
 369 eventq_index=0
 370 issueLat=12
 371 opClass=FloatDiv
 372 opLat=12
 373
 374 [system.cpu.fuPool.FUList3.opList2]
 375 type=OpDesc
 376 eventq_index=0
 377 issueLat=24
 378 opClass=FloatSqrt
 379 opLat=24
 380
 381 [system.cpu.fuPool.FUList4]
 382 type=FUDesc
 383 children=opList
 384 count=0
 385 eventq_index=0
 386 opList=system.cpu.fuPool.FUList4.opList
 387
 388 [system.cpu.fuPool.FUList4.opList]
 389 type=OpDesc
 390 eventq_index=0
 391 issueLat=1
 392 opClass=MemRead
 393 opLat=1
 394
 395 [system.cpu.fuPool.FUList5]
 396 type=FUDesc
 397 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 398 count=4
 399 eventq_index=0
 400 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 401
 402 [system.cpu.fuPool.FUList5.opList00]
 403 type=OpDesc
 404 eventq_index=0
 405 issueLat=1
 406 opClass=SimdAdd
 407 opLat=1
 408
 409 [system.cpu.fuPool.FUList5.opList01]
 410 type=OpDesc
 411 eventq_index=0
 412 issueLat=1
 413 opClass=SimdAddAcc
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList5.opList02]
 417 type=OpDesc
 418 eventq_index=0
 419 issueLat=1
 420 opClass=SimdAlu
 421 opLat=1
 422
 423 [system.cpu.fuPool.FUList5.opList03]
 424 type=OpDesc
 425 eventq_index=0
 426 issueLat=1
 427 opClass=SimdCmp
 428 opLat=1
 429
 430 [system.cpu.fuPool.FUList5.opList04]
 431 type=OpDesc
 432 eventq_index=0
 433 issueLat=1
 434 opClass=SimdCvt
 435 opLat=1
 436
 437 [system.cpu.fuPool.FUList5.opList05]
 438 type=OpDesc
 439 eventq_index=0
 440 issueLat=1
 441 opClass=SimdMisc
 442 opLat=1
 443
 444 [system.cpu.fuPool.FUList5.opList06]
 445 type=OpDesc
 446 eventq_index=0
 447 issueLat=1
 448 opClass=SimdMult
 449 opLat=1
 450
 451 [system.cpu.fuPool.FUList5.opList07]
 452 type=OpDesc
 453 eventq_index=0
 454 issueLat=1
 455 opClass=SimdMultAcc
 456 opLat=1
 457
 458 [system.cpu.fuPool.FUList5.opList08]
 459 type=OpDesc
 460 eventq_index=0
 461 issueLat=1
 462 opClass=SimdShift
 463 opLat=1
 464
 465 [system.cpu.fuPool.FUList5.opList09]
 466 type=OpDesc
 467 eventq_index=0
 468 issueLat=1
 469 opClass=SimdShiftAcc
 470 opLat=1
 471
 472 [system.cpu.fuPool.FUList5.opList10]
 473 type=OpDesc
 474 eventq_index=0
 475 issueLat=1
 476 opClass=SimdSqrt
 477 opLat=1
 478
 479 [system.cpu.fuPool.FUList5.opList11]
 480 type=OpDesc
 481 eventq_index=0
 482 issueLat=1
 483 opClass=SimdFloatAdd
 484 opLat=1
 485
 486 [system.cpu.fuPool.FUList5.opList12]
 487 type=OpDesc
 488 eventq_index=0
 489 issueLat=1
 490 opClass=SimdFloatAlu
 491 opLat=1
 492
 493 [system.cpu.fuPool.FUList5.opList13]
 494 type=OpDesc
 495 eventq_index=0
 496 issueLat=1
 497 opClass=SimdFloatCmp
 498 opLat=1
 499
 500 [system.cpu.fuPool.FUList5.opList14]
 501 type=OpDesc
 502 eventq_index=0
 503 issueLat=1
 504 opClass=SimdFloatCvt
 505 opLat=1
 506
 507 [system.cpu.fuPool.FUList5.opList15]
 508 type=OpDesc
 509 eventq_index=0
 510 issueLat=1
 511 opClass=SimdFloatDiv
 512 opLat=1
 513
 514 [system.cpu.fuPool.FUList5.opList16]
 515 type=OpDesc
 516 eventq_index=0
 517 issueLat=1
 518 opClass=SimdFloatMisc
 519 opLat=1
 520
 521 [system.cpu.fuPool.FUList5.opList17]
 522 type=OpDesc
 523 eventq_index=0
 524 issueLat=1
 525 opClass=SimdFloatMult
 526 opLat=1
 527
 528 [system.cpu.fuPool.FUList5.opList18]
 529 type=OpDesc
 530 eventq_index=0
 531 issueLat=1
 532 opClass=SimdFloatMultAcc
 533 opLat=1
 534
 535 [system.cpu.fuPool.FUList5.opList19]
 536 type=OpDesc
 537 eventq_index=0
 538 issueLat=1
 539 opClass=SimdFloatSqrt
 540 opLat=1
 541
 542 [system.cpu.fuPool.FUList6]
 543 type=FUDesc
 544 children=opList
 545 count=0
 546 eventq_index=0
 547 opList=system.cpu.fuPool.FUList6.opList
 548
 549 [system.cpu.fuPool.FUList6.opList]
 550 type=OpDesc
 551 eventq_index=0
 552 issueLat=1
 553 opClass=MemWrite
 554 opLat=1
 555
 556 [system.cpu.fuPool.FUList7]
 557 type=FUDesc
 558 children=opList0 opList1
 559 count=4
 560 eventq_index=0
 561 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 562
 563 [system.cpu.fuPool.FUList7.opList0]
 564 type=OpDesc
 565 eventq_index=0
 566 issueLat=1
 567 opClass=MemRead
 568 opLat=1
 569
 570 [system.cpu.fuPool.FUList7.opList1]
 571 type=OpDesc
 572 eventq_index=0
 573 issueLat=1
 574 opClass=MemWrite
 575 opLat=1
 576
 577 [system.cpu.fuPool.FUList8]
 578 type=FUDesc
 579 children=opList
 580 count=1
 581 eventq_index=0
 582 opList=system.cpu.fuPool.FUList8.opList
 583
 584 [system.cpu.fuPool.FUList8.opList]
 585 type=OpDesc
 586 eventq_index=0
 587 issueLat=3
 588 opClass=IprAccess
 589 opLat=3
 590
 591 [system.cpu.icache]
 592 type=BaseCache
 593 children=tags
 594 addr_ranges=0:18446744073709551615
 595 assoc=1
 596 clk_domain=system.cpu_clk_domain
 597 eventq_index=0
 598 forward_snoops=true
 599 hit_latency=2
 600 is_top_level=true
 601 max_miss_count=0
 602 mshrs=4
 603 prefetch_on_access=false
 604 prefetcher=Null
 605 response_latency=2
 606 sequential_access=false
 607 size=32768
 608 system=system
 609 tags=system.cpu.icache.tags
 610 tgts_per_mshr=20
 611 two_queue=false
 612 write_buffers=8
 613 cpu_side=system.cpu.icache_port
 614 mem_side=system.cpu.toL2Bus.slave[0]
 615
 616 [system.cpu.icache.tags]
 617 type=LRU
 618 assoc=1
 619 block_size=64
 620 clk_domain=system.cpu_clk_domain
 621 eventq_index=0
 622 hit_latency=2
 623 sequential_access=false
 624 size=32768
 625
 626 [system.cpu.interrupts]
 627 type=ArmInterrupts
 628 eventq_index=0
 629
 630 [system.cpu.isa]
 631 type=ArmISA
 632 eventq_index=0
 633 fpsid=1090793632
 634 id_aa64afr0_el1=0
 635 id_aa64afr1_el1=0
 636 id_aa64dfr0_el1=1052678
 637 id_aa64dfr1_el1=0
 638 id_aa64isar0_el1=0
 639 id_aa64isar1_el1=0
 640 id_aa64mmfr0_el1=15728642
 641 id_aa64mmfr1_el1=0
 642 id_aa64pfr0_el1=17
 643 id_aa64pfr1_el1=0
 644 id_isar0=34607377
 645 id_isar1=34677009
 646 id_isar2=555950401
 647 id_isar3=17899825
 648 id_isar4=268501314
 649 id_isar5=0
 650 id_mmfr0=270536963
 651 id_mmfr1=0
 652 id_mmfr2=19070976
 653 id_mmfr3=34611729
 654 id_pfr0=49
 655 id_pfr1=4113
 656 midr=1091551472
 657 system=system
 658
 659 [system.cpu.istage2_mmu]
 660 type=ArmStage2MMU
 661 children=stage2_tlb
 662 eventq_index=0
 663 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 664 tlb=system.cpu.itb
 665
 666 [system.cpu.istage2_mmu.stage2_tlb]
 667 type=ArmTLB
 668 children=walker
 669 eventq_index=0
 670 is_stage2=true
 671 size=32
 672 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 673
 674 [system.cpu.istage2_mmu.stage2_tlb.walker]
 675 type=ArmTableWalker
 676 clk_domain=system.cpu_clk_domain
 677 eventq_index=0
 678 is_stage2=true
 679 num_squash_per_cycle=2
 680 sys=system
 681 port=system.cpu.toL2Bus.slave[4]
 682
 683 [system.cpu.itb]
 684 type=ArmTLB
 685 children=walker
 686 eventq_index=0
 687 is_stage2=false
 688 size=64
 689 walker=system.cpu.itb.walker
 690
 691 [system.cpu.itb.walker]
 692 type=ArmTableWalker
 693 clk_domain=system.cpu_clk_domain
 694 eventq_index=0
 695 is_stage2=false
 696 num_squash_per_cycle=2
 697 sys=system
 698 port=system.cpu.toL2Bus.slave[2]
 699
 700 [system.cpu.l2cache]
 701 type=BaseCache
 702 children=tags
 703 addr_ranges=0:18446744073709551615
 704 assoc=8
 705 clk_domain=system.cpu_clk_domain
 706 eventq_index=0
 707 forward_snoops=true
 708 hit_latency=20
 709 is_top_level=false
 710 max_miss_count=0
 711 mshrs=20
 712 prefetch_on_access=false
 713 prefetcher=Null
 714 response_latency=20
 715 sequential_access=false
 716 size=4194304
 717 system=system
 718 tags=system.cpu.l2cache.tags
 719 tgts_per_mshr=12
 720 two_queue=false
 721 write_buffers=8
 722 cpu_side=system.cpu.toL2Bus.master[0]
 723 mem_side=system.membus.slave[1]
 724
 725 [system.cpu.l2cache.tags]
 726 type=LRU
 727 assoc=8
 728 block_size=64
 729 clk_domain=system.cpu_clk_domain
 730 eventq_index=0
 731 hit_latency=20
 732 sequential_access=false
 733 size=4194304
 734
 735 [system.cpu.toL2Bus]
 736 type=CoherentBus
 737 clk_domain=system.cpu_clk_domain
 738 eventq_index=0
 739 header_cycles=1
 740 system=system
 741 use_default_range=false
 742 width=32
 743 master=system.cpu.l2cache.cpu_side
 744 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 745
 746 [system.cpu.tracer]
 747 type=ExeTracer
 748 eventq_index=0
 749
 750 [system.cpu_clk_domain]
 751 type=SrcClockDomain
 752 clock=500
 753 domain_id=-1
 754 eventq_index=0
 755 init_perf_level=0
 756 voltage_domain=system.voltage_domain
 757
 758 [system.dvfs_handler]
 759 type=DVFSHandler
 760 domains=
 761 enable=false
 762 eventq_index=0
 763 sys_clk_domain=system.clk_domain
 764 transition_latency=100000000
 765
 766 [system.intrctrl]
 767 type=IntrControl
 768 eventq_index=0
 769 sys=system
 770
 771 [system.iobus]
 772 type=NoncoherentBus
 773 clk_domain=system.clk_domain
 774 eventq_index=0
 775 header_cycles=1
 776 use_default_range=false
 777 width=8
 778 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 779 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 780
 781 [system.iocache]
 782 type=BaseCache
 783 children=tags
 784 addr_ranges=0:134217727
 785 assoc=8
 786 clk_domain=system.clk_domain
 787 eventq_index=0
 788 forward_snoops=false
 789 hit_latency=50
 790 is_top_level=true
 791 max_miss_count=0
 792 mshrs=20
 793 prefetch_on_access=false
 794 prefetcher=Null
 795 response_latency=50
 796 sequential_access=false
 797 size=1024
 798 system=system
 799 tags=system.iocache.tags
 800 tgts_per_mshr=12
 801 two_queue=false
 802 write_buffers=8
 803 cpu_side=system.iobus.master[25]
 804 mem_side=system.membus.slave[2]
 805
 806 [system.iocache.tags]
 807 type=LRU
 808 assoc=8
 809 block_size=64
 810 clk_domain=system.clk_domain
 811 eventq_index=0
 812 hit_latency=50
 813 sequential_access=false
 814 size=1024
 815
 816 [system.membus]
 817 type=CoherentBus
 818 children=badaddr_responder
 819 clk_domain=system.clk_domain
 820 eventq_index=0
 821 header_cycles=1
 822 system=system
 823 use_default_range=false
 824 width=8
 825 default=system.membus.badaddr_responder.pio
 826 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 827 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 828
 829 [system.membus.badaddr_responder]
 830 type=IsaFake
 831 clk_domain=system.clk_domain
 832 eventq_index=0
 833 fake_mem=false
 834 pio_addr=0
 835 pio_latency=100000
 836 pio_size=8
 837 ret_bad_addr=true
 838 ret_data16=65535
 839 ret_data32=4294967295
 840 ret_data64=18446744073709551615
 841 ret_data8=255
 842 system=system
 843 update_data=false
 844 warn_access=warn
 845 pio=system.membus.default
 846
 847 [system.physmem]
 848 type=DRAMCtrl
 849 activation_limit=4
 850 addr_mapping=RoRaBaChCo
 851 banks_per_rank=8
 852 burst_length=8
 853 channels=1
 854 clk_domain=system.clk_domain
 855 conf_table_reported=true
 856 device_bus_width=8
 857 device_rowbuffer_size=1024
 858 devices_per_rank=8
 859 eventq_index=0
 860 in_addr_map=true
 861 max_accesses_per_row=16
 862 mem_sched_policy=frfcfs
 863 min_writes_per_switch=16
 864 null=false
 865 page_policy=open_adaptive
 866 range=0:134217727
 867 ranks_per_channel=2
 868 read_buffer_size=32
 869 static_backend_latency=10000
 870 static_frontend_latency=10000
 871 tBURST=5000
 872 tCK=1250
 873 tCL=13750
 874 tRAS=35000
 875 tRCD=13750
 876 tREFI=7800000
 877 tRFC=260000
 878 tRP=13750
 879 tRRD=6000
 880 tRTP=7500
 881 tRTW=2500
 882 tWR=15000
 883 tWTR=7500
 884 tXAW=30000
 885 write_buffer_size=64
 886 write_high_thresh_perc=85
 887 write_low_thresh_perc=50
 888 port=system.membus.master[6]
 889
 890 [system.realview]
 891 type=RealView
 892 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 893 eventq_index=0
 894 intrctrl=system.intrctrl
 895 max_mem_size=268435456
 896 mem_start_addr=0
 897 pci_cfg_base=0
 898 system=system
 899
 900 [system.realview.a9scu]
 901 type=A9SCU
 902 clk_domain=system.clk_domain
 903 eventq_index=0
 904 pio_addr=520093696
 905 pio_latency=100000
 906 system=system
 907 pio=system.membus.master[4]
 908
 909 [system.realview.aaci_fake]
 910 type=AmbaFake
 911 amba_id=0
 912 clk_domain=system.clk_domain
 913 eventq_index=0
 914 ignore_access=false
 915 pio_addr=268451840
 916 pio_latency=100000
 917 system=system
 918 pio=system.iobus.master[21]
 919
 920 [system.realview.cf_ctrl]
 921 type=IdeController
 922 BAR0=402653184
 923 BAR0LegacyIO=true
 924 BAR0Size=16
 925 BAR1=402653440
 926 BAR1LegacyIO=true
 927 BAR1Size=1
 928 BAR2=1
 929 BAR2LegacyIO=false
 930 BAR2Size=8
 931 BAR3=1
 932 BAR3LegacyIO=false
 933 BAR3Size=4
 934 BAR4=1
 935 BAR4LegacyIO=false
 936 BAR4Size=16
 937 BAR5=1
 938 BAR5LegacyIO=false
 939 BAR5Size=0
 940 BIST=0
 941 CacheLineSize=0
 942 CapabilityPtr=0
 943 CardbusCIS=0
 944 ClassCode=1
 945 Command=1
 946 DeviceID=28945
 947 ExpansionROM=0
 948 HeaderType=0
 949 InterruptLine=31
 950 InterruptPin=1
 951 LatencyTimer=0
 952 MSICAPBaseOffset=0
 953 MSICAPCapId=0
 954 MSICAPMaskBits=0
 955 MSICAPMsgAddr=0
 956 MSICAPMsgCtrl=0
 957 MSICAPMsgData=0
 958 MSICAPMsgUpperAddr=0
 959 MSICAPNextCapability=0
 960 MSICAPPendingBits=0
 961 MSIXCAPBaseOffset=0
 962 MSIXCAPCapId=0
 963 MSIXCAPNextCapability=0
 964 MSIXMsgCtrl=0
 965 MSIXPbaOffset=0
 966 MSIXTableOffset=0
 967 MaximumLatency=0
 968 MinimumGrant=0
 969 PMCAPBaseOffset=0
 970 PMCAPCapId=0
 971 PMCAPCapabilities=0
 972 PMCAPCtrlStatus=0
 973 PMCAPNextCapability=0
 974 PXCAPBaseOffset=0
 975 PXCAPCapId=0
 976 PXCAPCapabilities=0
 977 PXCAPDevCap2=0
 978 PXCAPDevCapabilities=0
 979 PXCAPDevCtrl=0
 980 PXCAPDevCtrl2=0
 981 PXCAPDevStatus=0
 982 PXCAPLinkCap=0
 983 PXCAPLinkCtrl=0
 984 PXCAPLinkStatus=0
 985 PXCAPNextCapability=0
 986 ProgIF=133
 987 Revision=0
 988 Status=640
 989 SubClassCode=1
 990 SubsystemID=0
 991 SubsystemVendorID=0
 992 VendorID=32902
 993 clk_domain=system.clk_domain
 994 config_latency=20000
 995 ctrl_offset=2
 996 disks=system.cf0
 997 eventq_index=0
 998 io_shift=1
 999 pci_bus=2
1000 pci_dev=7
1001 pci_func=0
1002 pio_latency=30000
1003 platform=system.realview
1004 system=system
1005 config=system.iobus.master[8]
1006 dma=system.iobus.slave[2]
1007 pio=system.iobus.master[7]
1008
1009 [system.realview.clcd]
1010 type=Pl111
1011 amba_id=1315089
1012 clk_domain=system.clk_domain
1013 enable_capture=true
1014 eventq_index=0
1015 gic=system.realview.gic
1016 int_num=55
1017 pio_addr=268566528
1018 pio_latency=10000
1019 pixel_clock=41667
1020 system=system
1021 vnc=system.vncserver
1022 dma=system.iobus.slave[1]
1023 pio=system.iobus.master[4]
1024
1025 [system.realview.dmac_fake]
1026 type=AmbaFake
1027 amba_id=0
1028 clk_domain=system.clk_domain
1029 eventq_index=0
1030 ignore_access=false
1031 pio_addr=268632064
1032 pio_latency=100000
1033 system=system
1034 pio=system.iobus.master[9]
1035
1036 [system.realview.flash_fake]
1037 type=IsaFake
1038 clk_domain=system.clk_domain
1039 eventq_index=0
1040 fake_mem=true
1041 pio_addr=1073741824
1042 pio_latency=100000
1043 pio_size=536870912
1044 ret_bad_addr=false
1045 ret_data16=65535
1046 ret_data32=4294967295
1047 ret_data64=18446744073709551615
1048 ret_data8=255
1049 system=system
1050 update_data=false
1051 warn_access=
1052 pio=system.iobus.master[24]
1053
1054 [system.realview.gic]
1055 type=Pl390
1056 clk_domain=system.clk_domain
1057 cpu_addr=520093952
1058 cpu_pio_delay=10000
1059 dist_addr=520097792
1060 dist_pio_delay=10000
1061 eventq_index=0
1062 int_latency=10000
1063 it_lines=128
1064 msix_addr=0
1065 platform=system.realview
1066 system=system
1067 pio=system.membus.master[2]
1068
1069 [system.realview.gpio0_fake]
1070 type=AmbaFake
1071 amba_id=0
1072 clk_domain=system.clk_domain
1073 eventq_index=0
1074 ignore_access=false
1075 pio_addr=268513280
1076 pio_latency=100000
1077 system=system
1078 pio=system.iobus.master[16]
1079
1080 [system.realview.gpio1_fake]
1081 type=AmbaFake
1082 amba_id=0
1083 clk_domain=system.clk_domain
1084 eventq_index=0
1085 ignore_access=false
1086 pio_addr=268517376
1087 pio_latency=100000
1088 system=system
1089 pio=system.iobus.master[17]
1090
1091 [system.realview.gpio2_fake]
1092 type=AmbaFake
1093 amba_id=0
1094 clk_domain=system.clk_domain
1095 eventq_index=0
1096 ignore_access=false
1097 pio_addr=268521472
1098 pio_latency=100000
1099 system=system
1100 pio=system.iobus.master[18]
1101
1102 [system.realview.kmi0]
1103 type=Pl050
1104 amba_id=1314896
1105 clk_domain=system.clk_domain
1106 eventq_index=0
1107 gic=system.realview.gic
1108 int_delay=1000000
1109 int_num=52
1110 is_mouse=false
1111 pio_addr=268460032
1112 pio_latency=100000
1113 system=system
1114 vnc=system.vncserver
1115 pio=system.iobus.master[5]
1116
1117 [system.realview.kmi1]
1118 type=Pl050
1119 amba_id=1314896
1120 clk_domain=system.clk_domain
1121 eventq_index=0
1122 gic=system.realview.gic
1123 int_delay=1000000
1124 int_num=53
1125 is_mouse=true
1126 pio_addr=268464128
1127 pio_latency=100000
1128 system=system
1129 vnc=system.vncserver
1130 pio=system.iobus.master[6]
1131
1132 [system.realview.l2x0_fake]
1133 type=IsaFake
1134 clk_domain=system.clk_domain
1135 eventq_index=0
1136 fake_mem=false
1137 pio_addr=520101888
1138 pio_latency=100000
1139 pio_size=4095
1140 ret_bad_addr=false
1141 ret_data16=65535
1142 ret_data32=4294967295
1143 ret_data64=18446744073709551615
1144 ret_data8=255
1145 system=system
1146 update_data=false
1147 warn_access=
1148 pio=system.membus.master[3]
1149
1150 [system.realview.local_cpu_timer]
1151 type=CpuLocalTimer
1152 clk_domain=system.clk_domain
1153 eventq_index=0
1154 gic=system.realview.gic
1155 int_num_timer=29
1156 int_num_watchdog=30
1157 pio_addr=520095232
1158 pio_latency=100000
1159 system=system
1160 pio=system.membus.master[5]
1161
1162 [system.realview.mmc_fake]
1163 type=AmbaFake
1164 amba_id=0
1165 clk_domain=system.clk_domain
1166 eventq_index=0
1167 ignore_access=false
1168 pio_addr=268455936
1169 pio_latency=100000
1170 system=system
1171 pio=system.iobus.master[22]
1172
1173 [system.realview.nvmem]
1174 type=SimpleMemory
1175 bandwidth=73.000000
1176 clk_domain=system.clk_domain
1177 conf_table_reported=false
1178 eventq_index=0
1179 in_addr_map=true
1180 latency=30000
1181 latency_var=0
1182 null=false
1183 range=2147483648:2214592511
1184 port=system.membus.master[1]
1185
1186 [system.realview.realview_io]
1187 type=RealViewCtrl
1188 clk_domain=system.clk_domain
1189 eventq_index=0
1190 idreg=0
1191 pio_addr=268435456
1192 pio_latency=100000
1193 proc_id0=201326592
1194 proc_id1=201327138
1195 system=system
1196 pio=system.iobus.master[1]
1197
1198 [system.realview.rtc]
1199 type=PL031
1200 amba_id=3412017
1201 clk_domain=system.clk_domain
1202 eventq_index=0
1203 gic=system.realview.gic
1204 int_delay=100000
1205 int_num=42
1206 pio_addr=268529664
1207 pio_latency=100000
1208 system=system
1209 time=Thu Jan  1 00:00:00 2009
1210 pio=system.iobus.master[23]
1211
1212 [system.realview.sci_fake]
1213 type=AmbaFake
1214 amba_id=0
1215 clk_domain=system.clk_domain
1216 eventq_index=0
1217 ignore_access=false
1218 pio_addr=268492800
1219 pio_latency=100000
1220 system=system
1221 pio=system.iobus.master[20]
1222
1223 [system.realview.smc_fake]
1224 type=AmbaFake
1225 amba_id=0
1226 clk_domain=system.clk_domain
1227 eventq_index=0
1228 ignore_access=false
1229 pio_addr=269357056
1230 pio_latency=100000
1231 system=system
1232 pio=system.iobus.master[13]
1233
1234 [system.realview.sp810_fake]
1235 type=AmbaFake
1236 amba_id=0
1237 clk_domain=system.clk_domain
1238 eventq_index=0
1239 ignore_access=true
1240 pio_addr=268439552
1241 pio_latency=100000
1242 system=system
1243 pio=system.iobus.master[14]
1244
1245 [system.realview.ssp_fake]
1246 type=AmbaFake
1247 amba_id=0
1248 clk_domain=system.clk_domain
1249 eventq_index=0
1250 ignore_access=false
1251 pio_addr=268488704
1252 pio_latency=100000
1253 system=system
1254 pio=system.iobus.master[19]
1255
1256 [system.realview.timer0]
1257 type=Sp804
1258 amba_id=1316868
1259 clk_domain=system.clk_domain
1260 clock0=1000000
1261 clock1=1000000
1262 eventq_index=0
1263 gic=system.realview.gic
1264 int_num0=36
1265 int_num1=36
1266 pio_addr=268505088
1267 pio_latency=100000
1268 system=system
1269 pio=system.iobus.master[2]
1270
1271 [system.realview.timer1]
1272 type=Sp804
1273 amba_id=1316868
1274 clk_domain=system.clk_domain
1275 clock0=1000000
1276 clock1=1000000
1277 eventq_index=0
1278 gic=system.realview.gic
1279 int_num0=37
1280 int_num1=37
1281 pio_addr=268509184
1282 pio_latency=100000
1283 system=system
1284 pio=system.iobus.master[3]
1285
1286 [system.realview.uart]
1287 type=Pl011
1288 clk_domain=system.clk_domain
1289 end_on_eot=false
1290 eventq_index=0
1291 gic=system.realview.gic
1292 int_delay=100000
1293 int_num=44
1294 pio_addr=268472320
1295 pio_latency=100000
1296 platform=system.realview
1297 system=system
1298 terminal=system.terminal
1299 pio=system.iobus.master[0]
1300
1301 [system.realview.uart1_fake]
1302 type=AmbaFake
1303 amba_id=0
1304 clk_domain=system.clk_domain
1305 eventq_index=0
1306 ignore_access=false
1307 pio_addr=268476416
1308 pio_latency=100000
1309 system=system
1310 pio=system.iobus.master[10]
1311
1312 [system.realview.uart2_fake]
1313 type=AmbaFake
1314 amba_id=0
1315 clk_domain=system.clk_domain
1316 eventq_index=0
1317 ignore_access=false
1318 pio_addr=268480512
1319 pio_latency=100000
1320 system=system
1321 pio=system.iobus.master[11]
1322
1323 [system.realview.uart3_fake]
1324 type=AmbaFake
1325 amba_id=0
1326 clk_domain=system.clk_domain
1327 eventq_index=0
1328 ignore_access=false
1329 pio_addr=268484608
1330 pio_latency=100000
1331 system=system
1332 pio=system.iobus.master[12]
1333
1334 [system.realview.watchdog_fake]
1335 type=AmbaFake
1336 amba_id=0
1337 clk_domain=system.clk_domain
1338 eventq_index=0
1339 ignore_access=false
1340 pio_addr=268500992
1341 pio_latency=100000
1342 system=system
1343 pio=system.iobus.master[15]
1344
1345 [system.terminal]
1346 type=Terminal
1347 eventq_index=0
1348 intr_control=system.intrctrl
1349 number=0
1350 output=true
1351 port=3456
1352
1353 [system.vncserver]
1354 type=VncServer
1355 eventq_index=0
1356 frame_capture=false
1357 number=0
1358 port=5900
1359
1360 [system.voltage_domain]
1361 type=VoltageDomain
1362 eventq_index=0
1363 voltage=1.000000
1364