tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=true
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=LinuxArmSystem
  11 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  12 atags_addr=256
  13 boot_loader=/dist/m5/system/binaries/boot.arm
  14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 dtb_filename=False
  18 early_kernel_symbols=false
  19 enable_context_switch_stats_dump=false
  20 flags_addr=268435504
  21 gic_cpu_addr=520093952
  22 init_param=0
  23 kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  24 load_addr_mask=268435455
  25 machine_type=RealView_PBX
  26 mem_mode=timing
  27 mem_ranges=0:134217727
  28 memories=system.realview.nvmem system.physmem
  29 multi_proc=true
  30 num_work_ids=16
  31 panic_on_oops=true
  32 panic_on_panic=true
  33 readfile=tests/halt.sh
  34 symbolfile=
  35 work_begin_ckpt_count=0
  36 work_begin_cpu_id_exit=-1
  37 work_begin_exit_count=0
  38 work_cpus_ckpt_count=0
  39 work_end_ckpt_count=0
  40 work_end_exit_count=0
  41 work_item_id=-1
  42 system_port=system.membus.slave[0]
  43
  44 [system.bridge]
  45 type=Bridge
  46 clk_domain=system.clk_domain
  47 delay=50000
  48 ranges=268435456:520093695 1073741824:1610612735
  49 req_size=16
  50 resp_size=16
  51 master=system.iobus.slave[0]
  52 slave=system.membus.master[0]
  53
  54 [system.cf0]
  55 type=IdeDisk
  56 children=image
  57 delay=1000000
  58 driveID=master
  59 image=system.cf0.image
  60
  61 [system.cf0.image]
  62 type=CowDiskImage
  63 children=child
  64 child=system.cf0.image.child
  65 image_file=
  66 read_only=false
  67 table_size=65536
  68
  69 [system.cf0.image.child]
  70 type=RawDiskImage
  71 image_file=/dist/m5/system/disks/linux-arm-ael.img
  72 read_only=true
  73
  74 [system.clk_domain]
  75 type=SrcClockDomain
  76 clock=1000
  77 voltage_domain=system.voltage_domain
  78
  79 [system.cpu]
  80 type=DerivO3CPU
  81 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
  82 LFSTSize=1024
  83 LQEntries=32
  84 LSQCheckLoads=true
  85 LSQDepCheckShift=4
  86 SQEntries=32
  87 SSITSize=1024
  88 activity=0
  89 backComSize=5
  90 branchPred=system.cpu.branchPred
  91 cachePorts=200
  92 checker=Null
  93 clk_domain=system.cpu_clk_domain
  94 commitToDecodeDelay=1
  95 commitToFetchDelay=1
  96 commitToIEWDelay=1
  97 commitToRenameDelay=1
  98 commitWidth=8
  99 cpu_id=0
 100 decodeToFetchDelay=1
 101 decodeToRenameDelay=1
 102 decodeWidth=8
 103 dispatchWidth=8
 104 do_checkpoint_insts=true
 105 do_quiesce=true
 106 do_statistics_insts=true
 107 dtb=system.cpu.dtb
 108 fetchToDecodeDelay=1
 109 fetchTrapLatency=1
 110 fetchWidth=8
 111 forwardComSize=5
 112 fuPool=system.cpu.fuPool
 113 function_trace=false
 114 function_trace_start=0
 115 iewToCommitDelay=1
 116 iewToDecodeDelay=1
 117 iewToFetchDelay=1
 118 iewToRenameDelay=1
 119 interrupts=system.cpu.interrupts
 120 isa=system.cpu.isa
 121 issueToExecuteDelay=1
 122 issueWidth=8
 123 itb=system.cpu.itb
 124 max_insts_all_threads=0
 125 max_insts_any_thread=0
 126 max_loads_all_threads=0
 127 max_loads_any_thread=0
 128 needsTSO=false
 129 numIQEntries=64
 130 numPhysFloatRegs=256
 131 numPhysIntRegs=256
 132 numROBEntries=192
 133 numRobs=1
 134 numThreads=1
 135 profile=0
 136 progress_interval=0
 137 renameToDecodeDelay=1
 138 renameToFetchDelay=1
 139 renameToIEWDelay=2
 140 renameToROBDelay=1
 141 renameWidth=8
 142 simpoint_start_insts=
 143 smtCommitPolicy=RoundRobin
 144 smtFetchPolicy=SingleThread
 145 smtIQPolicy=Partitioned
 146 smtIQThreshold=100
 147 smtLSQPolicy=Partitioned
 148 smtLSQThreshold=100
 149 smtNumFetchingThreads=1
 150 smtROBPolicy=Partitioned
 151 smtROBThreshold=100
 152 squashWidth=8
 153 store_set_clear_period=250000
 154 switched_out=false
 155 system=system
 156 tracer=system.cpu.tracer
 157 trapLatency=13
 158 wbDepth=1
 159 wbWidth=8
 160 workload=
 161 dcache_port=system.cpu.dcache.cpu_side
 162 icache_port=system.cpu.icache.cpu_side
 163
 164 [system.cpu.branchPred]
 165 type=BranchPredictor
 166 BTBEntries=4096
 167 BTBTagSize=16
 168 RASSize=16
 169 choiceCtrBits=2
 170 choicePredictorSize=8192
 171 globalCtrBits=2
 172 globalPredictorSize=8192
 173 instShiftAmt=2
 174 localCtrBits=2
 175 localHistoryTableSize=2048
 176 localPredictorSize=2048
 177 numThreads=1
 178 predType=tournament
 179
 180 [system.cpu.dcache]
 181 type=BaseCache
 182 children=tags
 183 addr_ranges=0:18446744073709551615
 184 assoc=4
 185 clk_domain=system.cpu_clk_domain
 186 forward_snoops=true
 187 hit_latency=2
 188 is_top_level=true
 189 max_miss_count=0
 190 mshrs=4
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=2
 194 size=32768
 195 system=system
 196 tags=system.cpu.dcache.tags
 197 tgts_per_mshr=20
 198 two_queue=false
 199 write_buffers=8
 200 cpu_side=system.cpu.dcache_port
 201 mem_side=system.cpu.toL2Bus.slave[1]
 202
 203 [system.cpu.dcache.tags]
 204 type=LRU
 205 assoc=4
 206 block_size=64
 207 clk_domain=system.cpu_clk_domain
 208 hit_latency=2
 209 size=32768
 210
 211 [system.cpu.dtb]
 212 type=ArmTLB
 213 children=walker
 214 size=64
 215 walker=system.cpu.dtb.walker
 216
 217 [system.cpu.dtb.walker]
 218 type=ArmTableWalker
 219 clk_domain=system.cpu_clk_domain
 220 num_squash_per_cycle=2
 221 sys=system
 222 port=system.cpu.toL2Bus.slave[3]
 223
 224 [system.cpu.fuPool]
 225 type=FUPool
 226 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 227 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 228
 229 [system.cpu.fuPool.FUList0]
 230 type=FUDesc
 231 children=opList
 232 count=6
 233 opList=system.cpu.fuPool.FUList0.opList
 234
 235 [system.cpu.fuPool.FUList0.opList]
 236 type=OpDesc
 237 issueLat=1
 238 opClass=IntAlu
 239 opLat=1
 240
 241 [system.cpu.fuPool.FUList1]
 242 type=FUDesc
 243 children=opList0 opList1
 244 count=2
 245 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 246
 247 [system.cpu.fuPool.FUList1.opList0]
 248 type=OpDesc
 249 issueLat=1
 250 opClass=IntMult
 251 opLat=3
 252
 253 [system.cpu.fuPool.FUList1.opList1]
 254 type=OpDesc
 255 issueLat=19
 256 opClass=IntDiv
 257 opLat=20
 258
 259 [system.cpu.fuPool.FUList2]
 260 type=FUDesc
 261 children=opList0 opList1 opList2
 262 count=4
 263 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 264
 265 [system.cpu.fuPool.FUList2.opList0]
 266 type=OpDesc
 267 issueLat=1
 268 opClass=FloatAdd
 269 opLat=2
 270
 271 [system.cpu.fuPool.FUList2.opList1]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=FloatCmp
 275 opLat=2
 276
 277 [system.cpu.fuPool.FUList2.opList2]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=FloatCvt
 281 opLat=2
 282
 283 [system.cpu.fuPool.FUList3]
 284 type=FUDesc
 285 children=opList0 opList1 opList2
 286 count=2
 287 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 288
 289 [system.cpu.fuPool.FUList3.opList0]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=FloatMult
 293 opLat=4
 294
 295 [system.cpu.fuPool.FUList3.opList1]
 296 type=OpDesc
 297 issueLat=12
 298 opClass=FloatDiv
 299 opLat=12
 300
 301 [system.cpu.fuPool.FUList3.opList2]
 302 type=OpDesc
 303 issueLat=24
 304 opClass=FloatSqrt
 305 opLat=24
 306
 307 [system.cpu.fuPool.FUList4]
 308 type=FUDesc
 309 children=opList
 310 count=0
 311 opList=system.cpu.fuPool.FUList4.opList
 312
 313 [system.cpu.fuPool.FUList4.opList]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=MemRead
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5]
 320 type=FUDesc
 321 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 322 count=4
 323 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 324
 325 [system.cpu.fuPool.FUList5.opList00]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdAdd
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList01]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdAddAcc
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList02]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdAlu
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList03]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdCmp
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList04]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdCvt
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList05]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdMisc
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList06]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdMult
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList07]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdMultAcc
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList08]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=SimdShift
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList09]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=SimdShiftAcc
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList5.opList10]
 386 type=OpDesc
 387 issueLat=1
 388 opClass=SimdSqrt
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList5.opList11]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=SimdFloatAdd
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList5.opList12]
 398 type=OpDesc
 399 issueLat=1
 400 opClass=SimdFloatAlu
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList5.opList13]
 404 type=OpDesc
 405 issueLat=1
 406 opClass=SimdFloatCmp
 407 opLat=1
 408
 409 [system.cpu.fuPool.FUList5.opList14]
 410 type=OpDesc
 411 issueLat=1
 412 opClass=SimdFloatCvt
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList5.opList15]
 416 type=OpDesc
 417 issueLat=1
 418 opClass=SimdFloatDiv
 419 opLat=1
 420
 421 [system.cpu.fuPool.FUList5.opList16]
 422 type=OpDesc
 423 issueLat=1
 424 opClass=SimdFloatMisc
 425 opLat=1
 426
 427 [system.cpu.fuPool.FUList5.opList17]
 428 type=OpDesc
 429 issueLat=1
 430 opClass=SimdFloatMult
 431 opLat=1
 432
 433 [system.cpu.fuPool.FUList5.opList18]
 434 type=OpDesc
 435 issueLat=1
 436 opClass=SimdFloatMultAcc
 437 opLat=1
 438
 439 [system.cpu.fuPool.FUList5.opList19]
 440 type=OpDesc
 441 issueLat=1
 442 opClass=SimdFloatSqrt
 443 opLat=1
 444
 445 [system.cpu.fuPool.FUList6]
 446 type=FUDesc
 447 children=opList
 448 count=0
 449 opList=system.cpu.fuPool.FUList6.opList
 450
 451 [system.cpu.fuPool.FUList6.opList]
 452 type=OpDesc
 453 issueLat=1
 454 opClass=MemWrite
 455 opLat=1
 456
 457 [system.cpu.fuPool.FUList7]
 458 type=FUDesc
 459 children=opList0 opList1
 460 count=4
 461 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 462
 463 [system.cpu.fuPool.FUList7.opList0]
 464 type=OpDesc
 465 issueLat=1
 466 opClass=MemRead
 467 opLat=1
 468
 469 [system.cpu.fuPool.FUList7.opList1]
 470 type=OpDesc
 471 issueLat=1
 472 opClass=MemWrite
 473 opLat=1
 474
 475 [system.cpu.fuPool.FUList8]
 476 type=FUDesc
 477 children=opList
 478 count=1
 479 opList=system.cpu.fuPool.FUList8.opList
 480
 481 [system.cpu.fuPool.FUList8.opList]
 482 type=OpDesc
 483 issueLat=3
 484 opClass=IprAccess
 485 opLat=3
 486
 487 [system.cpu.icache]
 488 type=BaseCache
 489 children=tags
 490 addr_ranges=0:18446744073709551615
 491 assoc=1
 492 clk_domain=system.cpu_clk_domain
 493 forward_snoops=true
 494 hit_latency=2
 495 is_top_level=true
 496 max_miss_count=0
 497 mshrs=4
 498 prefetch_on_access=false
 499 prefetcher=Null
 500 response_latency=2
 501 size=32768
 502 system=system
 503 tags=system.cpu.icache.tags
 504 tgts_per_mshr=20
 505 two_queue=false
 506 write_buffers=8
 507 cpu_side=system.cpu.icache_port
 508 mem_side=system.cpu.toL2Bus.slave[0]
 509
 510 [system.cpu.icache.tags]
 511 type=LRU
 512 assoc=1
 513 block_size=64
 514 clk_domain=system.cpu_clk_domain
 515 hit_latency=2
 516 size=32768
 517
 518 [system.cpu.interrupts]
 519 type=ArmInterrupts
 520
 521 [system.cpu.isa]
 522 type=ArmISA
 523 fpsid=1090793632
 524 id_isar0=34607377
 525 id_isar1=34677009
 526 id_isar2=555950401
 527 id_isar3=17899825
 528 id_isar4=268501314
 529 id_isar5=0
 530 id_mmfr0=3
 531 id_mmfr1=0
 532 id_mmfr2=19070976
 533 id_mmfr3=4027589137
 534 id_pfr0=49
 535 id_pfr1=1
 536 midr=890224640
 537
 538 [system.cpu.itb]
 539 type=ArmTLB
 540 children=walker
 541 size=64
 542 walker=system.cpu.itb.walker
 543
 544 [system.cpu.itb.walker]
 545 type=ArmTableWalker
 546 clk_domain=system.cpu_clk_domain
 547 num_squash_per_cycle=2
 548 sys=system
 549 port=system.cpu.toL2Bus.slave[2]
 550
 551 [system.cpu.l2cache]
 552 type=BaseCache
 553 children=tags
 554 addr_ranges=0:18446744073709551615
 555 assoc=8
 556 clk_domain=system.cpu_clk_domain
 557 forward_snoops=true
 558 hit_latency=20
 559 is_top_level=false
 560 max_miss_count=0
 561 mshrs=20
 562 prefetch_on_access=false
 563 prefetcher=Null
 564 response_latency=20
 565 size=4194304
 566 system=system
 567 tags=system.cpu.l2cache.tags
 568 tgts_per_mshr=12
 569 two_queue=false
 570 write_buffers=8
 571 cpu_side=system.cpu.toL2Bus.master[0]
 572 mem_side=system.membus.slave[1]
 573
 574 [system.cpu.l2cache.tags]
 575 type=LRU
 576 assoc=8
 577 block_size=64
 578 clk_domain=system.cpu_clk_domain
 579 hit_latency=20
 580 size=4194304
 581
 582 [system.cpu.toL2Bus]
 583 type=CoherentBus
 584 clk_domain=system.cpu_clk_domain
 585 header_cycles=1
 586 system=system
 587 use_default_range=false
 588 width=32
 589 master=system.cpu.l2cache.cpu_side
 590 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 591
 592 [system.cpu.tracer]
 593 type=ExeTracer
 594
 595 [system.cpu_clk_domain]
 596 type=SrcClockDomain
 597 clock=500
 598 voltage_domain=system.voltage_domain
 599
 600 [system.intrctrl]
 601 type=IntrControl
 602 sys=system
 603
 604 [system.iobus]
 605 type=NoncoherentBus
 606 clk_domain=system.clk_domain
 607 header_cycles=1
 608 use_default_range=false
 609 width=8
 610 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 611 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 612
 613 [system.iocache]
 614 type=BaseCache
 615 children=tags
 616 addr_ranges=0:134217727
 617 assoc=8
 618 clk_domain=system.clk_domain
 619 forward_snoops=false
 620 hit_latency=50
 621 is_top_level=true
 622 max_miss_count=0
 623 mshrs=20
 624 prefetch_on_access=false
 625 prefetcher=Null
 626 response_latency=50
 627 size=1024
 628 system=system
 629 tags=system.iocache.tags
 630 tgts_per_mshr=12
 631 two_queue=false
 632 write_buffers=8
 633 cpu_side=system.iobus.master[25]
 634 mem_side=system.membus.slave[2]
 635
 636 [system.iocache.tags]
 637 type=LRU
 638 assoc=8
 639 block_size=64
 640 clk_domain=system.clk_domain
 641 hit_latency=50
 642 size=1024
 643
 644 [system.membus]
 645 type=CoherentBus
 646 children=badaddr_responder
 647 clk_domain=system.clk_domain
 648 header_cycles=1
 649 system=system
 650 use_default_range=false
 651 width=8
 652 default=system.membus.badaddr_responder.pio
 653 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 654 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 655
 656 [system.membus.badaddr_responder]
 657 type=IsaFake
 658 clk_domain=system.clk_domain
 659 fake_mem=false
 660 pio_addr=0
 661 pio_latency=100000
 662 pio_size=8
 663 ret_bad_addr=true
 664 ret_data16=65535
 665 ret_data32=4294967295
 666 ret_data64=18446744073709551615
 667 ret_data8=255
 668 system=system
 669 update_data=false
 670 warn_access=warn
 671 pio=system.membus.default
 672
 673 [system.physmem]
 674 type=SimpleDRAM
 675 activation_limit=4
 676 addr_mapping=RaBaChCo
 677 banks_per_rank=8
 678 burst_length=8
 679 channels=1
 680 clk_domain=system.clk_domain
 681 conf_table_reported=true
 682 device_bus_width=8
 683 device_rowbuffer_size=1024
 684 devices_per_rank=8
 685 in_addr_map=true
 686 mem_sched_policy=frfcfs
 687 null=false
 688 page_policy=open
 689 range=0:134217727
 690 ranks_per_channel=2
 691 read_buffer_size=32
 692 static_backend_latency=10000
 693 static_frontend_latency=10000
 694 tBURST=5000
 695 tCL=13750
 696 tRCD=13750
 697 tREFI=7800000
 698 tRFC=300000
 699 tRP=13750
 700 tWTR=7500
 701 tXAW=40000
 702 write_buffer_size=32
 703 write_thresh_perc=70
 704 port=system.membus.master[6]
 705
 706 [system.realview]
 707 type=RealView
 708 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 709 intrctrl=system.intrctrl
 710 max_mem_size=268435456
 711 mem_start_addr=0
 712 pci_cfg_base=0
 713 system=system
 714
 715 [system.realview.a9scu]
 716 type=A9SCU
 717 clk_domain=system.clk_domain
 718 pio_addr=520093696
 719 pio_latency=100000
 720 system=system
 721 pio=system.membus.master[4]
 722
 723 [system.realview.aaci_fake]
 724 type=AmbaFake
 725 amba_id=0
 726 clk_domain=system.clk_domain
 727 ignore_access=false
 728 pio_addr=268451840
 729 pio_latency=100000
 730 system=system
 731 pio=system.iobus.master[21]
 732
 733 [system.realview.cf_ctrl]
 734 type=IdeController
 735 BAR0=402653184
 736 BAR0LegacyIO=true
 737 BAR0Size=16
 738 BAR1=402653440
 739 BAR1LegacyIO=true
 740 BAR1Size=1
 741 BAR2=1
 742 BAR2LegacyIO=false
 743 BAR2Size=8
 744 BAR3=1
 745 BAR3LegacyIO=false
 746 BAR3Size=4
 747 BAR4=1
 748 BAR4LegacyIO=false
 749 BAR4Size=16
 750 BAR5=1
 751 BAR5LegacyIO=false
 752 BAR5Size=0
 753 BIST=0
 754 CacheLineSize=0
 755 CardbusCIS=0
 756 ClassCode=1
 757 Command=1
 758 DeviceID=28945
 759 ExpansionROM=0
 760 HeaderType=0
 761 InterruptLine=31
 762 InterruptPin=1
 763 LatencyTimer=0
 764 MaximumLatency=0
 765 MinimumGrant=0
 766 ProgIF=133
 767 Revision=0
 768 Status=640
 769 SubClassCode=1
 770 SubsystemID=0
 771 SubsystemVendorID=0
 772 VendorID=32902
 773 clk_domain=system.clk_domain
 774 config_latency=20000
 775 ctrl_offset=2
 776 disks=system.cf0
 777 io_shift=1
 778 pci_bus=2
 779 pci_dev=7
 780 pci_func=0
 781 pio_latency=30000
 782 platform=system.realview
 783 system=system
 784 config=system.iobus.master[8]
 785 dma=system.iobus.slave[2]
 786 pio=system.iobus.master[7]
 787
 788 [system.realview.clcd]
 789 type=Pl111
 790 amba_id=1315089
 791 clk_domain=system.clk_domain
 792 gic=system.realview.gic
 793 int_num=55
 794 pio_addr=268566528
 795 pio_latency=10000
 796 pixel_clock=41667
 797 system=system
 798 vnc=system.vncserver
 799 dma=system.iobus.slave[1]
 800 pio=system.iobus.master[4]
 801
 802 [system.realview.dmac_fake]
 803 type=AmbaFake
 804 amba_id=0
 805 clk_domain=system.clk_domain
 806 ignore_access=false
 807 pio_addr=268632064
 808 pio_latency=100000
 809 system=system
 810 pio=system.iobus.master[9]
 811
 812 [system.realview.flash_fake]
 813 type=IsaFake
 814 clk_domain=system.clk_domain
 815 fake_mem=true
 816 pio_addr=1073741824
 817 pio_latency=100000
 818 pio_size=536870912
 819 ret_bad_addr=false
 820 ret_data16=65535
 821 ret_data32=4294967295
 822 ret_data64=18446744073709551615
 823 ret_data8=255
 824 system=system
 825 update_data=false
 826 warn_access=
 827 pio=system.iobus.master[24]
 828
 829 [system.realview.gic]
 830 type=Pl390
 831 clk_domain=system.clk_domain
 832 cpu_addr=520093952
 833 cpu_pio_delay=10000
 834 dist_addr=520097792
 835 dist_pio_delay=10000
 836 int_latency=10000
 837 it_lines=128
 838 platform=system.realview
 839 system=system
 840 pio=system.membus.master[2]
 841
 842 [system.realview.gpio0_fake]
 843 type=AmbaFake
 844 amba_id=0
 845 clk_domain=system.clk_domain
 846 ignore_access=false
 847 pio_addr=268513280
 848 pio_latency=100000
 849 system=system
 850 pio=system.iobus.master[16]
 851
 852 [system.realview.gpio1_fake]
 853 type=AmbaFake
 854 amba_id=0
 855 clk_domain=system.clk_domain
 856 ignore_access=false
 857 pio_addr=268517376
 858 pio_latency=100000
 859 system=system
 860 pio=system.iobus.master[17]
 861
 862 [system.realview.gpio2_fake]
 863 type=AmbaFake
 864 amba_id=0
 865 clk_domain=system.clk_domain
 866 ignore_access=false
 867 pio_addr=268521472
 868 pio_latency=100000
 869 system=system
 870 pio=system.iobus.master[18]
 871
 872 [system.realview.kmi0]
 873 type=Pl050
 874 amba_id=1314896
 875 clk_domain=system.clk_domain
 876 gic=system.realview.gic
 877 int_delay=1000000
 878 int_num=52
 879 is_mouse=false
 880 pio_addr=268460032
 881 pio_latency=100000
 882 system=system
 883 vnc=system.vncserver
 884 pio=system.iobus.master[5]
 885
 886 [system.realview.kmi1]
 887 type=Pl050
 888 amba_id=1314896
 889 clk_domain=system.clk_domain
 890 gic=system.realview.gic
 891 int_delay=1000000
 892 int_num=53
 893 is_mouse=true
 894 pio_addr=268464128
 895 pio_latency=100000
 896 system=system
 897 vnc=system.vncserver
 898 pio=system.iobus.master[6]
 899
 900 [system.realview.l2x0_fake]
 901 type=IsaFake
 902 clk_domain=system.clk_domain
 903 fake_mem=false
 904 pio_addr=520101888
 905 pio_latency=100000
 906 pio_size=4095
 907 ret_bad_addr=false
 908 ret_data16=65535
 909 ret_data32=4294967295
 910 ret_data64=18446744073709551615
 911 ret_data8=255
 912 system=system
 913 update_data=false
 914 warn_access=
 915 pio=system.membus.master[3]
 916
 917 [system.realview.local_cpu_timer]
 918 type=CpuLocalTimer
 919 clk_domain=system.clk_domain
 920 gic=system.realview.gic
 921 int_num_timer=29
 922 int_num_watchdog=30
 923 pio_addr=520095232
 924 pio_latency=100000
 925 system=system
 926 pio=system.membus.master[5]
 927
 928 [system.realview.mmc_fake]
 929 type=AmbaFake
 930 amba_id=0
 931 clk_domain=system.clk_domain
 932 ignore_access=false
 933 pio_addr=268455936
 934 pio_latency=100000
 935 system=system
 936 pio=system.iobus.master[22]
 937
 938 [system.realview.nvmem]
 939 type=SimpleMemory
 940 bandwidth=73.000000
 941 clk_domain=system.clk_domain
 942 conf_table_reported=false
 943 in_addr_map=true
 944 latency=30000
 945 latency_var=0
 946 null=false
 947 range=2147483648:2214592511
 948 port=system.membus.master[1]
 949
 950 [system.realview.realview_io]
 951 type=RealViewCtrl
 952 clk_domain=system.clk_domain
 953 idreg=0
 954 pio_addr=268435456
 955 pio_latency=100000
 956 proc_id0=201326592
 957 proc_id1=201327138
 958 system=system
 959 pio=system.iobus.master[1]
 960
 961 [system.realview.rtc]
 962 type=PL031
 963 amba_id=3412017
 964 clk_domain=system.clk_domain
 965 gic=system.realview.gic
 966 int_delay=100000
 967 int_num=42
 968 pio_addr=268529664
 969 pio_latency=100000
 970 system=system
 971 time=Thu Jan  1 00:00:00 2009
 972 pio=system.iobus.master[23]
 973
 974 [system.realview.sci_fake]
 975 type=AmbaFake
 976 amba_id=0
 977 clk_domain=system.clk_domain
 978 ignore_access=false
 979 pio_addr=268492800
 980 pio_latency=100000
 981 system=system
 982 pio=system.iobus.master[20]
 983
 984 [system.realview.smc_fake]
 985 type=AmbaFake
 986 amba_id=0
 987 clk_domain=system.clk_domain
 988 ignore_access=false
 989 pio_addr=269357056
 990 pio_latency=100000
 991 system=system
 992 pio=system.iobus.master[13]
 993
 994 [system.realview.sp810_fake]
 995 type=AmbaFake
 996 amba_id=0
 997 clk_domain=system.clk_domain
 998 ignore_access=true
 999 pio_addr=268439552
1000 pio_latency=100000
1001 system=system
1002 pio=system.iobus.master[14]
1003
1004 [system.realview.ssp_fake]
1005 type=AmbaFake
1006 amba_id=0
1007 clk_domain=system.clk_domain
1008 ignore_access=false
1009 pio_addr=268488704
1010 pio_latency=100000
1011 system=system
1012 pio=system.iobus.master[19]
1013
1014 [system.realview.timer0]
1015 type=Sp804
1016 amba_id=1316868
1017 clk_domain=system.clk_domain
1018 clock0=1000000
1019 clock1=1000000
1020 gic=system.realview.gic
1021 int_num0=36
1022 int_num1=36
1023 pio_addr=268505088
1024 pio_latency=100000
1025 system=system
1026 pio=system.iobus.master[2]
1027
1028 [system.realview.timer1]
1029 type=Sp804
1030 amba_id=1316868
1031 clk_domain=system.clk_domain
1032 clock0=1000000
1033 clock1=1000000
1034 gic=system.realview.gic
1035 int_num0=37
1036 int_num1=37
1037 pio_addr=268509184
1038 pio_latency=100000
1039 system=system
1040 pio=system.iobus.master[3]
1041
1042 [system.realview.uart]
1043 type=Pl011
1044 clk_domain=system.clk_domain
1045 end_on_eot=false
1046 gic=system.realview.gic
1047 int_delay=100000
1048 int_num=44
1049 pio_addr=268472320
1050 pio_latency=100000
1051 platform=system.realview
1052 system=system
1053 terminal=system.terminal
1054 pio=system.iobus.master[0]
1055
1056 [system.realview.uart1_fake]
1057 type=AmbaFake
1058 amba_id=0
1059 clk_domain=system.clk_domain
1060 ignore_access=false
1061 pio_addr=268476416
1062 pio_latency=100000
1063 system=system
1064 pio=system.iobus.master[10]
1065
1066 [system.realview.uart2_fake]
1067 type=AmbaFake
1068 amba_id=0
1069 clk_domain=system.clk_domain
1070 ignore_access=false
1071 pio_addr=268480512
1072 pio_latency=100000
1073 system=system
1074 pio=system.iobus.master[11]
1075
1076 [system.realview.uart3_fake]
1077 type=AmbaFake
1078 amba_id=0
1079 clk_domain=system.clk_domain
1080 ignore_access=false
1081 pio_addr=268484608
1082 pio_latency=100000
1083 system=system
1084 pio=system.iobus.master[12]
1085
1086 [system.realview.watchdog_fake]
1087 type=AmbaFake
1088 amba_id=0
1089 clk_domain=system.clk_domain
1090 ignore_access=false
1091 pio_addr=268500992
1092 pio_latency=100000
1093 system=system
1094 pio=system.iobus.master[15]
1095
1096 [system.terminal]
1097 type=Terminal
1098 intr_control=system.intrctrl
1099 number=0
1100 output=true
1101 port=3456
1102
1103 [system.vncserver]
1104 type=VncServer
1105 frame_capture=false
1106 number=0
1107 port=5900
1108
1109 [system.voltage_domain]
1110 type=VoltageDomain
1111 voltage=1.000000
1112