tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr

   1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
   2 info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
   3 warn: Sockets disabled, not accepting vnc client connections
   4 warn: Sockets disabled, not accepting terminal connections
   5 warn: Sockets disabled, not accepting gdb connections
   6 warn: ClockedObject: More than one power state change request encountered within the same simulation tick
   7 info: Using bootloader at address 0x10
   8 info: Using kernel entry physical address at 0x80008000
   9 info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
  10 warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
  11 info: Entering event queue @ 0.  Starting simulation...
  12 warn: Not doing anything for miscreg ACTLR
  13 warn: Not doing anything for write of miscreg ACTLR
  14 warn: The clidr register always reports 0 caches.
  15 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
  16 warn: The csselr register isn't implemented.
  17 warn:   instruction 'mcr dccmvau' unimplemented
  18 warn:   instruction 'mcr icimvau' unimplemented
  19 warn:   instruction 'mcr bpiallis' unimplemented
  20 warn:   instruction 'mcr icialluis' unimplemented
  21 warn:   instruction 'mcr dccimvac' unimplemented
  22 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
  23 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  24 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  25 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  26 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  27 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  28 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  29 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  30 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  31 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
  32 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  33 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  34 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  35 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  36 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  37 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  38 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  39 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  40 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  41 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  42 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
  43 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  44 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  45 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  46 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  47 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
  48 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
  49 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
  50 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
  51 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
  52 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
  53 warn: Returning zero for read from miscreg pmcr
  54 warn: Ignoring write to miscreg pmcntenclr
  55 warn: Ignoring write to miscreg pmintenclr
  56 warn: Ignoring write to miscreg pmovsr
  57 warn: Ignoring write to miscreg pmcr
  58 warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
  59 warn:   instruction 'mcr dcisw' unimplemented
  60 warn:   instruction 'mcr bpiall' unimplemented