regressions: updates due to changes to o3 cpu, x86 memory map

[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-o3 / stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.533115                       # Number of seconds simulated
sim_ticks                                2533114761500                       # Number of ticks simulated
final_tick                               2533114761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  48903                       # Simulator instruction rate (inst/s)
host_op_rate                                    62925                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2054075271                       # Simulator tick rate (ticks/s)
host_mem_usage                                 439344                       # Number of bytes of host memory used
host_seconds                                  1233.21                       # Real time elapsed on the host
sim_insts                                    60307912                       # Number of instructions simulated
sim_ops                                      77599507                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            797568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9093776                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129431504                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       797568                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          797568                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3783296                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6799368                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           36                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12462                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142124                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15096833                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59114                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813132                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47189991                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            910                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             76                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               314857                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3589958                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51095792                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          314857                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314857                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1493535                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1190657                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2684193                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1493535                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47189991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           910                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            76                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              314857                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4780616                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53779984                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15096833                       # Total number of read requests seen
system.physmem.writeReqs                       813132                       # Total number of write requests seen
system.physmem.cpureqs                         218384                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    966197312                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52040448                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              129431504                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6799368                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      362                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4681                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                943940                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                943443                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                943393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                944200                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                943981                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                943147                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                943277                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                943874                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                943783                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                943286                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               943218                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               943604                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               943686                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               943073                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               942962                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               943604                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50831                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50410                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50438                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51154                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50913                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50182                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50278                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50867                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51364                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 50898                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50799                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51185                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51240                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50713                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                50631                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51229                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32499                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2533113625500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      36                       # Categorize read packet sizes
system.physmem.readPktSize::3                14942208                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154589                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  59114                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1039924                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    981034                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    950254                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3550451                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2676520                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2688059                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2649699                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     60688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59177                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    108732                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   157579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   108199                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    16725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    16575                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20010                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    12714                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2832                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32522                       # What write queue length does an incoming req see
system.physmem.totQLat                   393203348000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              485594944250                       # Sum of mem lat for all requests
system.physmem.totBusLat                  75482355000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16909241250                       # Total cycles spent in bank access
system.physmem.avgQLat                       26046.04                       # Average queueing delay per request
system.physmem.avgBankLat                     1120.08                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  32166.12                       # Average memory access latency
system.physmem.avgRdBW                         381.43                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.54                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.10                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.14                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.19                       # Average read queue length over time
system.physmem.avgWrQLen                        12.50                       # Average write queue length over time
system.physmem.readRowHits                   15020252                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    793086                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.50                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.53                       # Row buffer hit rate for writes
system.physmem.avgGap                       159215.54                       # Average gap between requests
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                14667150                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11753528                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            704564                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9796618                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7939850                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.046847                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1399135                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72592                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51396830                       # DTB read hits
system.cpu.dtb.read_misses                      64077                       # DTB read misses
system.cpu.dtb.write_hits                    11700143                       # DTB write hits
system.cpu.dtb.write_misses                     15896                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3561                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2438                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    402                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1367                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51460907                       # DTB read accesses
system.cpu.dtb.write_accesses                11716039                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63096973                       # DTB hits
system.cpu.dtb.misses                           79973                       # DTB misses
system.cpu.dtb.accesses                      63176946                       # DTB accesses
system.cpu.itb.inst_hits                     12326910                       # ITB inst hits
system.cpu.itb.inst_misses                      11389                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2475                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2902                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 12338299                       # ITB inst accesses
system.cpu.itb.hits                          12326910                       # DTB hits
system.cpu.itb.misses                           11389                       # DTB misses
system.cpu.itb.accesses                      12338299                       # DTB accesses
system.cpu.numCycles                        471812928                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30572325                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       95988347                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14667150                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9338985                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21158726                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5294508                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     123624                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               95546847                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2524                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         86189                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       195223                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          338                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  12323529                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                899693                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5440                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          151321070                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.784862                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.149553                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                130177628     86.03%     86.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1303626      0.86%     86.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1711813      1.13%     88.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2496487      1.65%     89.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2227867      1.47%     91.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1109718      0.73%     91.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2758277      1.82%     93.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   745468      0.49%     94.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8790186      5.81%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            151321070                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.031087                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.203446                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32524080                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              95179608                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19189171                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                962117                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3466094                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1956870                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171719                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              112629435                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                567829                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3466094                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 34464944                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                36679462                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       52534223                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18153241                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6023106                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              106095889                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20512                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 985946                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4064605                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              763                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           110475366                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             485429679                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        485339109                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             90570                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78390245                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32085120                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             830681                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         737048                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12150768                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             20327707                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13516010                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1973803                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2472084                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97885695                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1983581                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 124302750                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            167746                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21700961                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     56920385                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         501172                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     151321070                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.821450                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.535276                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           107116828     70.79%     70.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13508917      8.93%     79.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7078442      4.68%     84.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5929928      3.92%     88.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12595030      8.32%     96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2803233      1.85%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1696659      1.12%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              465338      0.31%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              126695      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       151321070                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   61883      0.70%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8366537     94.63%     95.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                413041      4.67%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58607180     47.15%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93099      0.07%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  18      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           13      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52915799     42.57%     90.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12320844      9.91%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              124302750                       # Type of FU issued
system.cpu.iq.rate                           0.263458                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8841465                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071128                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          408992248                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         121586509                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     85934655                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23175                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12492                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10289                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              132768239                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12310                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           623420                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4673095                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6218                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29888                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1783885                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107776                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        892693                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3466094                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                27949012                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                433143                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100090532                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            202747                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              20327707                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13516010                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1410284                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 112802                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3586                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29888                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         350750                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       269018                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               619768                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121511519                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52083610                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2791231                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221256                       # number of nop insts executed
system.cpu.iew.exec_refs                     64295473                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11548935                       # Number of branches executed
system.cpu.iew.exec_stores                   12211863                       # Number of stores executed
system.cpu.iew.exec_rate                     0.257542                       # Inst execution rate
system.cpu.iew.wb_sent                      120354811                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      85944944                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47248906                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88214174                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.182159                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535616                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        21435223                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482409                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            535384                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    147854976                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.525852                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.516269                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    120428562     81.45%     81.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13320107      9.01%     90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3879152      2.62%     93.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2123376      1.44%     94.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1928119      1.30%     95.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       968604      0.66%     96.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1604726      1.09%     97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       701143      0.47%     98.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2901187      1.96%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    147854976                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60458293                       # Number of instructions committed
system.cpu.commit.committedOps               77749888                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27386737                       # Number of memory references committed
system.cpu.commit.loads                      15654612                       # Number of loads committed
system.cpu.commit.membars                      403603                       # Number of memory barriers committed
system.cpu.commit.branches                    9961369                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68855092                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991267                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2901187                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    242290263                       # The number of ROB reads
system.cpu.rob.rob_writes                   201932483                       # The number of ROB writes
system.cpu.timesIdled                         1770811                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       320491858                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4594333550                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60307912                       # Number of Instructions Simulated
system.cpu.committedOps                      77599507                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60307912                       # Number of Instructions Simulated
system.cpu.cpi                               7.823400                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.823400                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.127822                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.127822                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                550176555                       # number of integer regfile reads
system.cpu.int_regfile_writes                88426576                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8298                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2914                       # number of floating regfile writes
system.cpu.misc_regfile_reads                30119271                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 831902                       # number of misc regfile writes
system.cpu.icache.replacements                 980182                       # number of replacements
system.cpu.icache.tagsinuse                511.616610                       # Cycle average of tags in use
system.cpu.icache.total_refs                 11263184                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 980694                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  11.484912                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6410377000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.616610                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999251                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999251                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11263184                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11263184                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11263184                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11263184                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11263184                       # number of overall hits
system.cpu.icache.overall_hits::total        11263184                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1060219                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1060219                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1060219                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1060219                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1060219                       # number of overall misses
system.cpu.icache.overall_misses::total       1060219                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14018220995                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14018220995                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14018220995                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14018220995                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14018220995                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14018220995                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12323403                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12323403                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12323403                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12323403                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12323403                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12323403                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.086033                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.086033                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.086033                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.086033                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.086033                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.086033                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13222.005072                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13222.005072                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13222.005072                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13222.005072                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13222.005072                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13222.005072                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4586                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          802                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               300                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    15.286667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          802                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79489                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79489                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79489                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79489                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79489                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79489                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       980730                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       980730                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       980730                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       980730                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       980730                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       980730                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11392389495                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11392389495                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11392389495                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11392389495                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11392389495                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11392389495                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7555000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7555000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7555000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7555000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.079583                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.079583                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.079583                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.079583                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.079583                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.079583                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11616.234331                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11616.234331                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11616.234331                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11616.234331                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11616.234331                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11616.234331                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 64360                       # number of replacements
system.cpu.l2cache.tagsinuse             51336.859008                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1885213                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                129758                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 14.528684                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          2523139048000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36935.695243                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    23.234452                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.003892                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   8162.031134                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6215.894286                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.563594                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000355                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.124543                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.094847                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.783338                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52172                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10475                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       967239                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       386976                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1416862                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607588                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607588                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           42                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           42                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112931                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112931                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52172                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10475                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       967239                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       499907                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1529793                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52172                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10475                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       967239                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       499907                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1529793                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           36                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12355                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10700                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23094                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2920                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2920                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133206                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133206                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           36                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12355                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143906                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156300                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           36                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            3                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12355                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143906                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156300                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2484000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       186500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    703826000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    629251500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1335748000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       410500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       410500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6753390000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6753390000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2484000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       186500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    703826000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7382641500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8089138000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2484000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       186500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    703826000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7382641500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8089138000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52208                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10478                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       979594                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397676                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1439956                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607588                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607588                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2962                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2962                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246137                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246137                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52208                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10478                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       979594                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643813                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1686093                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52208                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10478                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       979594                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643813                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1686093                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000690                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000286                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012612                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026906                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016038                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.985820                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.985820                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541186                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541186                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000690                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000286                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012612                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223521                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092700                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000690                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000286                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012612                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223521                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092700                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        69000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62166.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56966.895994                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58808.551402                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57839.612020                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   140.582192                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   140.582192                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50698.842394                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50698.842394                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        69000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62166.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56966.895994                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51301.832446                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51753.921945                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        69000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62166.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56966.895994                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51301.832446                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51753.921945                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59114                       # number of writebacks
system.cpu.l2cache.writebacks::total            59114                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           72                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           36                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            3                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12343                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10640                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23022                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133206                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133206                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           36                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            3                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12343                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143846                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156228                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           36                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            3                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12343                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143846                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156228                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2033785                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       149502                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    549600048                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    494356239                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1046139574                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29202920                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29202920                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5093264625                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5093264625                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2033785                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       149502                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    549600048                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5587620864                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6139404199                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2033785                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       149502                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    549600048                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5587620864                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6139404199                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      5080830                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002364267                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007445097                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  26884342911                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  26884342911                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      5080830                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193891788008                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000690                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000286                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012600                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026755                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015988                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.985820                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.985820                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541186                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541186                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000690                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000286                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012600                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223428                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092657                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000690                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000286                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012600                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223428                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092657                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        49834                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44527.266305                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.052538                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45440.864130                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38236.000068                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38236.000068                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        49834                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44527.266305                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38844.464664                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39297.719993                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        49834                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44527.266305                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38844.464664                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39297.719993                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643301                       # number of replacements
system.cpu.dcache.tagsinuse                511.992821                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21506564                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 643813                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.404986                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               42245000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.992821                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13753913                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13753913                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7259030                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7259030                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242896                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242896                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247606                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247606                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21012943                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21012943                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21012943                       # number of overall hits
system.cpu.dcache.overall_hits::total        21012943                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       737130                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        737130                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2963360                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2963360                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13521                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13521                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3700490                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3700490                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3700490                       # number of overall misses
system.cpu.dcache.overall_misses::total       3700490                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9747104000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9747104000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104655662232                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 104655662232                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    180718000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    180718000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       192000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       192000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 114402766232                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 114402766232                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 114402766232                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 114402766232                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14491043                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14491043                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222390                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222390                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256417                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256417                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247618                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247618                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24713433                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24713433                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24713433                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24713433                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050868                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050868                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289889                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289889                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052731                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052731                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149736                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149736                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149736                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149736                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        16000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        16000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30915.572325                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30915.572325                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        30983                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        18747                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2620                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             251                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.825573                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    74.689243                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607588                       # number of writebacks
system.cpu.dcache.writebacks::total            607588                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       351544                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       351544                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2714338                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2714338                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1354                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1354                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3065882                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3065882                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3065882                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3065882                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385586                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385586                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249022                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12167                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12167                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634608                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634608                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634608                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634608                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4803296500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4803296500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8203666916                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8203666916                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    141299500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    141299500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       168000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       168000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13006963416                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  13006963416                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13006963416                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  13006963416                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  36699724336                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  36699724336                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026609                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026609                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024360                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024360                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047450                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047450                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025679                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025679                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025679                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025679                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        14000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        14000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1229535673761                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83046                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------