2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.525141 # Number of seconds simulated
4 sim_ticks 2525141046500 # Number of ticks simulated
5 final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 50522 # Simulator instruction rate (inst/s)
8 host_op_rate 65007 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2115457252 # Simulator tick rate (ticks/s)
10 host_mem_usage 427804 # Number of bytes of host memory used
11 host_seconds 1193.66 # Real time elapsed on the host
12 sim_insts 60305756 # Number of instructions simulated
13 sim_ops 77596741 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory
25 system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory
32 system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory
34 system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.readReqs 15096843 # Number of read requests accepted
53 system.physmem.writeReqs 813143 # Number of write requests accepted
54 system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue
55 system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue
56 system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM
57 system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue
58 system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM
59 system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side
60 system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side
61 system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue
62 system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one
63 system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write
64 system.physmem.perBankRdBursts::0 943582 # Per bank write bursts
65 system.physmem.perBankRdBursts::1 943145 # Per bank write bursts
66 system.physmem.perBankRdBursts::2 939291 # Per bank write bursts
67 system.physmem.perBankRdBursts::3 939307 # Per bank write bursts
68 system.physmem.perBankRdBursts::4 943115 # Per bank write bursts
69 system.physmem.perBankRdBursts::5 943141 # Per bank write bursts
70 system.physmem.perBankRdBursts::6 939138 # Per bank write bursts
71 system.physmem.perBankRdBursts::7 938546 # Per bank write bursts
72 system.physmem.perBankRdBursts::8 943996 # Per bank write bursts
73 system.physmem.perBankRdBursts::9 943390 # Per bank write bursts
74 system.physmem.perBankRdBursts::10 938426 # Per bank write bursts
75 system.physmem.perBankRdBursts::11 937974 # Per bank write bursts
76 system.physmem.perBankRdBursts::12 943928 # Per bank write bursts
77 system.physmem.perBankRdBursts::13 943533 # Per bank write bursts
78 system.physmem.perBankRdBursts::14 939234 # Per bank write bursts
79 system.physmem.perBankRdBursts::15 938672 # Per bank write bursts
80 system.physmem.perBankWrBursts::0 6704 # Per bank write bursts
81 system.physmem.perBankWrBursts::1 6457 # Per bank write bursts
82 system.physmem.perBankWrBursts::2 6598 # Per bank write bursts
83 system.physmem.perBankWrBursts::3 6635 # Per bank write bursts
84 system.physmem.perBankWrBursts::4 6561 # Per bank write bursts
85 system.physmem.perBankWrBursts::5 6794 # Per bank write bursts
86 system.physmem.perBankWrBursts::6 6789 # Per bank write bursts
87 system.physmem.perBankWrBursts::7 6723 # Per bank write bursts
88 system.physmem.perBankWrBursts::8 7136 # Per bank write bursts
89 system.physmem.perBankWrBursts::9 6877 # Per bank write bursts
90 system.physmem.perBankWrBursts::10 6538 # Per bank write bursts
91 system.physmem.perBankWrBursts::11 6183 # Per bank write bursts
92 system.physmem.perBankWrBursts::12 7149 # Per bank write bursts
93 system.physmem.perBankWrBursts::13 6765 # Per bank write bursts
94 system.physmem.perBankWrBursts::14 7038 # Per bank write bursts
95 system.physmem.perBankWrBursts::15 6899 # Per bank write bursts
96 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
97 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
98 system.physmem.totGap 2525139929000 # Total gap between requests
99 system.physmem.readPktSize::0 0 # Read request sizes (log2)
100 system.physmem.readPktSize::1 0 # Read request sizes (log2)
101 system.physmem.readPktSize::2 36 # Read request sizes (log2)
102 system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
103 system.physmem.readPktSize::4 0 # Read request sizes (log2)
104 system.physmem.readPktSize::5 0 # Read request sizes (log2)
105 system.physmem.readPktSize::6 154599 # Read request sizes (log2)
106 system.physmem.writePktSize::0 0 # Write request sizes (log2)
107 system.physmem.writePktSize::1 0 # Write request sizes (log2)
108 system.physmem.writePktSize::2 754018 # Write request sizes (log2)
109 system.physmem.writePktSize::3 0 # Write request sizes (log2)
110 system.physmem.writePktSize::4 0 # Write request sizes (log2)
111 system.physmem.writePktSize::5 0 # Write request sizes (log2)
112 system.physmem.writePktSize::6 59125 # Write request sizes (log2)
113 system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
145 system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
177 system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation
372 system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation
373 system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation
374 system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation
375 system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation
376 system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation
377 system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation
378 system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation
379 system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation
380 system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation
381 system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation
382 system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation
383 system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation
384 system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation
385 system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation
386 system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation
387 system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation
388 system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation
389 system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation
390 system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation
391 system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation
392 system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation
393 system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation
394 system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation
395 system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation
396 system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation
397 system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation
398 system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation
399 system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation
400 system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation
401 system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation
402 system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation
403 system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation
404 system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation
405 system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation
406 system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation
407 system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation
408 system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation
409 system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation
410 system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation
411 system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation
412 system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation
413 system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation
414 system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation
415 system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation
416 system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation
417 system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation
418 system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation
419 system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation
420 system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation
421 system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation
422 system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation
423 system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation
424 system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation
425 system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation
426 system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation
427 system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation
428 system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation
429 system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation
430 system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation
431 system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation
432 system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation
433 system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation
434 system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation
435 system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation
436 system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation
437 system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation
438 system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation
439 system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation
440 system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation
441 system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation
442 system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation
443 system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation
444 system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation
445 system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation
446 system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation
447 system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation
448 system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation
449 system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation
450 system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation
451 system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation
452 system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation
453 system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation
454 system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation
455 system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation
456 system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation
457 system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation
458 system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation
459 system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation
460 system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation
461 system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation
462 system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation
463 system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation
464 system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation
465 system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation
466 system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation
467 system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation
468 system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation
469 system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation
470 system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation
471 system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation
472 system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation
473 system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation
474 system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation
475 system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation
476 system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation
477 system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation
478 system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation
479 system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation
480 system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation
481 system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation
482 system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation
483 system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation
484 system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation
485 system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation
486 system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation
487 system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation
488 system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation
489 system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation
490 system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation
491 system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation
492 system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation
493 system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation
494 system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation
495 system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation
496 system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation
497 system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation
498 system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation
499 system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation
500 system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation
501 system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation
502 system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation
503 system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation
504 system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation
505 system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation
506 system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation
507 system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation
508 system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation
509 system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation
520 system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation
521 system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation
522 system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation
523 system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation
524 system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation
525 system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation
526 system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation
527 system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation
528 system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation
529 system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation
530 system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation
531 system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation
532 system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation
533 system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation
534 system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation
535 system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation
536 system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation
537 system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation
538 system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation
539 system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation
540 system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation
541 system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation
542 system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation
543 system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation
544 system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation
545 system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation
546 system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation
547 system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation
548 system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation
549 system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation
550 system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation
551 system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation
552 system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation
553 system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation
554 system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation
555 system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation
556 system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation
557 system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation
558 system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation
559 system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation
560 system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation
561 system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation
562 system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation
563 system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation
564 system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation
565 system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation
566 system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation
567 system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation
568 system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation
569 system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation
570 system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation
571 system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation
572 system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation
573 system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation
574 system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation
575 system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation
576 system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation
577 system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation
578 system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation
579 system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation
580 system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation
581 system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation
582 system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation
583 system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation
584 system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation
585 system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation
586 system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation
587 system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation
588 system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation
589 system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation
590 system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation
591 system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation
592 system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation
593 system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation
594 system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation
595 system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation
596 system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation
597 system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation
598 system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation
599 system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation
600 system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation
601 system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation
602 system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation
603 system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation
604 system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation
605 system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation
606 system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation
607 system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation
608 system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation
609 system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation
610 system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation
611 system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation
612 system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation
613 system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation
614 system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation
615 system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation
616 system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation
617 system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation
618 system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation
619 system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation
620 system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation
621 system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation
622 system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation
623 system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation
624 system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation
625 system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation
626 system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation
627 system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation
628 system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation
629 system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation
630 system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation
631 system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation
632 system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation
633 system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation
634 system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation
635 system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation
636 system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation
637 system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation
638 system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation
639 system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation
640 system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation
641 system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation
642 system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation
643 system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation
644 system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation
645 system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation
646 system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation
647 system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation
648 system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation
649 system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation
650 system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation
651 system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation
652 system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation
653 system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation
654 system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation
655 system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation
656 system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation
657 system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation
658 system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation
659 system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation
660 system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation
661 system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation
662 system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation
663 system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation
664 system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation
665 system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation
666 system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation
667 system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation
668 system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation
669 system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation
670 system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation
671 system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation
672 system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation
673 system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation
674 system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation
675 system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation
676 system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation
677 system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation
678 system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation
679 system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation
680 system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation
681 system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation
682 system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation
683 system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation
684 system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation
685 system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation
686 system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation
687 system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation
688 system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation
689 system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation
690 system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation
691 system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation
692 system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation
693 system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation
694 system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation
695 system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation
696 system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation
697 system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation
698 system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation
699 system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation
700 system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation
701 system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation
702 system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation
703 system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation
704 system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation
705 system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation
706 system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation
707 system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation
708 system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation
709 system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation
710 system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation
711 system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation
712 system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation
713 system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation
714 system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation
715 system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation
716 system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation
717 system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation
718 system.physmem.totQLat 365610387500 # Total ticks spent queuing
719 system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM
720 system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers
721 system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks
722 system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst
723 system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst
724 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
725 system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst
726 system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s
727 system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
728 system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s
729 system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
730 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
731 system.physmem.busUtil 3.00 # Data bus utilization in percentage
732 system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
733 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
734 system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
735 system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing
736 system.physmem.readRowHits 14986740 # Number of row buffer hits during reads
737 system.physmem.writeRowHits 93410 # Number of row buffer hits during writes
738 system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
739 system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes
740 system.physmem.avgGap 158714.15 # Average gap between requests
741 system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
742 system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state
743 system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
744 system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
745 system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
746 system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
747 system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
748 system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
749 system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
750 system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
751 system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
752 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
753 system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
754 system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
755 system.membus.throughput 54899945 # Throughput (bytes/s)
756 system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
757 system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
758 system.membus.trans_dist::WriteReq 763332 # Transaction distribution
759 system.membus.trans_dist::WriteResp 763332 # Transaction distribution
760 system.membus.trans_dist::Writeback 59125 # Transaction distribution
761 system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution
762 system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
763 system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution
764 system.membus.trans_dist::ReadExReq 131442 # Transaction distribution
765 system.membus.trans_dist::ReadExResp 131442 # Transaction distribution
766 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes)
767 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
768 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
769 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
770 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes)
771 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes)
772 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
773 system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
774 system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes)
775 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes)
776 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
777 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
778 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
779 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes)
780 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes)
781 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
782 system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
783 system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes)
784 system.membus.data_through_bus 138630105 # Total data (bytes)
785 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
786 system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks)
787 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
788 system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
789 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
790 system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks)
791 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
792 system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
793 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
794 system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks)
795 system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
796 system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks)
797 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
798 system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks)
799 system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
800 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
801 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
802 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
803 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
804 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
805 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
806 system.iobus.throughput 48285606 # Throughput (bytes/s)
807 system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution
808 system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution
809 system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
810 system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
811 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
812 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
813 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
814 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
815 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
816 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
817 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
818 system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
819 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
820 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
821 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
822 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
823 system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
824 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
825 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
826 system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
827 system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
828 system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
829 system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
830 system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
831 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
832 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
833 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
834 system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes)
835 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
836 system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
837 system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes)
838 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
839 system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
840 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
841 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
842 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
843 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
844 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
845 system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
846 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
847 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
848 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
849 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
850 system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
851 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
852 system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
853 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
854 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
855 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
856 system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
857 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
858 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
859 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
860 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
861 system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes)
862 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
863 system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
864 system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes)
865 system.iobus.data_through_bus 121927965 # Total data (bytes)
866 system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
867 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
868 system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
869 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
870 system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
871 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
872 system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
873 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
874 system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
875 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
876 system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
877 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
878 system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
879 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
880 system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
881 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
882 system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
883 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
884 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
885 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
886 system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
887 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
888 system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
889 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
890 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
891 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
892 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
893 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
894 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
895 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
896 system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
897 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
898 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
899 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
900 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
901 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
902 system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
903 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
904 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
905 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
906 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
907 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
908 system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
909 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
910 system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
911 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
912 system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
913 system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
914 system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks)
915 system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
916 system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks)
917 system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
918 system.cpu.branchPred.lookups 14384905 # Number of BP lookups
919 system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted
920 system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect
921 system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups
922 system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits
923 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
924 system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage
925 system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target.
926 system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions.
927 system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
928 system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
929 system.cpu.checker.dtb.read_hits 14986852 # DTB read hits
930 system.cpu.checker.dtb.read_misses 7306 # DTB read misses
931 system.cpu.checker.dtb.write_hits 11227410 # DTB write hits
932 system.cpu.checker.dtb.write_misses 2191 # DTB write misses
933 system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
934 system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
935 system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
936 system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
937 system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB
938 system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
939 system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch
940 system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
941 system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
942 system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses
943 system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses
944 system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
945 system.cpu.checker.dtb.hits 26214262 # DTB hits
946 system.cpu.checker.dtb.misses 9497 # DTB misses
947 system.cpu.checker.dtb.accesses 26223759 # DTB accesses
948 system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits
949 system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
950 system.cpu.checker.itb.read_hits 0 # DTB read hits
951 system.cpu.checker.itb.read_misses 0 # DTB read misses
952 system.cpu.checker.itb.write_hits 0 # DTB write hits
953 system.cpu.checker.itb.write_misses 0 # DTB write misses
954 system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
955 system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
956 system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
957 system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
958 system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
959 system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
960 system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
961 system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
962 system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
963 system.cpu.checker.itb.read_accesses 0 # DTB read accesses
964 system.cpu.checker.itb.write_accesses 0 # DTB write accesses
965 system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses
966 system.cpu.checker.itb.hits 61479743 # DTB hits
967 system.cpu.checker.itb.misses 4471 # DTB misses
968 system.cpu.checker.itb.accesses 61484214 # DTB accesses
969 system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated
970 system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
971 system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
972 system.cpu.dtb.inst_hits 0 # ITB inst hits
973 system.cpu.dtb.inst_misses 0 # ITB inst misses
974 system.cpu.dtb.read_hits 51179212 # DTB read hits
975 system.cpu.dtb.read_misses 64531 # DTB read misses
976 system.cpu.dtb.write_hits 11698539 # DTB write hits
977 system.cpu.dtb.write_misses 15837 # DTB write misses
978 system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
979 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
980 system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
981 system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
982 system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB
983 system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions
984 system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
985 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
986 system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions
987 system.cpu.dtb.read_accesses 51243743 # DTB read accesses
988 system.cpu.dtb.write_accesses 11714376 # DTB write accesses
989 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
990 system.cpu.dtb.hits 62877751 # DTB hits
991 system.cpu.dtb.misses 80368 # DTB misses
992 system.cpu.dtb.accesses 62958119 # DTB accesses
993 system.cpu.itb.inst_hits 11513998 # ITB inst hits
994 system.cpu.itb.inst_misses 11344 # ITB inst misses
995 system.cpu.itb.read_hits 0 # DTB read hits
996 system.cpu.itb.read_misses 0 # DTB read misses
997 system.cpu.itb.write_hits 0 # DTB write hits
998 system.cpu.itb.write_misses 0 # DTB write misses
999 system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
1000 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1001 system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
1002 system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
1003 system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB
1004 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1005 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1006 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1007 system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions
1008 system.cpu.itb.read_accesses 0 # DTB read accesses
1009 system.cpu.itb.write_accesses 0 # DTB write accesses
1010 system.cpu.itb.inst_accesses 11525342 # ITB inst accesses
1011 system.cpu.itb.hits 11513998 # DTB hits
1012 system.cpu.itb.misses 11344 # DTB misses
1013 system.cpu.itb.accesses 11525342 # DTB accesses
1014 system.cpu.numCycles 474882944 # number of cpu cycles simulated
1015 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
1016 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
1017 system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss
1018 system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed
1019 system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered
1020 system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken
1021 system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked
1022 system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing
1023 system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb
1024 system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked
1025 system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1026 system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps
1027 system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions
1028 system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR
1029 system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched
1030 system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed
1031 system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed
1032 system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total)
1033 system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total)
1034 system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total)
1035 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1036 system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total)
1037 system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total)
1038 system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total)
1039 system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total)
1040 system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total)
1041 system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total)
1042 system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total)
1043 system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total)
1044 system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total)
1045 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1046 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1047 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1048 system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total)
1049 system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle
1050 system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle
1051 system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle
1052 system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked
1053 system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running
1054 system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking
1055 system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing
1056 system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch
1057 system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction
1058 system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode
1059 system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode
1060 system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing
1061 system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle
1062 system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking
1063 system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst
1064 system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running
1065 system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking
1066 system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename
1067 system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full
1068 system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full
1069 system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full
1070 system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers
1071 system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed
1072 system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made
1073 system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups
1074 system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups
1075 system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed
1076 system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing
1077 system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed
1078 system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed
1079 system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer
1080 system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit.
1081 system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit.
1082 system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads.
1083 system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores.
1084 system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec)
1085 system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ
1086 system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued
1087 system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued
1088 system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling
1089 system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph
1090 system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed
1091 system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle
1092 system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle
1093 system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle
1094 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1095 system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle
1096 system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle
1097 system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle
1098 system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle
1099 system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle
1100 system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle
1101 system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle
1102 system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle
1103 system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle
1104 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1105 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1106 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1107 system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle
1108 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1109 system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available
1110 system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available
1111 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
1112 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
1113 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
1114 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available
1115 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available
1116 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available
1117 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
1118 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available
1119 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available
1120 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available
1121 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available
1122 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available
1123 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available
1124 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available
1125 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available
1126 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available
1127 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available
1128 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available
1129 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available
1130 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available
1131 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available
1132 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available
1133 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available
1134 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available
1135 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
1136 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
1137 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
1138 system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available
1139 system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available
1140 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1141 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1142 system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
1143 system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued
1144 system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued
1145 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
1146 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
1147 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
1148 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
1149 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
1150 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
1151 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
1152 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
1153 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
1154 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
1155 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
1156 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
1157 system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued
1158 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
1159 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
1160 system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
1161 system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued
1162 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
1163 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
1164 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
1165 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
1166 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
1167 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
1168 system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued
1169 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
1170 system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued
1171 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
1172 system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued
1173 system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued
1174 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1175 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1176 system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued
1177 system.cpu.iq.rate 0.258795 # Inst issue rate
1178 system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested
1179 system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst)
1180 system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads
1181 system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes
1182 system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses
1183 system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads
1184 system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes
1185 system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses
1186 system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses
1187 system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses
1188 system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores
1189 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1190 system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed
1191 system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed
1192 system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations
1193 system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed
1194 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1195 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1196 system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled
1197 system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked
1198 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1199 system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing
1200 system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking
1201 system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking
1202 system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ
1203 system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch
1204 system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions
1205 system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions
1206 system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions
1207 system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall
1208 system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall
1209 system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations
1210 system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly
1211 system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly
1212 system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute
1213 system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions
1214 system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed
1215 system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute
1216 system.cpu.iew.exec_swp 0 # number of swp insts executed
1217 system.cpu.iew.exec_nop 221869 # number of nop insts executed
1218 system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed
1219 system.cpu.iew.exec_branches 11475076 # Number of branches executed
1220 system.cpu.iew.exec_stores 12210518 # Number of stores executed
1221 system.cpu.iew.exec_rate 0.254424 # Inst execution rate
1222 system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit
1223 system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back
1224 system.cpu.iew.wb_producers 47026181 # num instructions producing a value
1225 system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value
1226 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1227 system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle
1228 system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back
1229 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1230 system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit
1231 system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
1232 system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted
1233 system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle
1234 system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle
1235 system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle
1236 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1237 system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle
1238 system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle
1239 system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle
1240 system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle
1241 system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle
1242 system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle
1243 system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle
1244 system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle
1245 system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle
1246 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1247 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1248 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1249 system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle
1250 system.cpu.commit.committedInsts 60456137 # Number of instructions committed
1251 system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed
1252 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
1253 system.cpu.commit.refs 27385736 # Number of memory references committed
1254 system.cpu.commit.loads 15654008 # Number of loads committed
1255 system.cpu.commit.membars 403573 # Number of memory barriers committed
1256 system.cpu.commit.branches 9961077 # Number of branches committed
1257 system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
1258 system.cpu.commit.int_insts 68852562 # Number of committed integer instructions.
1259 system.cpu.commit.function_calls 991208 # Number of function calls committed.
1260 system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached
1261 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
1262 system.cpu.rob.rob_reads 240636318 # The number of ROB reads
1263 system.cpu.rob.rob_writes 195934369 # The number of ROB writes
1264 system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself
1265 system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling
1266 system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1267 system.cpu.committedInsts 60305756 # Number of Instructions Simulated
1268 system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated
1269 system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated
1270 system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction
1271 system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads
1272 system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle
1273 system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads
1274 system.cpu.int_regfile_reads 547208472 # number of integer regfile reads
1275 system.cpu.int_regfile_writes 87526189 # number of integer regfile writes
1276 system.cpu.fp_regfile_reads 8624 # number of floating regfile reads
1277 system.cpu.fp_regfile_writes 3008 # number of floating regfile writes
1278 system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads
1279 system.cpu.misc_regfile_writes 831837 # number of misc regfile writes
1280 system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s)
1281 system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution
1282 system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution
1283 system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
1284 system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
1285 system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution
1286 system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution
1287 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
1288 system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution
1289 system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution
1290 system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution
1291 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes)
1292 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes)
1293 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes)
1294 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes)
1295 system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes)
1296 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes)
1297 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes)
1298 system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes)
1299 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes)
1300 system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes)
1301 system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes)
1302 system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes)
1303 system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks)
1304 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1305 system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks)
1306 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1307 system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks)
1308 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1309 system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks)
1310 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1311 system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks)
1312 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1313 system.cpu.icache.tags.replacements 980741 # number of replacements
1314 system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use
1315 system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks.
1316 system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks.
1317 system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks.
1318 system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit.
1319 system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor
1320 system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy
1321 system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy
1322 system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits
1323 system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits
1324 system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits
1325 system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits
1326 system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits
1327 system.cpu.icache.overall_hits::total 10449649 # number of overall hits
1328 system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses
1329 system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses
1330 system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses
1331 system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses
1332 system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses
1333 system.cpu.icache.overall_misses::total 1060761 # number of overall misses
1334 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles
1335 system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles
1336 system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles
1337 system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles
1338 system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles
1339 system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles
1340 system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses)
1341 system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses)
1342 system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses
1343 system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses
1344 system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses
1345 system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses
1346 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses
1347 system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses
1348 system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses
1349 system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses
1350 system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses
1351 system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses
1352 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency
1353 system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency
1354 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency
1355 system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency
1356 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency
1357 system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency
1358 system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked
1359 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1360 system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked
1361 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1362 system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked
1363 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1364 system.cpu.icache.fast_writes 0 # number of fast writes performed
1365 system.cpu.icache.cache_copies 0 # number of cache copies performed
1366 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits
1367 system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits
1368 system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits
1369 system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits
1370 system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits
1371 system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits
1372 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses
1373 system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses
1374 system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses
1375 system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses
1376 system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses
1377 system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses
1378 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles
1379 system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles
1380 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles
1381 system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles
1382 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles
1383 system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles
1384 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles
1385 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles
1386 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles
1387 system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles
1388 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses
1389 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses
1390 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses
1391 system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses
1392 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses
1393 system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses
1394 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency
1395 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency
1396 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency
1397 system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency
1398 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency
1399 system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency
1400 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1401 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1402 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1403 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1404 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1405 system.cpu.l2cache.tags.replacements 64371 # number of replacements
1406 system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use
1407 system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks.
1408 system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks.
1409 system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks.
1410 system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit.
1411 system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor
1412 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor
1413 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor
1414 system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor
1415 system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor
1416 system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy
1417 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy
1418 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
1419 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy
1420 system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy
1421 system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy
1422 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits
1423 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits
1424 system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits
1425 system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits
1426 system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits
1427 system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits
1428 system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits
1429 system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits
1430 system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits
1431 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
1432 system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
1433 system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits
1434 system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits
1435 system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits
1436 system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits
1437 system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits
1438 system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits
1439 system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits
1440 system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits
1441 system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits
1442 system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits
1443 system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits
1444 system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits
1445 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
1446 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
1447 system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses
1448 system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses
1449 system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses
1450 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses
1451 system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses
1452 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
1453 system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
1454 system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses
1455 system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses
1456 system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
1457 system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
1458 system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses
1459 system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses
1460 system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
1461 system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
1462 system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
1463 system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses
1464 system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses
1465 system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
1466 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles
1467 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles
1468 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles
1469 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles
1470 system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles
1471 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles
1472 system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles
1473 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles
1474 system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles
1475 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles
1476 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles
1477 system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles
1478 system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles
1479 system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles
1480 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles
1481 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles
1482 system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles
1483 system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles
1484 system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles
1485 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses)
1486 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses)
1487 system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses)
1488 system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses)
1489 system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses)
1490 system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses)
1491 system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses)
1492 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses)
1493 system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses)
1494 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
1495 system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
1496 system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses)
1497 system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses)
1498 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses
1499 system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses
1500 system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses
1501 system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses
1502 system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses
1503 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses
1504 system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses
1505 system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses
1506 system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses
1507 system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses
1508 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses
1509 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses
1510 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses
1511 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses
1512 system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses
1513 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses
1514 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses
1515 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
1516 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
1517 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses
1518 system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses
1519 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses
1520 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses
1521 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses
1522 system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses
1523 system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses
1524 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses
1525 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses
1526 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses
1527 system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses
1528 system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses
1529 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency
1530 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency
1531 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency
1532 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency
1533 system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency
1534 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency
1535 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency
1536 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency
1537 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency
1538 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency
1539 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency
1540 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency
1541 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency
1542 system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency
1543 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency
1544 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency
1545 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency
1546 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency
1547 system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency
1548 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1549 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1550 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1551 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1552 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1553 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1554 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1555 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1556 system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks
1557 system.cpu.l2cache.writebacks::total 59125 # number of writebacks
1558 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
1559 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
1560 system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
1561 system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
1562 system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
1563 system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
1564 system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
1565 system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
1566 system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
1567 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
1568 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
1569 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses
1570 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
1571 system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses
1572 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses
1573 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses
1574 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
1575 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
1576 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses
1577 system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses
1578 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
1579 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
1580 system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses
1581 system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses
1582 system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses
1583 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
1584 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
1585 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses
1586 system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses
1587 system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses
1588 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles
1589 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles
1590 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles
1591 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles
1592 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles
1593 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles
1594 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles
1595 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
1596 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
1597 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles
1598 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles
1599 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles
1600 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles
1601 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles
1602 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles
1603 system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles
1604 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles
1605 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles
1606 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles
1607 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles
1608 system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles
1609 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles
1610 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles
1611 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles
1612 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles
1613 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles
1614 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles
1615 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles
1616 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles
1617 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses
1618 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses
1619 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses
1620 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses
1621 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses
1622 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses
1623 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses
1624 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
1625 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
1626 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses
1627 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses
1628 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses
1629 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses
1630 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses
1631 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses
1632 system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses
1633 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses
1634 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses
1635 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses
1636 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses
1637 system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses
1638 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency
1639 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency
1640 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency
1641 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency
1642 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency
1643 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency
1644 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency
1645 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
1646 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
1647 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency
1648 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency
1649 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency
1650 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency
1651 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency
1652 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency
1653 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency
1654 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency
1655 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency
1656 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency
1657 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency
1658 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency
1659 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1660 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1661 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1662 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1663 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1664 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1665 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1666 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1667 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1668 system.cpu.dcache.tags.replacements 643382 # number of replacements
1669 system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use
1670 system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks.
1671 system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks.
1672 system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks.
1673 system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit.
1674 system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor
1675 system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
1676 system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
1677 system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits
1678 system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits
1679 system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits
1680 system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits
1681 system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits
1682 system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits
1683 system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
1684 system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
1685 system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits
1686 system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits
1687 system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits
1688 system.cpu.dcache.overall_hits::total 21010251 # number of overall hits
1689 system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses
1690 system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses
1691 system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses
1692 system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses
1693 system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses
1694 system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses
1695 system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
1696 system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
1697 system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses
1698 system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses
1699 system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses
1700 system.cpu.dcache.overall_misses::total 3701471 # number of overall misses
1701 system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles
1702 system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles
1703 system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles
1704 system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles
1705 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles
1706 system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles
1707 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
1708 system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
1709 system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles
1710 system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles
1711 system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles
1712 system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles
1713 system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses)
1714 system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses)
1715 system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses)
1716 system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses)
1717 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses)
1718 system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses)
1719 system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
1720 system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
1721 system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses
1722 system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses
1723 system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses
1724 system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses
1725 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses
1726 system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses
1727 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses
1728 system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses
1729 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses
1730 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses
1731 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
1732 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
1733 system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses
1734 system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses
1735 system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses
1736 system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses
1737 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency
1738 system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency
1739 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency
1740 system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency
1741 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency
1742 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency
1743 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
1744 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
1745 system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency
1746 system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency
1747 system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency
1748 system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency
1749 system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked
1750 system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked
1751 system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked
1752 system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked
1753 system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked
1754 system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked
1755 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1756 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1757 system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks
1758 system.cpu.dcache.writebacks::total 607699 # number of writebacks
1759 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits
1760 system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits
1761 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits
1762 system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits
1763 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits
1764 system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits
1765 system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits
1766 system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits
1767 system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits
1768 system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits
1769 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses
1770 system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses
1771 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses
1772 system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses
1773 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
1774 system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
1775 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
1776 system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
1777 system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses
1778 system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses
1779 system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses
1780 system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses
1781 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles
1782 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles
1783 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles
1784 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles
1785 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles
1786 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles
1787 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
1788 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
1789 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles
1790 system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles
1791 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles
1792 system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles
1793 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles
1794 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles
1795 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles
1796 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles
1797 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles
1798 system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles
1799 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses
1800 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses
1801 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses
1802 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses
1803 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses
1804 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses
1805 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
1806 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
1807 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
1808 system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
1809 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
1810 system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
1811 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency
1812 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency
1813 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency
1814 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency
1815 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency
1816 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency
1817 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
1818 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
1819 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency
1820 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency
1821 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency
1822 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency
1823 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1824 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1825 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1826 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1827 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1828 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1829 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1830 system.iocache.tags.replacements 0 # number of replacements
1831 system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1832 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1833 system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1834 system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1835 system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1836 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1837 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1838 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1839 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1840 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1841 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1842 system.iocache.fast_writes 0 # number of fast writes performed
1843 system.iocache.cache_copies 0 # number of cache copies performed
1844 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles
1845 system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles
1846 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles
1847 system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles
1848 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1849 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1850 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1851 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1852 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1853 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1854 system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
1856 ---------- End Simulation Statistics ----------
projects / gem5.git / blob