2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.533144 # Number of seconds simulated
4 sim_ticks 2533143504000 # Number of ticks simulated
5 final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 65433 # Simulator instruction rate (inst/s)
8 host_op_rate 84194 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2748425484 # Simulator tick rate (ticks/s)
10 host_mem_usage 408856 # Number of bytes of host memory used
11 host_seconds 921.67 # Real time elapsed on the host
12 sim_insts 60307579 # Number of instructions simulated
13 sim_ops 77599125 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory
25 system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory
32 system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory
34 system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.readReqs 15096820 # Total number of read requests seen
53 system.physmem.writeReqs 813121 # Total number of write requests seen
54 system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady
55 system.physmem.bytesRead 966196480 # Total number of bytes read from memory
56 system.physmem.bytesWritten 52039744 # Total number of bytes written to memory
57 system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize()
58 system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize()
59 system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q
60 system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed
61 system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis
74 system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
75 system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis
76 system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis
77 system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis
90 system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis
91 system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis
92 system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
93 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
94 system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry
95 system.physmem.totGap 2533142364000 # Total gap between requests
96 system.physmem.readPktSize::0 0 # Categorize read packet sizes
97 system.physmem.readPktSize::1 0 # Categorize read packet sizes
98 system.physmem.readPktSize::2 36 # Categorize read packet sizes
99 system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
100 system.physmem.readPktSize::4 0 # Categorize read packet sizes
101 system.physmem.readPktSize::5 0 # Categorize read packet sizes
102 system.physmem.readPktSize::6 154576 # Categorize read packet sizes
103 system.physmem.writePktSize::0 0 # Categorize write packet sizes
104 system.physmem.writePktSize::1 0 # Categorize write packet sizes
105 system.physmem.writePktSize::2 754018 # Categorize write packet sizes
106 system.physmem.writePktSize::3 0 # Categorize write packet sizes
107 system.physmem.writePktSize::4 0 # Categorize write packet sizes
108 system.physmem.writePktSize::5 0 # Categorize write packet sizes
109 system.physmem.writePktSize::6 59103 # Categorize write packet sizes
110 system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
142 system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
174 system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays
175 system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests
176 system.physmem.totBusLat 75482965000 # Total cycles spent in databus access
177 system.physmem.totBankLat 16912788750 # Total cycles spent in bank access
178 system.physmem.avgQLat 26048.65 # Average queueing delay per request
179 system.physmem.avgBankLat 1120.31 # Average bank access latency per request
180 system.physmem.avgBusLat 5000.00 # Average bus latency per request
181 system.physmem.avgMemAccLat 32168.96 # Average memory access latency
182 system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
183 system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
184 system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
185 system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
186 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
187 system.physmem.busUtil 3.14 # Data bus utilization in percentage
188 system.physmem.avgRdQLen 0.19 # Average read queue length over time
189 system.physmem.avgWrQLen 9.55 # Average write queue length over time
190 system.physmem.readRowHits 15020273 # Number of row buffer hits during reads
191 system.physmem.writeRowHits 793117 # Number of row buffer hits during writes
192 system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
193 system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
194 system.physmem.avgGap 159217.58 # Average gap between requests
195 system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
196 system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
197 system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
198 system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
199 system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
200 system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
201 system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
202 system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
203 system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
204 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
205 system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
206 system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
207 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
208 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
209 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
210 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
211 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
212 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
213 system.cpu.branchPred.lookups 14678084 # Number of BP lookups
214 system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted
215 system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect
216 system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups
217 system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits
218 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
219 system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage
220 system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target.
221 system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions.
222 system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
223 system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
224 system.cpu.checker.dtb.read_hits 14987411 # DTB read hits
225 system.cpu.checker.dtb.read_misses 7302 # DTB read misses
226 system.cpu.checker.dtb.write_hits 11227746 # DTB write hits
227 system.cpu.checker.dtb.write_misses 2189 # DTB write misses
228 system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
229 system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
230 system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
231 system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
232 system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
233 system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
234 system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
235 system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
236 system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
237 system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses
238 system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses
239 system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
240 system.cpu.checker.dtb.hits 26215157 # DTB hits
241 system.cpu.checker.dtb.misses 9491 # DTB misses
242 system.cpu.checker.dtb.accesses 26224648 # DTB accesses
243 system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits
244 system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
245 system.cpu.checker.itb.read_hits 0 # DTB read hits
246 system.cpu.checker.itb.read_misses 0 # DTB read misses
247 system.cpu.checker.itb.write_hits 0 # DTB write hits
248 system.cpu.checker.itb.write_misses 0 # DTB write misses
249 system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
250 system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
251 system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
252 system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
253 system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
254 system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
255 system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
256 system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
257 system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
258 system.cpu.checker.itb.read_accesses 0 # DTB read accesses
259 system.cpu.checker.itb.write_accesses 0 # DTB write accesses
260 system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses
261 system.cpu.checker.itb.hits 61481576 # DTB hits
262 system.cpu.checker.itb.misses 4471 # DTB misses
263 system.cpu.checker.itb.accesses 61486047 # DTB accesses
264 system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated
265 system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
266 system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
267 system.cpu.dtb.inst_hits 0 # ITB inst hits
268 system.cpu.dtb.inst_misses 0 # ITB inst misses
269 system.cpu.dtb.read_hits 51401633 # DTB read hits
270 system.cpu.dtb.read_misses 64365 # DTB read misses
271 system.cpu.dtb.write_hits 11702282 # DTB write hits
272 system.cpu.dtb.write_misses 15903 # DTB write misses
273 system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
274 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
275 system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
276 system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
277 system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB
278 system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions
279 system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch
280 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
281 system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
282 system.cpu.dtb.read_accesses 51465998 # DTB read accesses
283 system.cpu.dtb.write_accesses 11718185 # DTB write accesses
284 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
285 system.cpu.dtb.hits 63103915 # DTB hits
286 system.cpu.dtb.misses 80268 # DTB misses
287 system.cpu.dtb.accesses 63184183 # DTB accesses
288 system.cpu.itb.inst_hits 12333169 # ITB inst hits
289 system.cpu.itb.inst_misses 11311 # ITB inst misses
290 system.cpu.itb.read_hits 0 # DTB read hits
291 system.cpu.itb.read_misses 0 # DTB read misses
292 system.cpu.itb.write_hits 0 # DTB write hits
293 system.cpu.itb.write_misses 0 # DTB write misses
294 system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
295 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296 system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
297 system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
298 system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB
299 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
300 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
301 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
302 system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions
303 system.cpu.itb.read_accesses 0 # DTB read accesses
304 system.cpu.itb.write_accesses 0 # DTB write accesses
305 system.cpu.itb.inst_accesses 12344480 # ITB inst accesses
306 system.cpu.itb.hits 12333169 # DTB hits
307 system.cpu.itb.misses 11311 # DTB misses
308 system.cpu.itb.accesses 12344480 # DTB accesses
309 system.cpu.numCycles 471839315 # number of cpu cycles simulated
310 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
311 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
312 system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss
313 system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed
314 system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered
315 system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken
316 system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked
317 system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing
318 system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb
319 system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked
320 system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
321 system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps
322 system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions
323 system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR
324 system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched
325 system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed
326 system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed
327 system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle
345 system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle
346 system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle
347 system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked
348 system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running
349 system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking
350 system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing
351 system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch
352 system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction
353 system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode
354 system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode
355 system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing
356 system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle
357 system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking
358 system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst
359 system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running
360 system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking
361 system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename
362 system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full
363 system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full
364 system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full
365 system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers
366 system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed
367 system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made
368 system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups
369 system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups
370 system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed
371 system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing
372 system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed
373 system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed
374 system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer
375 system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit.
376 system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit.
377 system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads.
378 system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores.
379 system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec)
380 system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ
381 system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued
382 system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued
383 system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling
384 system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph
385 system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed
386 system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle
403 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
404 system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available
405 system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
406 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
407 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
408 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
409 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
410 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
411 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
412 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
433 system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available
434 system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available
435 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
436 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
437 system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
438 system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued
439 system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued
440 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
441 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
442 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
443 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued
444 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued
445 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued
446 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
467 system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued
468 system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued
469 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
470 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
471 system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued
472 system.cpu.iq.rate 0.263513 # Inst issue rate
473 system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested
474 system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst)
475 system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads
476 system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes
477 system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses
478 system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads
479 system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes
480 system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses
481 system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses
482 system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses
483 system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores
484 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
485 system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed
486 system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed
487 system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations
488 system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed
489 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
490 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
491 system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled
492 system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked
493 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
494 system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing
495 system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking
496 system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking
497 system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ
498 system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch
499 system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions
500 system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions
501 system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions
502 system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall
503 system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall
504 system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations
505 system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly
506 system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly
507 system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute
508 system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions
509 system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed
510 system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute
511 system.cpu.iew.exec_swp 0 # number of swp insts executed
512 system.cpu.iew.exec_nop 220929 # number of nop insts executed
513 system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed
514 system.cpu.iew.exec_branches 11562998 # Number of branches executed
515 system.cpu.iew.exec_stores 12213915 # Number of stores executed
516 system.cpu.iew.exec_rate 0.257621 # Inst execution rate
517 system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit
518 system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back
519 system.cpu.iew.wb_producers 47225460 # num instructions producing a value
520 system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value
521 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
522 system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle
523 system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back
524 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
525 system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit
526 system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards
527 system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted
528 system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle
545 system.cpu.commit.committedInsts 60457960 # Number of instructions committed
546 system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed
547 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
548 system.cpu.commit.refs 27386605 # Number of memory references committed
549 system.cpu.commit.loads 15654525 # Number of loads committed
550 system.cpu.commit.membars 403599 # Number of memory barriers committed
551 system.cpu.commit.branches 9961316 # Number of branches committed
552 system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
553 system.cpu.commit.int_insts 68854760 # Number of committed integer instructions.
554 system.cpu.commit.function_calls 991257 # Number of function calls committed.
555 system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached
556 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
557 system.cpu.rob.rob_reads 242401590 # The number of ROB reads
558 system.cpu.rob.rob_writes 202045449 # The number of ROB writes
559 system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself
560 system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling
561 system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
562 system.cpu.committedInsts 60307579 # Number of Instructions Simulated
563 system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated
564 system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated
565 system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction
566 system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads
567 system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle
568 system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads
569 system.cpu.int_regfile_reads 550352195 # number of integer regfile reads
570 system.cpu.int_regfile_writes 88467764 # number of integer regfile writes
571 system.cpu.fp_regfile_reads 8269 # number of floating regfile reads
572 system.cpu.fp_regfile_writes 2928 # number of floating regfile writes
573 system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads
574 system.cpu.misc_regfile_writes 831890 # number of misc regfile writes
575 system.cpu.icache.replacements 979593 # number of replacements
576 system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use
577 system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks.
578 system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks.
579 system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks.
580 system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
581 system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor
582 system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
583 system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
584 system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits
585 system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits
586 system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits
587 system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits
588 system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits
589 system.cpu.icache.overall_hits::total 11270072 # number of overall hits
590 system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses
591 system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses
592 system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses
593 system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses
594 system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses
595 system.cpu.icache.overall_misses::total 1059286 # number of overall misses
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597 system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles
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599 system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles
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601 system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles
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605 system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses
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607 system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses
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609 system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses
610 system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses
611 system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses
612 system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses
613 system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses
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615 system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency
616 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency
617 system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency
618 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency
619 system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency
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622 system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked
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629 system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits
630 system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits
631 system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits
632 system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits
633 system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits
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635 system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses
636 system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses
637 system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses
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639 system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses
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641 system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles
642 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles
643 system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles
644 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles
645 system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles
646 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
647 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
648 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
649 system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles
650 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses
651 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses
652 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for demand accesses
653 system.cpu.icache.demand_mshr_miss_rate::total 0.079496 # mshr miss rate for demand accesses
654 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for overall accesses
655 system.cpu.icache.overall_mshr_miss_rate::total 0.079496 # mshr miss rate for overall accesses
656 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11610.747043 # average ReadReq mshr miss latency
657 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11610.747043 # average ReadReq mshr miss latency
658 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency
659 system.cpu.icache.demand_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency
660 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency
661 system.cpu.icache.overall_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency
662 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
663 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
664 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
665 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
666 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
667 system.cpu.l2cache.replacements 64347 # number of replacements
668 system.cpu.l2cache.tagsinuse 51347.741462 # Cycle average of tags in use
669 system.cpu.l2cache.total_refs 1885858 # Total number of references to valid blocks.
670 system.cpu.l2cache.sampled_refs 129741 # Sample count of references to valid blocks.
671 system.cpu.l2cache.avg_refs 14.535559 # Average number of references to valid blocks.
672 system.cpu.l2cache.warmup_cycle 2498197510500 # Cycle when the warmup percentage was hit.
673 system.cpu.l2cache.occ_blocks::writebacks 36929.511487 # Average occupied blocks per requestor
674 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.548284 # Average occupied blocks per requestor
675 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
676 system.cpu.l2cache.occ_blocks::cpu.inst 8159.884348 # Average occupied blocks per requestor
677 system.cpu.l2cache.occ_blocks::cpu.data 6231.796994 # Average occupied blocks per requestor
678 system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy
679 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy
680 system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
681 system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy
682 system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy
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684 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52622 # number of ReadReq hits
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688 system.cpu.l2cache.ReadReq_hits::total 1417091 # number of ReadReq hits
689 system.cpu.l2cache.Writeback_hits::writebacks 607840 # number of Writeback hits
690 system.cpu.l2cache.Writeback_hits::total 607840 # number of Writeback hits
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692 system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits
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694 system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
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696 system.cpu.l2cache.ReadExReq_hits::total 112895 # number of ReadExReq hits
697 system.cpu.l2cache.demand_hits::cpu.dtb.walker 52622 # number of demand (read+write) hits
698 system.cpu.l2cache.demand_hits::cpu.itb.walker 10526 # number of demand (read+write) hits
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702 system.cpu.l2cache.overall_hits::cpu.dtb.walker 52622 # number of overall hits
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704 system.cpu.l2cache.overall_hits::cpu.inst 966687 # number of overall hits
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706 system.cpu.l2cache.overall_hits::total 1529986 # number of overall hits
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713 system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
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723 system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
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725 system.cpu.l2cache.overall_misses::cpu.inst 12342 # number of overall misses
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727 system.cpu.l2cache.overall_misses::total 156285 # number of overall misses
728 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2975000 # number of ReadReq miss cycles
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734 system.cpu.l2cache.UpgradeReq_miss_latency::total 522000 # number of UpgradeReq miss cycles
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736 system.cpu.l2cache.ReadExReq_miss_latency::total 6733037500 # number of ReadExReq miss cycles
737 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2975000 # number of demand (read+write) miss cycles
738 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
739 system.cpu.l2cache.demand_miss_latency::cpu.inst 697957500 # number of demand (read+write) miss cycles
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742 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2975000 # number of overall miss cycles
743 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
744 system.cpu.l2cache.overall_miss_latency::cpu.inst 697957500 # number of overall miss cycles
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747 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52663 # number of ReadReq accesses(hits+misses)
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751 system.cpu.l2cache.ReadReq_accesses::total 1440185 # number of ReadReq accesses(hits+misses)
752 system.cpu.l2cache.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses)
753 system.cpu.l2cache.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses)
754 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses)
755 system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses)
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757 system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
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759 system.cpu.l2cache.ReadExReq_accesses::total 246086 # number of ReadExReq accesses(hits+misses)
760 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52663 # number of demand (read+write) accesses
761 system.cpu.l2cache.demand_accesses::cpu.itb.walker 10528 # number of demand (read+write) accesses
762 system.cpu.l2cache.demand_accesses::cpu.inst 979029 # number of demand (read+write) accesses
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765 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52663 # number of overall (read+write) accesses
766 system.cpu.l2cache.overall_accesses::cpu.itb.walker 10528 # number of overall (read+write) accesses
767 system.cpu.l2cache.overall_accesses::cpu.inst 979029 # number of overall (read+write) accesses
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769 system.cpu.l2cache.overall_accesses::total 1686271 # number of overall (read+write) accesses
770 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000779 # miss rate for ReadReq accesses
771 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses
772 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses
773 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026909 # miss rate for ReadReq accesses
774 system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses
775 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986491 # miss rate for UpgradeReq accesses
776 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986491 # miss rate for UpgradeReq accesses
777 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
778 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
779 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541238 # miss rate for ReadExReq accesses
780 system.cpu.l2cache.ReadExReq_miss_rate::total 0.541238 # miss rate for ReadExReq accesses
781 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000779 # miss rate for demand accesses
782 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses
783 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses
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785 system.cpu.l2cache.demand_miss_rate::total 0.092681 # miss rate for demand accesses
786 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000779 # miss rate for overall accesses
787 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses
788 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses
789 system.cpu.l2cache.overall_miss_rate::cpu.data 0.223430 # miss rate for overall accesses
790 system.cpu.l2cache.overall_miss_rate::total 0.092681 # miss rate for overall accesses
791 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72560.975610 # average ReadReq miss latency
792 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
793 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56551.409820 # average ReadReq miss latency
794 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59219.067980 # average ReadReq miss latency
795 system.cpu.l2cache.ReadReq_avg_miss_latency::total 57817.073655 # average ReadReq miss latency
796 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 178.705923 # average UpgradeReq miss latency
797 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 178.705923 # average UpgradeReq miss latency
798 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50551.745238 # average ReadExReq miss latency
799 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50551.745238 # average ReadExReq miss latency
800 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency
801 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
802 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency
803 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency
804 system.cpu.l2cache.demand_avg_miss_latency::total 51625.331919 # average overall miss latency
805 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency
806 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
807 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency
808 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency
809 system.cpu.l2cache.overall_avg_miss_latency::total 51625.331919 # average overall miss latency
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814 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
815 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
816 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
817 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
818 system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks
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838 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses
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840 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
841 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
842 system.cpu.l2cache.demand_mshr_misses::cpu.inst 12330 # number of demand (read+write) MSHR misses
843 system.cpu.l2cache.demand_mshr_misses::cpu.data 143838 # number of demand (read+write) MSHR misses
844 system.cpu.l2cache.demand_mshr_misses::total 156211 # number of demand (read+write) MSHR misses
845 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
846 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
847 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12330 # number of overall MSHR misses
848 system.cpu.l2cache.overall_mshr_misses::cpu.data 143838 # number of overall MSHR misses
849 system.cpu.l2cache.overall_mshr_misses::total 156211 # number of overall MSHR misses
850 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2463540 # number of ReadReq MSHR miss cycles
851 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles
852 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 543887277 # number of ReadReq MSHR miss cycles
853 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499142740 # number of ReadReq MSHR miss cycles
854 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1045586808 # number of ReadReq MSHR miss cycles
855 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles
856 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles
857 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
858 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
859 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles
860 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles
861 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # number of demand (read+write) MSHR miss cycles
862 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles
863 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 543887277 # number of demand (read+write) MSHR miss cycles
864 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5572159369 # number of demand (read+write) MSHR miss cycles
865 system.cpu.l2cache.demand_mshr_miss_latency::total 6118603437 # number of demand (read+write) MSHR miss cycles
866 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2463540 # number of overall MSHR miss cycles
867 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles
868 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles
869 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles
870 system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles
871 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles
872 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles
873 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles
874 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles
875 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles
876 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles
877 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles
878 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles
879 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses
880 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses
881 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses
882 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses
883 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses
884 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses
885 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses
886 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
887 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
888 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses
889 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses
890 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses
891 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses
892 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses
893 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses
894 system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses
895 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses
896 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses
897 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses
898 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses
899 system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses
900 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency
901 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency
902 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency
903 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency
904 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency
905 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
906 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
907 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
908 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
909 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency
910 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency
911 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency
912 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency
913 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency
914 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency
915 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency
916 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency
917 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency
918 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency
919 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency
920 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency
921 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
922 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
923 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
924 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
925 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
926 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
927 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
928 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
929 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
930 system.cpu.dcache.replacements 643539 # number of replacements
931 system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
932 system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks.
933 system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks.
934 system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks.
935 system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
936 system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
937 system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
938 system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
939 system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits
940 system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits
941 system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits
942 system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits
943 system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits
944 system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits
945 system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits
946 system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits
947 system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits
948 system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits
949 system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits
950 system.cpu.dcache.overall_hits::total 21015683 # number of overall hits
951 system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses
952 system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses
953 system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses
954 system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses
955 system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses
956 system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses
957 system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses
958 system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
959 system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses
960 system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses
961 system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses
962 system.cpu.dcache.overall_misses::total 3700421 # number of overall misses
963 system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles
964 system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles
965 system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles
966 system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles
967 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles
968 system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles
969 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles
970 system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles
971 system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles
972 system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles
973 system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles
974 system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles
975 system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses)
976 system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses)
977 system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses)
978 system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses)
979 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses)
980 system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses)
981 system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses)
982 system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses)
983 system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses
984 system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses
985 system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses
986 system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses
987 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses
988 system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses
989 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses
990 system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses
991 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses
992 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses
993 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses
994 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses
995 system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses
996 system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses
997 system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses
998 system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses
999 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency
1000 system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency
1001 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency
1002 system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency
1003 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency
1004 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency
1005 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency
1006 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency
1007 system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency
1008 system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency
1009 system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency
1010 system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency
1011 system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked
1012 system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked
1013 system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked
1014 system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked
1015 system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked
1016 system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked
1017 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1018 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1019 system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks
1020 system.cpu.dcache.writebacks::total 607840 # number of writebacks
1021 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits
1022 system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits
1023 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits
1024 system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits
1025 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits
1026 system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits
1027 system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits
1028 system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits
1029 system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits
1030 system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits
1031 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses
1032 system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses
1033 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses
1034 system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses
1035 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
1036 system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
1037 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
1038 system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
1039 system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses
1040 system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses
1041 system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses
1042 system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses
1043 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles
1044 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles
1045 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles
1046 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles
1047 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles
1048 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles
1049 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles
1050 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles
1051 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles
1052 system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles
1053 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles
1054 system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles
1055 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles
1056 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles
1057 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles
1058 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles
1059 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles
1060 system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles
1061 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses
1062 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses
1063 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses
1064 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses
1065 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses
1066 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses
1067 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
1068 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
1069 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses
1070 system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses
1071 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses
1072 system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses
1073 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency
1074 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency
1075 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency
1076 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency
1077 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency
1078 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency
1079 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency
1080 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency
1081 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency
1082 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency
1083 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency
1084 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency
1085 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1086 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1087 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1088 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1089 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1090 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1091 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1092 system.iocache.replacements 0 # number of replacements
1093 system.iocache.tagsinuse 0 # Cycle average of tags in use
1094 system.iocache.total_refs 0 # Total number of references to valid blocks.
1095 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1096 system.iocache.avg_refs nan # Average number of references to valid blocks.
1097 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1098 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1099 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1100 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1101 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1102 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1103 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1104 system.iocache.fast_writes 0 # number of fast writes performed
1105 system.iocache.cache_copies 0 # number of cache copies performed
1106 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles
1107 system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles
1108 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles
1109 system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles
1110 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1111 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1112 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1113 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1114 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1115 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1116 system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
1118 ---------- End Simulation Statistics ----------
projects / gem5.git / blob