2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.534173 # Number of seconds simulated
4 sim_ticks 2534173219000 # Number of ticks simulated
5 final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 58476 # Simulator instruction rate (inst/s)
8 host_op_rate 75217 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2445371941 # Simulator tick rate (ticks/s)
10 host_mem_usage 386340 # Number of bytes of host memory used
11 host_seconds 1036.31 # Real time elapsed on the host
12 sim_insts 60599410 # Number of instructions simulated
13 sim_ops 77948210 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
25 system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
32 system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
34 system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s)
52 system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
53 system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
54 system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
55 system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
56 system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
57 system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
58 system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
59 system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
60 system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
61 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
62 system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
63 system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
64 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
65 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
66 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
67 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
68 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
69 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
70 system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
71 system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
72 system.cpu.checker.dtb.read_hits 15049590 # DTB read hits
73 system.cpu.checker.dtb.read_misses 7303 # DTB read misses
74 system.cpu.checker.dtb.write_hits 11294593 # DTB write hits
75 system.cpu.checker.dtb.write_misses 2189 # DTB write misses
76 system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
77 system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78 system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
79 system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
80 system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
81 system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82 system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
83 system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84 system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
85 system.cpu.checker.dtb.read_accesses 15056893 # DTB read accesses
86 system.cpu.checker.dtb.write_accesses 11296782 # DTB write accesses
87 system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
88 system.cpu.checker.dtb.hits 26344183 # DTB hits
89 system.cpu.checker.dtb.misses 9492 # DTB misses
90 system.cpu.checker.dtb.accesses 26353675 # DTB accesses
91 system.cpu.checker.itb.inst_hits 61778177 # ITB inst hits
92 system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
93 system.cpu.checker.itb.read_hits 0 # DTB read hits
94 system.cpu.checker.itb.read_misses 0 # DTB read misses
95 system.cpu.checker.itb.write_hits 0 # DTB write hits
96 system.cpu.checker.itb.write_misses 0 # DTB write misses
97 system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
98 system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
99 system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
100 system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
101 system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
102 system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
103 system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
104 system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
105 system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
106 system.cpu.checker.itb.read_accesses 0 # DTB read accesses
107 system.cpu.checker.itb.write_accesses 0 # DTB write accesses
108 system.cpu.checker.itb.inst_accesses 61782648 # ITB inst accesses
109 system.cpu.checker.itb.hits 61778177 # DTB hits
110 system.cpu.checker.itb.misses 4471 # DTB misses
111 system.cpu.checker.itb.accesses 61782648 # DTB accesses
112 system.cpu.checker.numCycles 78238784 # number of cpu cycles simulated
113 system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
114 system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
115 system.cpu.dtb.inst_hits 0 # ITB inst hits
116 system.cpu.dtb.inst_misses 0 # ITB inst misses
117 system.cpu.dtb.read_hits 51719750 # DTB read hits
118 system.cpu.dtb.read_misses 77229 # DTB read misses
119 system.cpu.dtb.write_hits 11809411 # DTB write hits
120 system.cpu.dtb.write_misses 17373 # DTB write misses
121 system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
122 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
123 system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
124 system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
125 system.cpu.dtb.flush_entries 7767 # Number of entries that have been flushed from TLB
126 system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions
127 system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
128 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
129 system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions
130 system.cpu.dtb.read_accesses 51796979 # DTB read accesses
131 system.cpu.dtb.write_accesses 11826784 # DTB write accesses
132 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
133 system.cpu.dtb.hits 63529161 # DTB hits
134 system.cpu.dtb.misses 94602 # DTB misses
135 system.cpu.dtb.accesses 63623763 # DTB accesses
136 system.cpu.itb.inst_hits 13045523 # ITB inst hits
137 system.cpu.itb.inst_misses 12142 # ITB inst misses
138 system.cpu.itb.read_hits 0 # DTB read hits
139 system.cpu.itb.read_misses 0 # DTB read misses
140 system.cpu.itb.write_hits 0 # DTB write hits
141 system.cpu.itb.write_misses 0 # DTB write misses
142 system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
143 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
144 system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
145 system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
146 system.cpu.itb.flush_entries 5168 # Number of entries that have been flushed from TLB
147 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
148 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
149 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
150 system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions
151 system.cpu.itb.read_accesses 0 # DTB read accesses
152 system.cpu.itb.write_accesses 0 # DTB write accesses
153 system.cpu.itb.inst_accesses 13057665 # ITB inst accesses
154 system.cpu.itb.hits 13045523 # DTB hits
155 system.cpu.itb.misses 12142 # DTB misses
156 system.cpu.itb.accesses 13057665 # DTB accesses
157 system.cpu.numCycles 475815628 # number of cpu cycles simulated
158 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160 system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups
161 system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted
162 system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect
163 system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups
164 system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits
165 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
166 system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target.
167 system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions.
168 system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss
169 system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed
170 system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered
171 system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken
172 system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked
173 system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing
174 system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb
175 system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked
176 system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
177 system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps
178 system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions
179 system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
180 system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched
181 system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed
182 system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed
183 system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total)
184 system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total)
185 system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total)
186 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
187 system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total)
188 system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total)
189 system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total)
190 system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total)
191 system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total)
192 system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total)
193 system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total)
194 system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total)
195 system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total)
196 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
197 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
198 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
199 system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total)
200 system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle
201 system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle
202 system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle
203 system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked
204 system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running
205 system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking
206 system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing
207 system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch
208 system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction
209 system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode
210 system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode
211 system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing
212 system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle
213 system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking
214 system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst
215 system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running
216 system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking
217 system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename
218 system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full
219 system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full
220 system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full
221 system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers
222 system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed
223 system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made
224 system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups
225 system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
226 system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed
227 system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing
228 system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed
229 system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed
230 system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer
231 system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit.
232 system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit.
233 system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads.
234 system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores.
235 system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec)
236 system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ
237 system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued
238 system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued
239 system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling
240 system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph
241 system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed
242 system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle
243 system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle
244 system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle
245 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
246 system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle
247 system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle
248 system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle
249 system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle
250 system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle
251 system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle
252 system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle
253 system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle
254 system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle
255 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
256 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
257 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
258 system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle
259 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
260 system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available
261 system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
262 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
263 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
264 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
265 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
266 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
267 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
268 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
269 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
270 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
271 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
272 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
273 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
274 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
275 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
276 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
277 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
278 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
279 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
280 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
281 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
282 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
283 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
284 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
285 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
286 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
287 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
288 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
289 system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available
290 system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available
291 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
292 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
293 system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
294 system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued
295 system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued
296 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
297 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
298 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
299 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
300 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
301 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
302 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
303 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
304 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
305 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
306 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
307 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
308 system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued
309 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
310 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
311 system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued
312 system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued
313 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
314 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
315 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
316 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
317 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
318 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
319 system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
320 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
321 system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued
322 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
323 system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued
324 system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued
325 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
326 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
327 system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued
328 system.cpu.iq.rate 0.265182 # Inst issue rate
329 system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested
330 system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst)
331 system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads
332 system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes
333 system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses
334 system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads
335 system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
336 system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
337 system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses
338 system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses
339 system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores
340 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
341 system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed
342 system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed
343 system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations
344 system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed
345 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
346 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
347 system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled
348 system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked
349 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
350 system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing
351 system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking
352 system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking
353 system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ
354 system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch
355 system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions
356 system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions
357 system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions
358 system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall
359 system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall
360 system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations
361 system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly
362 system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly
363 system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute
364 system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions
365 system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed
366 system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute
367 system.cpu.iew.exec_swp 0 # number of swp insts executed
368 system.cpu.iew.exec_nop 225103 # number of nop insts executed
369 system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed
370 system.cpu.iew.exec_branches 11726228 # Number of branches executed
371 system.cpu.iew.exec_stores 12321727 # Number of stores executed
372 system.cpu.iew.exec_rate 0.258426 # Inst execution rate
373 system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit
374 system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back
375 system.cpu.iew.wb_producers 47710631 # num instructions producing a value
376 system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value
377 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
378 system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle
379 system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
380 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
381 system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit
382 system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards
383 system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted
384 system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle
385 system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle
386 system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle
387 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
388 system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle
389 system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle
390 system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle
391 system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle
392 system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle
393 system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle
394 system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle
395 system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle
396 system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle
397 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
398 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
399 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
400 system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle
401 system.cpu.commit.committedInsts 60749791 # Number of instructions committed
402 system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed
403 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
404 system.cpu.commit.refs 27515604 # Number of memory references committed
405 system.cpu.commit.loads 15716666 # Number of loads committed
406 system.cpu.commit.membars 413138 # Number of memory barriers committed
407 system.cpu.commit.branches 10023383 # Number of branches committed
408 system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
409 system.cpu.commit.int_insts 69136784 # Number of committed integer instructions.
410 system.cpu.commit.function_calls 996034 # Number of function calls committed.
411 system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached
412 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
413 system.cpu.rob.rob_reads 249407638 # The number of ROB reads
414 system.cpu.rob.rob_writes 208557399 # The number of ROB writes
415 system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself
416 system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling
417 system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
418 system.cpu.committedInsts 60599410 # Number of Instructions Simulated
419 system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated
420 system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated
421 system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction
422 system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads
423 system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle
424 system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads
425 system.cpu.int_regfile_reads 556670721 # number of integer regfile reads
426 system.cpu.int_regfile_writes 89963166 # number of integer regfile writes
427 system.cpu.fp_regfile_reads 8373 # number of floating regfile reads
428 system.cpu.fp_regfile_writes 2910 # number of floating regfile writes
429 system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads
430 system.cpu.misc_regfile_writes 912934 # number of misc regfile writes
431 system.cpu.icache.replacements 989799 # number of replacements
432 system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use
433 system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks.
434 system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks.
435 system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks.
436 system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit.
437 system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor
438 system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy
439 system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy
440 system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits
441 system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits
442 system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits
443 system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits
444 system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits
445 system.cpu.icache.overall_hits::total 11967809 # number of overall hits
446 system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses
447 system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses
448 system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses
449 system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses
450 system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses
451 system.cpu.icache.overall_misses::total 1073749 # number of overall misses
452 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles
453 system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles
454 system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles
455 system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles
456 system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles
457 system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles
458 system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses)
459 system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses)
460 system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses
461 system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses
462 system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses
463 system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses
464 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses
465 system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses
466 system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses
467 system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses
468 system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses
469 system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses
470 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency
471 system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency
472 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
473 system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency
474 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
475 system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency
476 system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked
477 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
478 system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked
479 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
480 system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked
481 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
482 system.cpu.icache.fast_writes 0 # number of fast writes performed
483 system.cpu.icache.cache_copies 0 # number of cache copies performed
484 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83395 # number of ReadReq MSHR hits
485 system.cpu.icache.ReadReq_mshr_hits::total 83395 # number of ReadReq MSHR hits
486 system.cpu.icache.demand_mshr_hits::cpu.inst 83395 # number of demand (read+write) MSHR hits
487 system.cpu.icache.demand_mshr_hits::total 83395 # number of demand (read+write) MSHR hits
488 system.cpu.icache.overall_mshr_hits::cpu.inst 83395 # number of overall MSHR hits
489 system.cpu.icache.overall_mshr_hits::total 83395 # number of overall MSHR hits
490 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990354 # number of ReadReq MSHR misses
491 system.cpu.icache.ReadReq_mshr_misses::total 990354 # number of ReadReq MSHR misses
492 system.cpu.icache.demand_mshr_misses::cpu.inst 990354 # number of demand (read+write) MSHR misses
493 system.cpu.icache.demand_mshr_misses::total 990354 # number of demand (read+write) MSHR misses
494 system.cpu.icache.overall_mshr_misses::cpu.inst 990354 # number of overall MSHR misses
495 system.cpu.icache.overall_mshr_misses::total 990354 # number of overall MSHR misses
496 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11451236993 # number of ReadReq MSHR miss cycles
497 system.cpu.icache.ReadReq_mshr_miss_latency::total 11451236993 # number of ReadReq MSHR miss cycles
498 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11451236993 # number of demand (read+write) MSHR miss cycles
499 system.cpu.icache.demand_mshr_miss_latency::total 11451236993 # number of demand (read+write) MSHR miss cycles
500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11451236993 # number of overall MSHR miss cycles
501 system.cpu.icache.overall_mshr_miss_latency::total 11451236993 # number of overall MSHR miss cycles
502 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles
503 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles
504 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles
505 system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles
506 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for ReadReq accesses
507 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075938 # mshr miss rate for ReadReq accesses
508 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for demand accesses
509 system.cpu.icache.demand_mshr_miss_rate::total 0.075938 # mshr miss rate for demand accesses
510 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for overall accesses
511 system.cpu.icache.overall_mshr_miss_rate::total 0.075938 # mshr miss rate for overall accesses
512 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.771487 # average ReadReq mshr miss latency
513 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.771487 # average ReadReq mshr miss latency
514 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency
515 system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency
516 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency
517 system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency
518 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
519 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
520 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
521 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
522 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
523 system.cpu.dcache.replacements 645297 # number of replacements
524 system.cpu.dcache.tagsinuse 511.991711 # Cycle average of tags in use
525 system.cpu.dcache.total_refs 21788102 # Total number of references to valid blocks.
526 system.cpu.dcache.sampled_refs 645809 # Sample count of references to valid blocks.
527 system.cpu.dcache.avg_refs 33.737687 # Average number of references to valid blocks.
528 system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit.
529 system.cpu.dcache.occ_blocks::cpu.data 511.991711 # Average occupied blocks per requestor
530 system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
531 system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
532 system.cpu.dcache.ReadReq_hits::cpu.data 13926305 # number of ReadReq hits
533 system.cpu.dcache.ReadReq_hits::total 13926305 # number of ReadReq hits
534 system.cpu.dcache.WriteReq_hits::cpu.data 7288115 # number of WriteReq hits
535 system.cpu.dcache.WriteReq_hits::total 7288115 # number of WriteReq hits
536 system.cpu.dcache.LoadLockedReq_hits::cpu.data 284783 # number of LoadLockedReq hits
537 system.cpu.dcache.LoadLockedReq_hits::total 284783 # number of LoadLockedReq hits
538 system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits
539 system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits
540 system.cpu.dcache.demand_hits::cpu.data 21214420 # number of demand (read+write) hits
541 system.cpu.dcache.demand_hits::total 21214420 # number of demand (read+write) hits
542 system.cpu.dcache.overall_hits::cpu.data 21214420 # number of overall hits
543 system.cpu.dcache.overall_hits::total 21214420 # number of overall hits
544 system.cpu.dcache.ReadReq_misses::cpu.data 727409 # number of ReadReq misses
545 system.cpu.dcache.ReadReq_misses::total 727409 # number of ReadReq misses
546 system.cpu.dcache.WriteReq_misses::cpu.data 2962946 # number of WriteReq misses
547 system.cpu.dcache.WriteReq_misses::total 2962946 # number of WriteReq misses
548 system.cpu.dcache.LoadLockedReq_misses::cpu.data 13565 # number of LoadLockedReq misses
549 system.cpu.dcache.LoadLockedReq_misses::total 13565 # number of LoadLockedReq misses
550 system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses
551 system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses
552 system.cpu.dcache.demand_misses::cpu.data 3690355 # number of demand (read+write) misses
553 system.cpu.dcache.demand_misses::total 3690355 # number of demand (read+write) misses
554 system.cpu.dcache.overall_misses::cpu.data 3690355 # number of overall misses
555 system.cpu.dcache.overall_misses::total 3690355 # number of overall misses
556 system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441109500 # number of ReadReq miss cycles
557 system.cpu.dcache.ReadReq_miss_latency::total 9441109500 # number of ReadReq miss cycles
558 system.cpu.dcache.WriteReq_miss_latency::cpu.data 104189875245 # number of WriteReq miss cycles
559 system.cpu.dcache.WriteReq_miss_latency::total 104189875245 # number of WriteReq miss cycles
560 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180817000 # number of LoadLockedReq miss cycles
561 system.cpu.dcache.LoadLockedReq_miss_latency::total 180817000 # number of LoadLockedReq miss cycles
562 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 318500 # number of StoreCondReq miss cycles
563 system.cpu.dcache.StoreCondReq_miss_latency::total 318500 # number of StoreCondReq miss cycles
564 system.cpu.dcache.demand_miss_latency::cpu.data 113630984745 # number of demand (read+write) miss cycles
565 system.cpu.dcache.demand_miss_latency::total 113630984745 # number of demand (read+write) miss cycles
566 system.cpu.dcache.overall_miss_latency::cpu.data 113630984745 # number of overall miss cycles
567 system.cpu.dcache.overall_miss_latency::total 113630984745 # number of overall miss cycles
568 system.cpu.dcache.ReadReq_accesses::cpu.data 14653714 # number of ReadReq accesses(hits+misses)
569 system.cpu.dcache.ReadReq_accesses::total 14653714 # number of ReadReq accesses(hits+misses)
570 system.cpu.dcache.WriteReq_accesses::cpu.data 10251061 # number of WriteReq accesses(hits+misses)
571 system.cpu.dcache.WriteReq_accesses::total 10251061 # number of WriteReq accesses(hits+misses)
572 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298348 # number of LoadLockedReq accesses(hits+misses)
573 system.cpu.dcache.LoadLockedReq_accesses::total 298348 # number of LoadLockedReq accesses(hits+misses)
574 system.cpu.dcache.StoreCondReq_accesses::cpu.data 285754 # number of StoreCondReq accesses(hits+misses)
575 system.cpu.dcache.StoreCondReq_accesses::total 285754 # number of StoreCondReq accesses(hits+misses)
576 system.cpu.dcache.demand_accesses::cpu.data 24904775 # number of demand (read+write) accesses
577 system.cpu.dcache.demand_accesses::total 24904775 # number of demand (read+write) accesses
578 system.cpu.dcache.overall_accesses::cpu.data 24904775 # number of overall (read+write) accesses
579 system.cpu.dcache.overall_accesses::total 24904775 # number of overall (read+write) accesses
580 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049640 # miss rate for ReadReq accesses
581 system.cpu.dcache.ReadReq_miss_rate::total 0.049640 # miss rate for ReadReq accesses
582 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289038 # miss rate for WriteReq accesses
583 system.cpu.dcache.WriteReq_miss_rate::total 0.289038 # miss rate for WriteReq accesses
584 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045467 # miss rate for LoadLockedReq accesses
585 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045467 # miss rate for LoadLockedReq accesses
586 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000052 # miss rate for StoreCondReq accesses
587 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses
588 system.cpu.dcache.demand_miss_rate::cpu.data 0.148179 # miss rate for demand accesses
589 system.cpu.dcache.demand_miss_rate::total 0.148179 # miss rate for demand accesses
590 system.cpu.dcache.overall_miss_rate::cpu.data 0.148179 # miss rate for overall accesses
591 system.cpu.dcache.overall_miss_rate::total 0.148179 # miss rate for overall accesses
592 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12979.093605 # average ReadReq miss latency
593 system.cpu.dcache.ReadReq_avg_miss_latency::total 12979.093605 # average ReadReq miss latency
594 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35164.284211 # average WriteReq miss latency
595 system.cpu.dcache.WriteReq_avg_miss_latency::total 35164.284211 # average WriteReq miss latency
596 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13329.671950 # average LoadLockedReq miss latency
597 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13329.671950 # average LoadLockedReq miss latency
598 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21233.333333 # average StoreCondReq miss latency
599 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21233.333333 # average StoreCondReq miss latency
600 system.cpu.dcache.demand_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency
601 system.cpu.dcache.demand_avg_miss_latency::total 30791.342498 # average overall miss latency
602 system.cpu.dcache.overall_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency
603 system.cpu.dcache.overall_avg_miss_latency::total 30791.342498 # average overall miss latency
604 system.cpu.dcache.blocked_cycles::no_mshrs 25421 # number of cycles access was blocked
605 system.cpu.dcache.blocked_cycles::no_targets 15604 # number of cycles access was blocked
606 system.cpu.dcache.blocked::no_mshrs 2521 # number of cycles access was blocked
607 system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked
608 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.083697 # average number of cycles each access was blocked
609 system.cpu.dcache.avg_blocked_cycles::no_targets 56.948905 # average number of cycles each access was blocked
610 system.cpu.dcache.fast_writes 0 # number of fast writes performed
611 system.cpu.dcache.cache_copies 0 # number of cache copies performed
612 system.cpu.dcache.writebacks::writebacks 609382 # number of writebacks
613 system.cpu.dcache.writebacks::total 609382 # number of writebacks
614 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339956 # number of ReadReq MSHR hits
615 system.cpu.dcache.ReadReq_mshr_hits::total 339956 # number of ReadReq MSHR hits
616 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713832 # number of WriteReq MSHR hits
617 system.cpu.dcache.WriteReq_mshr_hits::total 2713832 # number of WriteReq MSHR hits
618 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1350 # number of LoadLockedReq MSHR hits
619 system.cpu.dcache.LoadLockedReq_mshr_hits::total 1350 # number of LoadLockedReq MSHR hits
620 system.cpu.dcache.demand_mshr_hits::cpu.data 3053788 # number of demand (read+write) MSHR hits
621 system.cpu.dcache.demand_mshr_hits::total 3053788 # number of demand (read+write) MSHR hits
622 system.cpu.dcache.overall_mshr_hits::cpu.data 3053788 # number of overall MSHR hits
623 system.cpu.dcache.overall_mshr_hits::total 3053788 # number of overall MSHR hits
624 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387453 # number of ReadReq MSHR misses
625 system.cpu.dcache.ReadReq_mshr_misses::total 387453 # number of ReadReq MSHR misses
626 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249114 # number of WriteReq MSHR misses
627 system.cpu.dcache.WriteReq_mshr_misses::total 249114 # number of WriteReq MSHR misses
628 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12215 # number of LoadLockedReq MSHR misses
629 system.cpu.dcache.LoadLockedReq_mshr_misses::total 12215 # number of LoadLockedReq MSHR misses
630 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses
631 system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses
632 system.cpu.dcache.demand_mshr_misses::cpu.data 636567 # number of demand (read+write) MSHR misses
633 system.cpu.dcache.demand_mshr_misses::total 636567 # number of demand (read+write) MSHR misses
634 system.cpu.dcache.overall_mshr_misses::cpu.data 636567 # number of overall MSHR misses
635 system.cpu.dcache.overall_mshr_misses::total 636567 # number of overall MSHR misses
636 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4759977000 # number of ReadReq MSHR miss cycles
637 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4759977000 # number of ReadReq MSHR miss cycles
638 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8542104919 # number of WriteReq MSHR miss cycles
639 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8542104919 # number of WriteReq MSHR miss cycles
640 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141597500 # number of LoadLockedReq MSHR miss cycles
641 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141597500 # number of LoadLockedReq MSHR miss cycles
642 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 288500 # number of StoreCondReq MSHR miss cycles
643 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 288500 # number of StoreCondReq MSHR miss cycles
644 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13302081919 # number of demand (read+write) MSHR miss cycles
645 system.cpu.dcache.demand_mshr_miss_latency::total 13302081919 # number of demand (read+write) MSHR miss cycles
646 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13302081919 # number of overall MSHR miss cycles
647 system.cpu.dcache.overall_mshr_miss_latency::total 13302081919 # number of overall MSHR miss cycles
648 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356244500 # number of ReadReq MSHR uncacheable cycles
649 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356244500 # number of ReadReq MSHR uncacheable cycles
650 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41726674069 # number of WriteReq MSHR uncacheable cycles
651 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41726674069 # number of WriteReq MSHR uncacheable cycles
652 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224082918569 # number of overall MSHR uncacheable cycles
653 system.cpu.dcache.overall_mshr_uncacheable_latency::total 224082918569 # number of overall MSHR uncacheable cycles
654 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026441 # mshr miss rate for ReadReq accesses
655 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026441 # mshr miss rate for ReadReq accesses
656 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024301 # mshr miss rate for WriteReq accesses
657 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024301 # mshr miss rate for WriteReq accesses
658 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040942 # mshr miss rate for LoadLockedReq accesses
659 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040942 # mshr miss rate for LoadLockedReq accesses
660 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000052 # mshr miss rate for StoreCondReq accesses
661 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
662 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for demand accesses
663 system.cpu.dcache.demand_mshr_miss_rate::total 0.025560 # mshr miss rate for demand accesses
664 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for overall accesses
665 system.cpu.dcache.overall_mshr_miss_rate::total 0.025560 # mshr miss rate for overall accesses
666 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12285.301701 # average ReadReq mshr miss latency
667 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12285.301701 # average ReadReq mshr miss latency
668 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.943235 # average WriteReq mshr miss latency
669 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.943235 # average WriteReq mshr miss latency
670 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11592.099877 # average LoadLockedReq mshr miss latency
671 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11592.099877 # average LoadLockedReq mshr miss latency
672 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19233.333333 # average StoreCondReq mshr miss latency
673 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19233.333333 # average StoreCondReq mshr miss latency
674 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency
675 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency
676 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency
677 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency
678 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
679 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
680 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
681 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
682 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
683 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
684 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
685 system.cpu.l2cache.replacements 64413 # number of replacements
686 system.cpu.l2cache.tagsinuse 51352.307141 # Cycle average of tags in use
687 system.cpu.l2cache.total_refs 1928116 # Total number of references to valid blocks.
688 system.cpu.l2cache.sampled_refs 129809 # Sample count of references to valid blocks.
689 system.cpu.l2cache.avg_refs 14.853485 # Average number of references to valid blocks.
690 system.cpu.l2cache.warmup_cycle 2498979146000 # Cycle when the warmup percentage was hit.
691 system.cpu.l2cache.occ_blocks::writebacks 36881.759655 # Average occupied blocks per requestor
692 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 43.531667 # Average occupied blocks per requestor
693 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor
694 system.cpu.l2cache.occ_blocks::cpu.inst 8178.474419 # Average occupied blocks per requestor
695 system.cpu.l2cache.occ_blocks::cpu.data 6248.541162 # Average occupied blocks per requestor
696 system.cpu.l2cache.occ_percent::writebacks 0.562771 # Average percentage of cache occupancy
697 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000664 # Average percentage of cache occupancy
698 system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
699 system.cpu.l2cache.occ_percent::cpu.inst 0.124794 # Average percentage of cache occupancy
700 system.cpu.l2cache.occ_percent::cpu.data 0.095345 # Average percentage of cache occupancy
701 system.cpu.l2cache.occ_percent::total 0.783574 # Average percentage of cache occupancy
702 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 82776 # number of ReadReq hits
703 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11675 # number of ReadReq hits
704 system.cpu.l2cache.ReadReq_hits::cpu.inst 976745 # number of ReadReq hits
705 system.cpu.l2cache.ReadReq_hits::cpu.data 388849 # number of ReadReq hits
706 system.cpu.l2cache.ReadReq_hits::total 1460045 # number of ReadReq hits
707 system.cpu.l2cache.Writeback_hits::writebacks 609382 # number of Writeback hits
708 system.cpu.l2cache.Writeback_hits::total 609382 # number of Writeback hits
709 system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits
710 system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits
711 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits
712 system.cpu.l2cache.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
713 system.cpu.l2cache.ReadExReq_hits::cpu.data 113019 # number of ReadExReq hits
714 system.cpu.l2cache.ReadExReq_hits::total 113019 # number of ReadExReq hits
715 system.cpu.l2cache.demand_hits::cpu.dtb.walker 82776 # number of demand (read+write) hits
716 system.cpu.l2cache.demand_hits::cpu.itb.walker 11675 # number of demand (read+write) hits
717 system.cpu.l2cache.demand_hits::cpu.inst 976745 # number of demand (read+write) hits
718 system.cpu.l2cache.demand_hits::cpu.data 501868 # number of demand (read+write) hits
719 system.cpu.l2cache.demand_hits::total 1573064 # number of demand (read+write) hits
720 system.cpu.l2cache.overall_hits::cpu.dtb.walker 82776 # number of overall hits
721 system.cpu.l2cache.overall_hits::cpu.itb.walker 11675 # number of overall hits
722 system.cpu.l2cache.overall_hits::cpu.inst 976745 # number of overall hits
723 system.cpu.l2cache.overall_hits::cpu.data 501868 # number of overall hits
724 system.cpu.l2cache.overall_hits::total 1573064 # number of overall hits
725 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses
726 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
727 system.cpu.l2cache.ReadReq_misses::cpu.inst 12352 # number of ReadReq misses
728 system.cpu.l2cache.ReadReq_misses::cpu.data 10732 # number of ReadReq misses
729 system.cpu.l2cache.ReadReq_misses::total 23140 # number of ReadReq misses
730 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2931 # number of UpgradeReq misses
731 system.cpu.l2cache.UpgradeReq_misses::total 2931 # number of UpgradeReq misses
732 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
733 system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
734 system.cpu.l2cache.ReadExReq_misses::cpu.data 133209 # number of ReadExReq misses
735 system.cpu.l2cache.ReadExReq_misses::total 133209 # number of ReadExReq misses
736 system.cpu.l2cache.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses
737 system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
738 system.cpu.l2cache.demand_misses::cpu.inst 12352 # number of demand (read+write) misses
739 system.cpu.l2cache.demand_misses::cpu.data 143941 # number of demand (read+write) misses
740 system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
741 system.cpu.l2cache.overall_misses::cpu.dtb.walker 55 # number of overall misses
742 system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
743 system.cpu.l2cache.overall_misses::cpu.inst 12352 # number of overall misses
744 system.cpu.l2cache.overall_misses::cpu.data 143941 # number of overall misses
745 system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
746 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2897000 # number of ReadReq miss cycles
747 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles
748 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657788500 # number of ReadReq miss cycles
749 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 564922998 # number of ReadReq miss cycles
750 system.cpu.l2cache.ReadReq_miss_latency::total 1225668498 # number of ReadReq miss cycles
751 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1151000 # number of UpgradeReq miss cycles
752 system.cpu.l2cache.UpgradeReq_miss_latency::total 1151000 # number of UpgradeReq miss cycles
753 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7004343998 # number of ReadExReq miss cycles
754 system.cpu.l2cache.ReadExReq_miss_latency::total 7004343998 # number of ReadExReq miss cycles
755 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2897000 # number of demand (read+write) miss cycles
756 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles
757 system.cpu.l2cache.demand_miss_latency::cpu.inst 657788500 # number of demand (read+write) miss cycles
758 system.cpu.l2cache.demand_miss_latency::cpu.data 7569266996 # number of demand (read+write) miss cycles
759 system.cpu.l2cache.demand_miss_latency::total 8230012496 # number of demand (read+write) miss cycles
760 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2897000 # number of overall miss cycles
761 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles
762 system.cpu.l2cache.overall_miss_latency::cpu.inst 657788500 # number of overall miss cycles
763 system.cpu.l2cache.overall_miss_latency::cpu.data 7569266996 # number of overall miss cycles
764 system.cpu.l2cache.overall_miss_latency::total 8230012496 # number of overall miss cycles
765 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 82831 # number of ReadReq accesses(hits+misses)
766 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11676 # number of ReadReq accesses(hits+misses)
767 system.cpu.l2cache.ReadReq_accesses::cpu.inst 989097 # number of ReadReq accesses(hits+misses)
768 system.cpu.l2cache.ReadReq_accesses::cpu.data 399581 # number of ReadReq accesses(hits+misses)
769 system.cpu.l2cache.ReadReq_accesses::total 1483185 # number of ReadReq accesses(hits+misses)
770 system.cpu.l2cache.Writeback_accesses::writebacks 609382 # number of Writeback accesses(hits+misses)
771 system.cpu.l2cache.Writeback_accesses::total 609382 # number of Writeback accesses(hits+misses)
772 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2973 # number of UpgradeReq accesses(hits+misses)
773 system.cpu.l2cache.UpgradeReq_accesses::total 2973 # number of UpgradeReq accesses(hits+misses)
774 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 15 # number of SCUpgradeReq accesses(hits+misses)
775 system.cpu.l2cache.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses)
776 system.cpu.l2cache.ReadExReq_accesses::cpu.data 246228 # number of ReadExReq accesses(hits+misses)
777 system.cpu.l2cache.ReadExReq_accesses::total 246228 # number of ReadExReq accesses(hits+misses)
778 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 82831 # number of demand (read+write) accesses
779 system.cpu.l2cache.demand_accesses::cpu.itb.walker 11676 # number of demand (read+write) accesses
780 system.cpu.l2cache.demand_accesses::cpu.inst 989097 # number of demand (read+write) accesses
781 system.cpu.l2cache.demand_accesses::cpu.data 645809 # number of demand (read+write) accesses
782 system.cpu.l2cache.demand_accesses::total 1729413 # number of demand (read+write) accesses
783 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 82831 # number of overall (read+write) accesses
784 system.cpu.l2cache.overall_accesses::cpu.itb.walker 11676 # number of overall (read+write) accesses
785 system.cpu.l2cache.overall_accesses::cpu.inst 989097 # number of overall (read+write) accesses
786 system.cpu.l2cache.overall_accesses::cpu.data 645809 # number of overall (read+write) accesses
787 system.cpu.l2cache.overall_accesses::total 1729413 # number of overall (read+write) accesses
788 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000664 # miss rate for ReadReq accesses
789 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000086 # miss rate for ReadReq accesses
790 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012488 # miss rate for ReadReq accesses
791 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026858 # miss rate for ReadReq accesses
792 system.cpu.l2cache.ReadReq_miss_rate::total 0.015602 # miss rate for ReadReq accesses
793 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985873 # miss rate for UpgradeReq accesses
794 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985873 # miss rate for UpgradeReq accesses
795 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.200000 # miss rate for SCUpgradeReq accesses
796 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
797 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540999 # miss rate for ReadExReq accesses
798 system.cpu.l2cache.ReadExReq_miss_rate::total 0.540999 # miss rate for ReadExReq accesses
799 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000664 # miss rate for demand accesses
800 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000086 # miss rate for demand accesses
801 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012488 # miss rate for demand accesses
802 system.cpu.l2cache.demand_miss_rate::cpu.data 0.222885 # miss rate for demand accesses
803 system.cpu.l2cache.demand_miss_rate::total 0.090406 # miss rate for demand accesses
804 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000664 # miss rate for overall accesses
805 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000086 # miss rate for overall accesses
806 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012488 # miss rate for overall accesses
807 system.cpu.l2cache.overall_miss_rate::cpu.data 0.222885 # miss rate for overall accesses
808 system.cpu.l2cache.overall_miss_rate::total 0.090406 # miss rate for overall accesses
809 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52672.727273 # average ReadReq miss latency
810 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency
811 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53253.602655 # average ReadReq miss latency
812 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52639.116474 # average ReadReq miss latency
813 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52967.523682 # average ReadReq miss latency
814 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 392.698738 # average UpgradeReq miss latency
815 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 392.698738 # average UpgradeReq miss latency
816 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52581.612339 # average ReadExReq miss latency
817 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52581.612339 # average ReadExReq miss latency
818 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52672.727273 # average overall miss latency
819 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
820 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53253.602655 # average overall miss latency
821 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52585.899751 # average overall miss latency
822 system.cpu.l2cache.demand_avg_miss_latency::total 52638.728076 # average overall miss latency
823 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52672.727273 # average overall miss latency
824 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
825 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53253.602655 # average overall miss latency
826 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52585.899751 # average overall miss latency
827 system.cpu.l2cache.overall_avg_miss_latency::total 52638.728076 # average overall miss latency
828 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
829 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
830 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
831 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
832 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
833 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
834 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
835 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
836 system.cpu.l2cache.writebacks::writebacks 59144 # number of writebacks
837 system.cpu.l2cache.writebacks::total 59144 # number of writebacks
838 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
839 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
840 system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
841 system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
842 system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
843 system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
844 system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
845 system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
846 system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
847 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses
848 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
849 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12344 # number of ReadReq MSHR misses
850 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses
851 system.cpu.l2cache.ReadReq_mshr_misses::total 23070 # number of ReadReq MSHR misses
852 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2931 # number of UpgradeReq MSHR misses
853 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2931 # number of UpgradeReq MSHR misses
854 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
855 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
856 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133209 # number of ReadExReq MSHR misses
857 system.cpu.l2cache.ReadExReq_mshr_misses::total 133209 # number of ReadExReq MSHR misses
858 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses
859 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
860 system.cpu.l2cache.demand_mshr_misses::cpu.inst 12344 # number of demand (read+write) MSHR misses
861 system.cpu.l2cache.demand_mshr_misses::cpu.data 143879 # number of demand (read+write) MSHR misses
862 system.cpu.l2cache.demand_mshr_misses::total 156279 # number of demand (read+write) MSHR misses
863 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses
864 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
865 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12344 # number of overall MSHR misses
866 system.cpu.l2cache.overall_mshr_misses::cpu.data 143879 # number of overall MSHR misses
867 system.cpu.l2cache.overall_mshr_misses::total 156279 # number of overall MSHR misses
868 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2227000 # number of ReadReq MSHR miss cycles
869 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles
870 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506657500 # number of ReadReq MSHR miss cycles
871 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431701998 # number of ReadReq MSHR miss cycles
872 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940634498 # number of ReadReq MSHR miss cycles
873 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117255500 # number of UpgradeReq MSHR miss cycles
874 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117255500 # number of UpgradeReq MSHR miss cycles
875 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
876 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
877 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5363194498 # number of ReadExReq MSHR miss cycles
878 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5363194498 # number of ReadExReq MSHR miss cycles
879 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2227000 # number of demand (read+write) MSHR miss cycles
880 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles
881 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506657500 # number of demand (read+write) MSHR miss cycles
882 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5794896496 # number of demand (read+write) MSHR miss cycles
883 system.cpu.l2cache.demand_mshr_miss_latency::total 6303828996 # number of demand (read+write) MSHR miss cycles
884 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2227000 # number of overall MSHR miss cycles
885 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles
886 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506657500 # number of overall MSHR miss cycles
887 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5794896496 # number of overall MSHR miss cycles
888 system.cpu.l2cache.overall_mshr_miss_latency::total 6303828996 # number of overall MSHR miss cycles
889 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles
890 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166679722000 # number of ReadReq MSHR uncacheable cycles
891 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166685014000 # number of ReadReq MSHR uncacheable cycles
892 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32284839499 # number of WriteReq MSHR uncacheable cycles
893 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32284839499 # number of WriteReq MSHR uncacheable cycles
894 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles
895 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198964561499 # number of overall MSHR uncacheable cycles
896 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198969853499 # number of overall MSHR uncacheable cycles
897 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses
898 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for ReadReq accesses
899 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for ReadReq accesses
900 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026703 # mshr miss rate for ReadReq accesses
901 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses
902 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985873 # mshr miss rate for UpgradeReq accesses
903 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985873 # mshr miss rate for UpgradeReq accesses
904 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
905 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
906 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540999 # mshr miss rate for ReadExReq accesses
907 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540999 # mshr miss rate for ReadExReq accesses
908 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for demand accesses
909 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for demand accesses
910 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for demand accesses
911 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for demand accesses
912 system.cpu.l2cache.demand_mshr_miss_rate::total 0.090365 # mshr miss rate for demand accesses
913 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for overall accesses
914 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for overall accesses
915 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for overall accesses
916 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for overall accesses
917 system.cpu.l2cache.overall_mshr_miss_rate::total 0.090365 # mshr miss rate for overall accesses
918 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average ReadReq mshr miss latency
919 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency
920 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41044.839598 # average ReadReq mshr miss latency
921 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40459.418744 # average ReadReq mshr miss latency
922 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40773.060165 # average ReadReq mshr miss latency
923 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40005.288298 # average UpgradeReq mshr miss latency
924 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40005.288298 # average UpgradeReq mshr miss latency
925 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
926 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
927 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40261.502586 # average ReadExReq mshr miss latency
928 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40261.502586 # average ReadExReq mshr miss latency
929 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency
930 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
931 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency
932 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
933 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency
934 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency
935 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
936 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency
937 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
938 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency
939 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
940 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
941 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
942 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
943 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
944 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
945 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
946 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
947 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
948 system.iocache.replacements 0 # number of replacements
949 system.iocache.tagsinuse 0 # Cycle average of tags in use
950 system.iocache.total_refs 0 # Total number of references to valid blocks.
951 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
952 system.iocache.avg_refs nan # Average number of references to valid blocks.
953 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
954 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
955 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
956 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
957 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
958 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
959 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
960 system.iocache.fast_writes 0 # number of fast writes performed
961 system.iocache.cache_copies 0 # number of cache copies performed
962 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles
963 system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles
964 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles
965 system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles
966 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
967 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
968 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
969 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
970 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
971 system.cpu.kern.inst.arm 0 # number of arm instructions executed
972 system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed
974 ---------- End Simulation Statistics ----------
projects / gem5.git / blob