2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.827390 # Number of seconds simulated
4 sim_ticks 2827390179000 # Number of ticks simulated
5 final_tick 2827390179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 115301 # Simulator instruction rate (inst/s)
8 host_op_rate 139868 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2711751203 # Simulator tick rate (ticks/s)
10 host_mem_usage 622004 # Number of bytes of host memory used
11 host_seconds 1042.64 # Real time elapsed on the host
12 sim_insts 120217407 # Number of instructions simulated
13 sim_ops 145833000 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 1297536 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 1327400 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.l2cache.prefetcher 8611392 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.inst 181424 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.data 629012 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.l2cache.prefetcher 447552 # Number of bytes read from this memory
26 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27 system.physmem.bytes_read::total 12497708 # Number of bytes read from this memory
28 system.physmem.bytes_inst_read::cpu0.inst 1297536 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::cpu1.inst 181424 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::total 1478960 # Number of instructions bytes read from this memory
31 system.physmem.bytes_written::writebacks 8852800 # Number of bytes written to this memory
32 system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34 system.physmem.bytes_written::total 8870364 # Number of bytes written to this memory
35 system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.inst 22521 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.data 21261 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.l2cache.prefetcher 134553 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.inst 2903 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.data 9849 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.l2cache.prefetcher 6993 # Number of read requests responded to by this memory
45 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
46 system.physmem.num_reads::total 198133 # Number of read requests responded to by this memory
47 system.physmem.num_writes::writebacks 138325 # Number of write requests responded to by this memory
48 system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
50 system.physmem.num_writes::total 142716 # Number of write requests responded to by this memory
51 system.physmem.bw_read::cpu0.dtb.walker 634 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.inst 458916 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.data 469479 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.l2cache.prefetcher 3045703 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.inst 64167 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.data 222471 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.l2cache.prefetcher 158292 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::total 4420228 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_inst_read::cpu0.inst 458916 # Instruction read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu1.inst 64167 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::total 523083 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::writebacks 3131085 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::total 3137297 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_total::writebacks 3131085 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu0.dtb.walker 634 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.inst 458916 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.data 475677 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.l2cache.prefetcher 3045703 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.inst 64167 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.data 222485 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.l2cache.prefetcher 158292 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::total 7557525 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.readReqs 198134 # Number of read requests accepted
84 system.physmem.writeReqs 142716 # Number of write requests accepted
85 system.physmem.readBursts 198134 # Number of DRAM read bursts, including those serviced by the write queue
86 system.physmem.writeBursts 142716 # Number of DRAM write bursts, including those merged in the write queue
87 system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
88 system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
89 system.physmem.bytesWritten 8883264 # Total number of bytes written to DRAM
90 system.physmem.bytesReadSys 12497772 # Total read bytes from the system interface side
91 system.physmem.bytesWrittenSys 8870364 # Total written bytes from the system interface side
92 system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
93 system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
94 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95 system.physmem.perBankRdBursts::0 12497 # Per bank write bursts
96 system.physmem.perBankRdBursts::1 12182 # Per bank write bursts
97 system.physmem.perBankRdBursts::2 12917 # Per bank write bursts
98 system.physmem.perBankRdBursts::3 12745 # Per bank write bursts
99 system.physmem.perBankRdBursts::4 14769 # Per bank write bursts
100 system.physmem.perBankRdBursts::5 12267 # Per bank write bursts
101 system.physmem.perBankRdBursts::6 12449 # Per bank write bursts
102 system.physmem.perBankRdBursts::7 12406 # Per bank write bursts
103 system.physmem.perBankRdBursts::8 12316 # Per bank write bursts
104 system.physmem.perBankRdBursts::9 12005 # Per bank write bursts
105 system.physmem.perBankRdBursts::10 11767 # Per bank write bursts
106 system.physmem.perBankRdBursts::11 10930 # Per bank write bursts
107 system.physmem.perBankRdBursts::12 12080 # Per bank write bursts
108 system.physmem.perBankRdBursts::13 12638 # Per bank write bursts
109 system.physmem.perBankRdBursts::14 12372 # Per bank write bursts
110 system.physmem.perBankRdBursts::15 11644 # Per bank write bursts
111 system.physmem.perBankWrBursts::0 9110 # Per bank write bursts
112 system.physmem.perBankWrBursts::1 9003 # Per bank write bursts
113 system.physmem.perBankWrBursts::2 9525 # Per bank write bursts
114 system.physmem.perBankWrBursts::3 9146 # Per bank write bursts
115 system.physmem.perBankWrBursts::4 8599 # Per bank write bursts
116 system.physmem.perBankWrBursts::5 8760 # Per bank write bursts
117 system.physmem.perBankWrBursts::6 8787 # Per bank write bursts
118 system.physmem.perBankWrBursts::7 8590 # Per bank write bursts
119 system.physmem.perBankWrBursts::8 8640 # Per bank write bursts
120 system.physmem.perBankWrBursts::9 8402 # Per bank write bursts
121 system.physmem.perBankWrBursts::10 8397 # Per bank write bursts
122 system.physmem.perBankWrBursts::11 7923 # Per bank write bursts
123 system.physmem.perBankWrBursts::12 8683 # Per bank write bursts
124 system.physmem.perBankWrBursts::13 8738 # Per bank write bursts
125 system.physmem.perBankWrBursts::14 8625 # Per bank write bursts
126 system.physmem.perBankWrBursts::15 7873 # Per bank write bursts
127 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128 system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
129 system.physmem.totGap 2827389912000 # Total gap between requests
130 system.physmem.readPktSize::0 0 # Read request sizes (log2)
131 system.physmem.readPktSize::1 0 # Read request sizes (log2)
132 system.physmem.readPktSize::2 551 # Read request sizes (log2)
133 system.physmem.readPktSize::3 28 # Read request sizes (log2)
134 system.physmem.readPktSize::4 3087 # Read request sizes (log2)
135 system.physmem.readPktSize::5 0 # Read request sizes (log2)
136 system.physmem.readPktSize::6 194468 # Read request sizes (log2)
137 system.physmem.writePktSize::0 0 # Write request sizes (log2)
138 system.physmem.writePktSize::1 0 # Write request sizes (log2)
139 system.physmem.writePktSize::2 4391 # Write request sizes (log2)
140 system.physmem.writePktSize::3 0 # Write request sizes (log2)
141 system.physmem.writePktSize::4 0 # Write request sizes (log2)
142 system.physmem.writePktSize::5 0 # Write request sizes (log2)
143 system.physmem.writePktSize::6 138325 # Write request sizes (log2)
144 system.physmem.rdQLenPdf::0 63072 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::1 74912 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::2 13439 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::3 10395 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::4 8664 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::5 7526 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::6 6556 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::8 4708 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::9 1378 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::10 855 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::11 585 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::12 259 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::15 2653 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::16 3705 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::17 4835 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::18 4665 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::20 5830 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::21 6370 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::22 6999 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::23 7929 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::25 8736 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::26 9851 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::27 9099 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::28 9885 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::29 12144 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::30 9599 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::31 8596 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::32 8331 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::33 1397 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::34 519 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::37 283 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::38 213 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::40 166 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see
240 system.physmem.bytesPerActivate::samples 90813 # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::mean 237.346812 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::gmean 134.326622 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::stdev 300.184335 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::0-127 49078 54.04% 54.04% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::128-255 17700 19.49% 73.53% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::256-383 6123 6.74% 80.28% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::384-511 3320 3.66% 83.93% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::512-639 2774 3.05% 86.99% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::640-767 1638 1.80% 88.79% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::768-895 995 1.10% 89.89% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::896-1023 978 1.08% 90.96% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::1024-1151 8207 9.04% 100.00% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::total 90813 # Bytes accessed per row activation
254 system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes
255 system.physmem.rdPerTurnAround::mean 29.444230 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::stdev 548.218856 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::0-2047 6721 99.96% 99.96% # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes
261 system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::mean 20.642623 # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::gmean 18.824239 # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::stdev 13.739703 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::16-19 5581 83.00% 83.00% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::20-23 483 7.18% 90.18% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::24-27 96 1.43% 91.61% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::28-31 46 0.68% 92.30% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::32-35 45 0.67% 92.97% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::36-39 26 0.39% 93.35% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::40-43 56 0.83% 94.19% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::44-47 16 0.24% 94.42% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::48-51 112 1.67% 96.09% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::52-55 17 0.25% 96.34% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::56-59 5 0.07% 96.42% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::60-63 15 0.22% 96.64% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::64-67 76 1.13% 97.77% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::68-71 5 0.07% 97.84% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::72-75 5 0.07% 97.92% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::76-79 30 0.45% 98.36% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::80-83 72 1.07% 99.43% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::84-87 5 0.07% 99.51% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.52% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::96-99 3 0.04% 99.57% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.60% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.61% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::116-119 1 0.01% 99.63% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::120-123 1 0.01% 99.64% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::128-131 7 0.10% 99.75% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::136-139 2 0.03% 99.78% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::140-143 3 0.04% 99.82% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::160-163 1 0.01% 99.94% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::168-171 1 0.01% 99.96% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
299 system.physmem.totQLat 6642491804 # Total ticks spent queuing
300 system.physmem.totMemAccLat 10354691804 # Total ticks spent from burst creation until serviced by the DRAM
301 system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
302 system.physmem.avgQLat 33550.65 # Average queueing delay per DRAM burst
303 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
304 system.physmem.avgMemAccLat 52300.65 # Average memory access latency per DRAM burst
305 system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
306 system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
307 system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s
308 system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
309 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
310 system.physmem.busUtil 0.06 # Data bus utilization in percentage
311 system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
312 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
313 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
314 system.physmem.avgWrQLen 28.40 # Average write queue length when enqueuing
315 system.physmem.readRowHits 165266 # Number of row buffer hits during reads
316 system.physmem.writeRowHits 80705 # Number of row buffer hits during writes
317 system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
318 system.physmem.writeRowHitRate 58.14 # Row buffer hit rate for writes
319 system.physmem.avgGap 8295114.90 # Average gap between requests
320 system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined
321 system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
322 system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
323 system.physmem_0.readEnergy 797401800 # Energy for read commands per rank (pJ)
324 system.physmem_0.writeEnergy 463449600 # Energy for write commands per rank (pJ)
325 system.physmem_0.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
326 system.physmem_0.actBackEnergy 80516584620 # Energy for active background per rank (pJ)
327 system.physmem_0.preBackEnergy 1625805455250 # Energy for precharge background per rank (pJ)
328 system.physmem_0.totalEnergy 1892805688350 # Total energy per rank (pJ)
329 system.physmem_0.averagePower 669.453328 # Core power per rank (mW)
330 system.physmem_0.memoryStateTime::IDLE 2704566595208 # Time in different power states
331 system.physmem_0.memoryStateTime::REF 94412760000 # Time in different power states
332 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
333 system.physmem_0.memoryStateTime::ACT 28410820792 # Time in different power states
334 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
335 system.physmem_1.actEnergy 329774760 # Energy for activate commands per rank (pJ)
336 system.physmem_1.preEnergy 179936625 # Energy for precharge commands per rank (pJ)
337 system.physmem_1.readEnergy 746865600 # Energy for read commands per rank (pJ)
338 system.physmem_1.writeEnergy 435980880 # Energy for write commands per rank (pJ)
339 system.physmem_1.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
340 system.physmem_1.actBackEnergy 80145816435 # Energy for active background per rank (pJ)
341 system.physmem_1.preBackEnergy 1626130690500 # Energy for precharge background per rank (pJ)
342 system.physmem_1.totalEnergy 1892640423360 # Total energy per rank (pJ)
343 system.physmem_1.averagePower 669.394877 # Core power per rank (mW)
344 system.physmem_1.memoryStateTime::IDLE 2705113148361 # Time in different power states
345 system.physmem_1.memoryStateTime::REF 94412760000 # Time in different power states
346 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
347 system.physmem_1.memoryStateTime::ACT 27864169139 # Time in different power states
348 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
349 system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
350 system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
351 system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
352 system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
353 system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
354 system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
355 system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
356 system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
357 system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
358 system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
359 system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
360 system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
361 system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
362 system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
363 system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
364 system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
365 system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
366 system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
367 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
368 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
369 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
370 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
371 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
372 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
373 system.cpu0.branchPred.lookups 53911245 # Number of BP lookups
374 system.cpu0.branchPred.condPredicted 24947324 # Number of conditional branches predicted
375 system.cpu0.branchPred.condIncorrect 985007 # Number of conditional branches incorrect
376 system.cpu0.branchPred.BTBLookups 32642222 # Number of BTB lookups
377 system.cpu0.branchPred.BTBHits 14256732 # Number of BTB hits
378 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
379 system.cpu0.branchPred.BTBHitPct 43.675740 # BTB Hit Percentage
380 system.cpu0.branchPred.usedRAS 15584760 # Number of times the RAS was used to get a target.
381 system.cpu0.branchPred.RASInCorrect 34685 # Number of incorrect RAS predictions.
382 system.cpu0.branchPred.indirectLookups 10159968 # Number of indirect predictor lookups.
383 system.cpu0.branchPred.indirectHits 9991718 # Number of indirect target hits.
384 system.cpu0.branchPred.indirectMisses 168250 # Number of indirect misses.
385 system.cpu0.branchPredindirectMispredicted 52822 # Number of mispredicted indirect branches.
386 system.cpu_clk_domain.clock 500 # Clock period in ticks
387 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
388 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
389 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
390 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
391 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
392 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
393 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
394 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
395 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
396 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
397 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
398 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
399 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
400 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
401 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
402 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
403 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
404 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
405 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
406 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
407 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
408 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
409 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
410 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
411 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
412 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
413 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
414 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
415 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
416 system.cpu0.dtb.walker.walks 71875 # Table walker walks requested
417 system.cpu0.dtb.walker.walksShort 71875 # Table walker walks initiated with short descriptors
418 system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26071 # Level at which table walker walks with short descriptors terminate
419 system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21701 # Level at which table walker walks with short descriptors terminate
420 system.cpu0.dtb.walker.walksSquashedBefore 24103 # Table walks squashed before starting
421 system.cpu0.dtb.walker.walkWaitTime::samples 47772 # Table walker wait (enqueue to first request) latency
422 system.cpu0.dtb.walker.walkWaitTime::mean 520.796701 # Table walker wait (enqueue to first request) latency
423 system.cpu0.dtb.walker.walkWaitTime::stdev 3158.268863 # Table walker wait (enqueue to first request) latency
424 system.cpu0.dtb.walker.walkWaitTime::0-8191 46423 97.18% 97.18% # Table walker wait (enqueue to first request) latency
425 system.cpu0.dtb.walker.walkWaitTime::8192-16383 981 2.05% 99.23% # Table walker wait (enqueue to first request) latency
426 system.cpu0.dtb.walker.walkWaitTime::16384-24575 165 0.35% 99.58% # Table walker wait (enqueue to first request) latency
427 system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.90% # Table walker wait (enqueue to first request) latency
428 system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.04% 99.94% # Table walker wait (enqueue to first request) latency
429 system.cpu0.dtb.walker.walkWaitTime::40960-49151 25 0.05% 99.99% # Table walker wait (enqueue to first request) latency
430 system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
431 system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
432 system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
433 system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
434 system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
435 system.cpu0.dtb.walker.walkWaitTime::total 47772 # Table walker wait (enqueue to first request) latency
436 system.cpu0.dtb.walker.walkCompletionTime::samples 18721 # Table walker service (enqueue to completion) latency
437 system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770 # Table walker service (enqueue to completion) latency
438 system.cpu0.dtb.walker.walkCompletionTime::gmean 9623.609798 # Table walker service (enqueue to completion) latency
439 system.cpu0.dtb.walker.walkCompletionTime::stdev 9038.861696 # Table walker service (enqueue to completion) latency
440 system.cpu0.dtb.walker.walkCompletionTime::0-32767 18593 99.32% 99.32% # Table walker service (enqueue to completion) latency
441 system.cpu0.dtb.walker.walkCompletionTime::32768-65535 88 0.47% 99.79% # Table walker service (enqueue to completion) latency
442 system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.91% # Table walker service (enqueue to completion) latency
443 system.cpu0.dtb.walker.walkCompletionTime::163840-196607 16 0.09% 99.99% # Table walker service (enqueue to completion) latency
444 system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
445 system.cpu0.dtb.walker.walkCompletionTime::total 18721 # Table walker service (enqueue to completion) latency
446 system.cpu0.dtb.walker.walksPending::samples 87200107652 # Table walker pending requests distribution
447 system.cpu0.dtb.walker.walksPending::mean 0.546732 # Table walker pending requests distribution
448 system.cpu0.dtb.walker.walksPending::stdev 0.508218 # Table walker pending requests distribution
449 system.cpu0.dtb.walker.walksPending::0 39687331700 45.51% 45.51% # Table walker pending requests distribution
450 system.cpu0.dtb.walker.walksPending::1 47447148952 54.41% 99.92% # Table walker pending requests distribution
451 system.cpu0.dtb.walker.walksPending::2 30000500 0.03% 99.96% # Table walker pending requests distribution
452 system.cpu0.dtb.walker.walksPending::3 16923500 0.02% 99.98% # Table walker pending requests distribution
453 system.cpu0.dtb.walker.walksPending::4 5972000 0.01% 99.99% # Table walker pending requests distribution
454 system.cpu0.dtb.walker.walksPending::5 3342500 0.00% 99.99% # Table walker pending requests distribution
455 system.cpu0.dtb.walker.walksPending::6 3974500 0.00% 99.99% # Table walker pending requests distribution
456 system.cpu0.dtb.walker.walksPending::7 1269500 0.00% 100.00% # Table walker pending requests distribution
457 system.cpu0.dtb.walker.walksPending::8 992000 0.00% 100.00% # Table walker pending requests distribution
458 system.cpu0.dtb.walker.walksPending::9 652500 0.00% 100.00% # Table walker pending requests distribution
459 system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution
460 system.cpu0.dtb.walker.walksPending::11 287500 0.00% 100.00% # Table walker pending requests distribution
461 system.cpu0.dtb.walker.walksPending::12 887500 0.00% 100.00% # Table walker pending requests distribution
462 system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution
463 system.cpu0.dtb.walker.walksPending::14 101000 0.00% 100.00% # Table walker pending requests distribution
464 system.cpu0.dtb.walker.walksPending::15 441500 0.00% 100.00% # Table walker pending requests distribution
465 system.cpu0.dtb.walker.walksPending::total 87200107652 # Table walker pending requests distribution
466 system.cpu0.dtb.walker.walkPageSizes::4K 5974 77.64% 77.64% # Table walker page sizes translated
467 system.cpu0.dtb.walker.walkPageSizes::1M 1720 22.36% 100.00% # Table walker page sizes translated
468 system.cpu0.dtb.walker.walkPageSizes::total 7694 # Table walker page sizes translated
469 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71875 # Table walker requests started/completed, data/inst
470 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
471 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71875 # Table walker requests started/completed, data/inst
472 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7694 # Table walker requests started/completed, data/inst
473 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
474 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7694 # Table walker requests started/completed, data/inst
475 system.cpu0.dtb.walker.walkRequestOrigin::total 79569 # Table walker requests started/completed, data/inst
476 system.cpu0.dtb.inst_hits 0 # ITB inst hits
477 system.cpu0.dtb.inst_misses 0 # ITB inst misses
478 system.cpu0.dtb.read_hits 24391036 # DTB read hits
479 system.cpu0.dtb.read_misses 61424 # DTB read misses
480 system.cpu0.dtb.write_hits 18141184 # DTB write hits
481 system.cpu0.dtb.write_misses 10451 # DTB write misses
482 system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
483 system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
484 system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
485 system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
486 system.cpu0.dtb.flush_entries 3871 # Number of entries that have been flushed from TLB
487 system.cpu0.dtb.align_faults 259 # Number of TLB faults due to alignment restrictions
488 system.cpu0.dtb.prefetch_faults 2351 # Number of TLB faults due to prefetch
489 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
490 system.cpu0.dtb.perms_faults 984 # Number of TLB faults due to permissions restrictions
491 system.cpu0.dtb.read_accesses 24452460 # DTB read accesses
492 system.cpu0.dtb.write_accesses 18151635 # DTB write accesses
493 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
494 system.cpu0.dtb.hits 42532220 # DTB hits
495 system.cpu0.dtb.misses 71875 # DTB misses
496 system.cpu0.dtb.accesses 42604095 # DTB accesses
497 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
498 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
499 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
500 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
501 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
502 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
503 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
504 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
505 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
506 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
507 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
508 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
509 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
510 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
511 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
512 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
513 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
514 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
515 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
516 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
517 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
518 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
519 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
520 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
521 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
522 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
523 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
524 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
525 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
526 system.cpu0.itb.walker.walks 11562 # Table walker walks requested
527 system.cpu0.itb.walker.walksShort 11562 # Table walker walks initiated with short descriptors
528 system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4001 # Level at which table walker walks with short descriptors terminate
529 system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6396 # Level at which table walker walks with short descriptors terminate
530 system.cpu0.itb.walker.walksSquashedBefore 1165 # Table walks squashed before starting
531 system.cpu0.itb.walker.walkWaitTime::samples 10397 # Table walker wait (enqueue to first request) latency
532 system.cpu0.itb.walker.walkWaitTime::mean 461.575454 # Table walker wait (enqueue to first request) latency
533 system.cpu0.itb.walker.walkWaitTime::stdev 2367.707906 # Table walker wait (enqueue to first request) latency
534 system.cpu0.itb.walker.walkWaitTime::0-4095 9981 96.00% 96.00% # Table walker wait (enqueue to first request) latency
535 system.cpu0.itb.walker.walkWaitTime::4096-8191 185 1.78% 97.78% # Table walker wait (enqueue to first request) latency
536 system.cpu0.itb.walker.walkWaitTime::8192-12287 127 1.22% 99.00% # Table walker wait (enqueue to first request) latency
537 system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.57% 99.57% # Table walker wait (enqueue to first request) latency
538 system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.67% # Table walker wait (enqueue to first request) latency
539 system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.22% 99.89% # Table walker wait (enqueue to first request) latency
540 system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
541 system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency
542 system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency
543 system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
544 system.cpu0.itb.walker.walkWaitTime::total 10397 # Table walker wait (enqueue to first request) latency
545 system.cpu0.itb.walker.walkCompletionTime::samples 4031 # Table walker service (enqueue to completion) latency
546 system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110 # Table walker service (enqueue to completion) latency
547 system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949 # Table walker service (enqueue to completion) latency
548 system.cpu0.itb.walker.walkCompletionTime::stdev 5265.028524 # Table walker service (enqueue to completion) latency
549 system.cpu0.itb.walker.walkCompletionTime::0-16383 3778 93.72% 93.72% # Table walker service (enqueue to completion) latency
550 system.cpu0.itb.walker.walkCompletionTime::16384-32767 218 5.41% 99.13% # Table walker service (enqueue to completion) latency
551 system.cpu0.itb.walker.walkCompletionTime::32768-49151 33 0.82% 99.95% # Table walker service (enqueue to completion) latency
552 system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
553 system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
554 system.cpu0.itb.walker.walkCompletionTime::total 4031 # Table walker service (enqueue to completion) latency
555 system.cpu0.itb.walker.walksPending::samples 22774753212 # Table walker pending requests distribution
556 system.cpu0.itb.walker.walksPending::mean 0.815515 # Table walker pending requests distribution
557 system.cpu0.itb.walker.walksPending::stdev 0.388020 # Table walker pending requests distribution
558 system.cpu0.itb.walker.walksPending::0 4202728000 18.45% 18.45% # Table walker pending requests distribution
559 system.cpu0.itb.walker.walksPending::1 18570993712 81.54% 100.00% # Table walker pending requests distribution
560 system.cpu0.itb.walker.walksPending::2 925000 0.00% 100.00% # Table walker pending requests distribution
561 system.cpu0.itb.walker.walksPending::3 106500 0.00% 100.00% # Table walker pending requests distribution
562 system.cpu0.itb.walker.walksPending::total 22774753212 # Table walker pending requests distribution
563 system.cpu0.itb.walker.walkPageSizes::4K 2507 87.47% 87.47% # Table walker page sizes translated
564 system.cpu0.itb.walker.walkPageSizes::1M 359 12.53% 100.00% # Table walker page sizes translated
565 system.cpu0.itb.walker.walkPageSizes::total 2866 # Table walker page sizes translated
566 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
567 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11562 # Table walker requests started/completed, data/inst
568 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11562 # Table walker requests started/completed, data/inst
569 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
570 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2866 # Table walker requests started/completed, data/inst
571 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2866 # Table walker requests started/completed, data/inst
572 system.cpu0.itb.walker.walkRequestOrigin::total 14428 # Table walker requests started/completed, data/inst
573 system.cpu0.itb.inst_hits 74050785 # ITB inst hits
574 system.cpu0.itb.inst_misses 11562 # ITB inst misses
575 system.cpu0.itb.read_hits 0 # DTB read hits
576 system.cpu0.itb.read_misses 0 # DTB read misses
577 system.cpu0.itb.write_hits 0 # DTB write hits
578 system.cpu0.itb.write_misses 0 # DTB write misses
579 system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
580 system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
581 system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
582 system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
583 system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB
584 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
585 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
586 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
587 system.cpu0.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
588 system.cpu0.itb.read_accesses 0 # DTB read accesses
589 system.cpu0.itb.write_accesses 0 # DTB write accesses
590 system.cpu0.itb.inst_accesses 74062347 # ITB inst accesses
591 system.cpu0.itb.hits 74050785 # DTB hits
592 system.cpu0.itb.misses 11562 # DTB misses
593 system.cpu0.itb.accesses 74062347 # DTB accesses
594 system.cpu0.numCycles 210807967 # number of cpu cycles simulated
595 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
596 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
597 system.cpu0.fetch.icacheStallCycles 21220653 # Number of cycles fetch is stalled on an Icache miss
598 system.cpu0.fetch.Insts 200130599 # Number of instructions fetch has processed
599 system.cpu0.fetch.Branches 53911245 # Number of branches that fetch encountered
600 system.cpu0.fetch.predictedBranches 39833210 # Number of branches that fetch has predicted taken
601 system.cpu0.fetch.Cycles 180362708 # Number of cycles fetch has run and was not squashing or blocked
602 system.cpu0.fetch.SquashCycles 5820684 # Number of cycles fetch has spent squashing
603 system.cpu0.fetch.TlbCycles 154995 # Number of cycles fetch has spent waiting for tlb
604 system.cpu0.fetch.MiscStallCycles 66964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
605 system.cpu0.fetch.PendingTrapStallCycles 420974 # Number of stall cycles due to pending traps
606 system.cpu0.fetch.PendingQuiesceStallCycles 452324 # Number of stall cycles due to pending quiesce instructions
607 system.cpu0.fetch.IcacheWaitRetryStallCycles 103497 # Number of stall cycles due to full MSHR
608 system.cpu0.fetch.CacheLines 74050081 # Number of cache lines fetched
609 system.cpu0.fetch.IcacheSquashes 272746 # Number of outstanding Icache misses that were squashed
610 system.cpu0.fetch.ItlbSquashes 5705 # Number of outstanding ITLB misses that were squashed
611 system.cpu0.fetch.rateDist::samples 205692457 # Number of instructions fetched each cycle (Total)
612 system.cpu0.fetch.rateDist::mean 1.188766 # Number of instructions fetched each cycle (Total)
613 system.cpu0.fetch.rateDist::stdev 1.306289 # Number of instructions fetched each cycle (Total)
614 system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
615 system.cpu0.fetch.rateDist::0 98524588 47.90% 47.90% # Number of instructions fetched each cycle (Total)
616 system.cpu0.fetch.rateDist::1 31037557 15.09% 62.99% # Number of instructions fetched each cycle (Total)
617 system.cpu0.fetch.rateDist::2 14908217 7.25% 70.24% # Number of instructions fetched each cycle (Total)
618 system.cpu0.fetch.rateDist::3 61222095 29.76% 100.00% # Number of instructions fetched each cycle (Total)
619 system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
620 system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
621 system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
622 system.cpu0.fetch.rateDist::total 205692457 # Number of instructions fetched each cycle (Total)
623 system.cpu0.fetch.branchRate 0.255736 # Number of branch fetches per cycle
624 system.cpu0.fetch.rate 0.949350 # Number of inst fetches per cycle
625 system.cpu0.decode.IdleCycles 26429213 # Number of cycles decode is idle
626 system.cpu0.decode.BlockedCycles 111222366 # Number of cycles decode is blocked
627 system.cpu0.decode.RunCycles 60319076 # Number of cycles decode is running
628 system.cpu0.decode.UnblockCycles 5157963 # Number of cycles decode is unblocking
629 system.cpu0.decode.SquashCycles 2563839 # Number of cycles decode is squashing
630 system.cpu0.decode.BranchResolved 3171648 # Number of times decode resolved a branch
631 system.cpu0.decode.BranchMispred 350947 # Number of times decode detected a branch misprediction
632 system.cpu0.decode.DecodedInsts 158388827 # Number of instructions handled by decode
633 system.cpu0.decode.SquashedInsts 4014782 # Number of squashed instructions handled by decode
634 system.cpu0.rename.SquashCycles 2563839 # Number of cycles rename is squashing
635 system.cpu0.rename.IdleCycles 35280795 # Number of cycles rename is idle
636 system.cpu0.rename.BlockCycles 13301493 # Number of cycles rename is blocking
637 system.cpu0.rename.serializeStallCycles 85153816 # count of cycles rename stalled for serializing inst
638 system.cpu0.rename.RunCycles 56482950 # Number of cycles rename is running
639 system.cpu0.rename.UnblockCycles 12909564 # Number of cycles rename is unblocking
640 system.cpu0.rename.RenamedInsts 141500597 # Number of instructions processed by rename
641 system.cpu0.rename.SquashedInsts 1085672 # Number of squashed instructions processed by rename
642 system.cpu0.rename.ROBFullEvents 1524488 # Number of times rename has blocked due to ROB full
643 system.cpu0.rename.IQFullEvents 177088 # Number of times rename has blocked due to IQ full
644 system.cpu0.rename.LQFullEvents 62946 # Number of times rename has blocked due to LQ full
645 system.cpu0.rename.SQFullEvents 8550384 # Number of times rename has blocked due to SQ full
646 system.cpu0.rename.RenamedOperands 145816753 # Number of destination operands rename has renamed
647 system.cpu0.rename.RenameLookups 652563275 # Number of register rename lookups that rename has made
648 system.cpu0.rename.int_rename_lookups 157207618 # Number of integer rename lookups
649 system.cpu0.rename.fp_rename_lookups 11000 # Number of floating rename lookups
650 system.cpu0.rename.CommittedMaps 133932927 # Number of HB maps that are committed
651 system.cpu0.rename.UndoneMaps 11883815 # Number of HB maps that are undone due to squashing
652 system.cpu0.rename.serializingInsts 2738789 # count of serializing insts renamed
653 system.cpu0.rename.tempSerializingInsts 2591099 # count of temporary serializing insts renamed
654 system.cpu0.rename.skidInsts 23044959 # count of insts added to the skid buffer
655 system.cpu0.memDep0.insertedLoads 25364147 # Number of loads inserted to the mem dependence unit.
656 system.cpu0.memDep0.insertedStores 19673316 # Number of stores inserted to the mem dependence unit.
657 system.cpu0.memDep0.conflictingLoads 1767343 # Number of conflicting loads.
658 system.cpu0.memDep0.conflictingStores 2535257 # Number of conflicting stores.
659 system.cpu0.iq.iqInstsAdded 138424520 # Number of instructions added to the IQ (excludes non-spec)
660 system.cpu0.iq.iqNonSpecInstsAdded 1769995 # Number of non-speculative instructions added to the IQ
661 system.cpu0.iq.iqInstsIssued 136412034 # Number of instructions issued
662 system.cpu0.iq.iqSquashedInstsIssued 484040 # Number of squashed instructions issued
663 system.cpu0.iq.iqSquashedInstsExamined 11120854 # Number of squashed instructions iterated over during squash; mainly for profiling
664 system.cpu0.iq.iqSquashedOperandsExamined 22999814 # Number of squashed operands that are examined and possibly removed from graph
665 system.cpu0.iq.iqSquashedNonSpecRemoved 127192 # Number of squashed non-spec instructions that were removed
666 system.cpu0.iq.issued_per_cycle::samples 205692457 # Number of insts issued each cycle
667 system.cpu0.iq.issued_per_cycle::mean 0.663184 # Number of insts issued each cycle
668 system.cpu0.iq.issued_per_cycle::stdev 0.962224 # Number of insts issued each cycle
669 system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
670 system.cpu0.iq.issued_per_cycle::0 126945183 61.72% 61.72% # Number of insts issued each cycle
671 system.cpu0.iq.issued_per_cycle::1 34499506 16.77% 78.49% # Number of insts issued each cycle
672 system.cpu0.iq.issued_per_cycle::2 31998886 15.56% 94.05% # Number of insts issued each cycle
673 system.cpu0.iq.issued_per_cycle::3 11080832 5.39% 99.43% # Number of insts issued each cycle
674 system.cpu0.iq.issued_per_cycle::4 1167990 0.57% 100.00% # Number of insts issued each cycle
675 system.cpu0.iq.issued_per_cycle::5 60 0.00% 100.00% # Number of insts issued each cycle
676 system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
677 system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
678 system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
679 system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
680 system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
681 system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
682 system.cpu0.iq.issued_per_cycle::total 205692457 # Number of insts issued each cycle
683 system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
684 system.cpu0.iq.fu_full::IntAlu 11130033 43.82% 43.82% # attempts to use FU when none available
685 system.cpu0.iq.fu_full::IntMult 71 0.00% 43.82% # attempts to use FU when none available
686 system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.82% # attempts to use FU when none available
687 system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.82% # attempts to use FU when none available
688 system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.82% # attempts to use FU when none available
689 system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.82% # attempts to use FU when none available
690 system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.82% # attempts to use FU when none available
691 system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.82% # attempts to use FU when none available
692 system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
693 system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.82% # attempts to use FU when none available
694 system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.82% # attempts to use FU when none available
695 system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.82% # attempts to use FU when none available
696 system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.82% # attempts to use FU when none available
697 system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.82% # attempts to use FU when none available
698 system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.82% # attempts to use FU when none available
699 system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.82% # attempts to use FU when none available
700 system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.82% # attempts to use FU when none available
701 system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.82% # attempts to use FU when none available
702 system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.82% # attempts to use FU when none available
703 system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.82% # attempts to use FU when none available
704 system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.82% # attempts to use FU when none available
705 system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.82% # attempts to use FU when none available
706 system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.82% # attempts to use FU when none available
707 system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.82% # attempts to use FU when none available
708 system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.82% # attempts to use FU when none available
709 system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.82% # attempts to use FU when none available
710 system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.82% # attempts to use FU when none available
711 system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.82% # attempts to use FU when none available
712 system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
713 system.cpu0.iq.fu_full::MemRead 5937286 23.38% 67.20% # attempts to use FU when none available
714 system.cpu0.iq.fu_full::MemWrite 8330186 32.80% 100.00% # attempts to use FU when none available
715 system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
716 system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
717 system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
718 system.cpu0.iq.FU_type_0::IntAlu 91960000 67.41% 67.42% # Type of FU issued
719 system.cpu0.iq.FU_type_0::IntMult 113905 0.08% 67.50% # Type of FU issued
720 system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
721 system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.50% # Type of FU issued
722 system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.50% # Type of FU issued
723 system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.50% # Type of FU issued
724 system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.50% # Type of FU issued
725 system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.50% # Type of FU issued
726 system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.50% # Type of FU issued
727 system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.50% # Type of FU issued
728 system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.50% # Type of FU issued
729 system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.50% # Type of FU issued
730 system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.50% # Type of FU issued
731 system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.50% # Type of FU issued
732 system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.50% # Type of FU issued
733 system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.50% # Type of FU issued
734 system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.50% # Type of FU issued
735 system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.50% # Type of FU issued
736 system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.50% # Type of FU issued
737 system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.50% # Type of FU issued
738 system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.50% # Type of FU issued
739 system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.50% # Type of FU issued
740 system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.50% # Type of FU issued
741 system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.50% # Type of FU issued
742 system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.50% # Type of FU issued
743 system.cpu0.iq.FU_type_0::SimdFloatMisc 8243 0.01% 67.50% # Type of FU issued
744 system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued
745 system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued
746 system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued
747 system.cpu0.iq.FU_type_0::MemRead 25115664 18.41% 85.92% # Type of FU issued
748 system.cpu0.iq.FU_type_0::MemWrite 19211906 14.08% 100.00% # Type of FU issued
749 system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
750 system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
751 system.cpu0.iq.FU_type_0::total 136412034 # Type of FU issued
752 system.cpu0.iq.rate 0.647091 # Inst issue rate
753 system.cpu0.iq.fu_busy_cnt 25397576 # FU busy when requested
754 system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst)
755 system.cpu0.iq.int_inst_queue_reads 504359597 # Number of integer instruction queue reads
756 system.cpu0.iq.int_inst_queue_writes 151322890 # Number of integer instruction queue writes
757 system.cpu0.iq.int_inst_queue_wakeup_accesses 132769388 # Number of integer instruction queue wakeup accesses
758 system.cpu0.iq.fp_inst_queue_reads 38543 # Number of floating instruction queue reads
759 system.cpu0.iq.fp_inst_queue_writes 13252 # Number of floating instruction queue writes
760 system.cpu0.iq.fp_inst_queue_wakeup_accesses 11438 # Number of floating instruction queue wakeup accesses
761 system.cpu0.iq.int_alu_accesses 161782111 # Number of integer alu accesses
762 system.cpu0.iq.fp_alu_accesses 25184 # Number of floating point alu accesses
763 system.cpu0.iew.lsq.thread0.forwLoads 383563 # Number of loads that had data forwarded from stores
764 system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
765 system.cpu0.iew.lsq.thread0.squashedLoads 2036205 # Number of loads squashed
766 system.cpu0.iew.lsq.thread0.ignoredResponses 2638 # Number of memory responses ignored because the instruction is squashed
767 system.cpu0.iew.lsq.thread0.memOrderViolation 20853 # Number of memory ordering violations
768 system.cpu0.iew.lsq.thread0.squashedStores 948035 # Number of stores squashed
769 system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
770 system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
771 system.cpu0.iew.lsq.thread0.rescheduledLoads 126036 # Number of loads that were rescheduled
772 system.cpu0.iew.lsq.thread0.cacheBlocked 394781 # Number of times an access to memory failed due to the cache being blocked
773 system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
774 system.cpu0.iew.iewSquashCycles 2563839 # Number of cycles IEW is squashing
775 system.cpu0.iew.iewBlockCycles 1921080 # Number of cycles IEW is blocking
776 system.cpu0.iew.iewUnblockCycles 231914 # Number of cycles IEW is unblocking
777 system.cpu0.iew.iewDispatchedInsts 140382056 # Number of instructions dispatched to IQ
778 system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
779 system.cpu0.iew.iewDispLoadInsts 25364147 # Number of dispatched load instructions
780 system.cpu0.iew.iewDispStoreInsts 19673316 # Number of dispatched store instructions
781 system.cpu0.iew.iewDispNonSpecInsts 906447 # Number of dispatched non-speculative instructions
782 system.cpu0.iew.iewIQFullEvents 31018 # Number of times the IQ has become full, causing a stall
783 system.cpu0.iew.iewLSQFullEvents 175567 # Number of times the LSQ has become full, causing a stall
784 system.cpu0.iew.memOrderViolationEvents 20853 # Number of memory order violations
785 system.cpu0.iew.predictedTakenIncorrect 275420 # Number of branches that were predicted taken incorrectly
786 system.cpu0.iew.predictedNotTakenIncorrect 424017 # Number of branches that were predicted not taken incorrectly
787 system.cpu0.iew.branchMispredicts 699437 # Number of branch mispredicts detected at execute
788 system.cpu0.iew.iewExecutedInsts 135325292 # Number of executed instructions
789 system.cpu0.iew.iewExecLoadInsts 24646519 # Number of load instructions executed
790 system.cpu0.iew.iewExecSquashedInsts 1015002 # Number of squashed instructions skipped in execute
791 system.cpu0.iew.exec_swp 0 # number of swp insts executed
792 system.cpu0.iew.exec_nop 187541 # number of nop insts executed
793 system.cpu0.iew.exec_refs 43690093 # number of memory reference insts executed
794 system.cpu0.iew.exec_branches 26111417 # Number of branches executed
795 system.cpu0.iew.exec_stores 19043574 # Number of stores executed
796 system.cpu0.iew.exec_rate 0.641936 # Inst execution rate
797 system.cpu0.iew.wb_sent 134725872 # cumulative count of insts sent to commit
798 system.cpu0.iew.wb_count 132780826 # cumulative count of insts written-back
799 system.cpu0.iew.wb_producers 67751819 # num instructions producing a value
800 system.cpu0.iew.wb_consumers 109549817 # num instructions consuming a value
801 system.cpu0.iew.wb_rate 0.629866 # insts written-back per cycle
802 system.cpu0.iew.wb_fanout 0.618457 # average fanout of values written-back
803 system.cpu0.commit.commitSquashedInsts 10037586 # The number of squashed insts skipped by commit
804 system.cpu0.commit.commitNonSpecStalls 1642803 # The number of times commit has been forced to stall to communicate backwards
805 system.cpu0.commit.branchMispredicts 638504 # The number of times a branch was mispredicted
806 system.cpu0.commit.committed_per_cycle::samples 202442995 # Number of insts commited each cycle
807 system.cpu0.commit.committed_per_cycle::mean 0.638330 # Number of insts commited each cycle
808 system.cpu0.commit.committed_per_cycle::stdev 1.339217 # Number of insts commited each cycle
809 system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
810 system.cpu0.commit.committed_per_cycle::0 140546392 69.43% 69.43% # Number of insts commited each cycle
811 system.cpu0.commit.committed_per_cycle::1 34245976 16.92% 86.34% # Number of insts commited each cycle
812 system.cpu0.commit.committed_per_cycle::2 12926596 6.39% 92.73% # Number of insts commited each cycle
813 system.cpu0.commit.committed_per_cycle::3 3383235 1.67% 94.40% # Number of insts commited each cycle
814 system.cpu0.commit.committed_per_cycle::4 4977119 2.46% 96.86% # Number of insts commited each cycle
815 system.cpu0.commit.committed_per_cycle::5 2872114 1.42% 98.28% # Number of insts commited each cycle
816 system.cpu0.commit.committed_per_cycle::6 1322991 0.65% 98.93% # Number of insts commited each cycle
817 system.cpu0.commit.committed_per_cycle::7 578946 0.29% 99.21% # Number of insts commited each cycle
818 system.cpu0.commit.committed_per_cycle::8 1589626 0.79% 100.00% # Number of insts commited each cycle
819 system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
820 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
821 system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
822 system.cpu0.commit.committed_per_cycle::total 202442995 # Number of insts commited each cycle
823 system.cpu0.commit.committedInsts 106684229 # Number of instructions committed
824 system.cpu0.commit.committedOps 129225495 # Number of ops (including micro ops) committed
825 system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
826 system.cpu0.commit.refs 42053222 # Number of memory references committed
827 system.cpu0.commit.loads 23327941 # Number of loads committed
828 system.cpu0.commit.membars 666720 # Number of memory barriers committed
829 system.cpu0.commit.branches 25467916 # Number of branches committed
830 system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
831 system.cpu0.commit.int_insts 112793765 # Number of committed integer instructions.
832 system.cpu0.commit.function_calls 4892953 # Number of function calls committed.
833 system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
834 system.cpu0.commit.op_class_0::IntAlu 87052485 67.36% 67.36% # Class of committed instruction
835 system.cpu0.commit.op_class_0::IntMult 111545 0.09% 67.45% # Class of committed instruction
836 system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
837 system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
838 system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction
839 system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
840 system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction
841 system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction
842 system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction
843 system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction
844 system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction
845 system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction
846 system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction
847 system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction
848 system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction
849 system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction
850 system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction
851 system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction
852 system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction
853 system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction
854 system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction
855 system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction
856 system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction
857 system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction
858 system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction
859 system.cpu0.commit.op_class_0::SimdFloatMisc 8243 0.01% 67.46% # Class of committed instruction
860 system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction
861 system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction
862 system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction
863 system.cpu0.commit.op_class_0::MemRead 23327941 18.05% 85.51% # Class of committed instruction
864 system.cpu0.commit.op_class_0::MemWrite 18725281 14.49% 100.00% # Class of committed instruction
865 system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
866 system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
867 system.cpu0.commit.op_class_0::total 129225495 # Class of committed instruction
868 system.cpu0.commit.bw_lim_events 1589626 # number cycles where commit BW limit reached
869 system.cpu0.rob.rob_reads 316721982 # The number of ROB reads
870 system.cpu0.rob.rob_writes 281765642 # The number of ROB writes
871 system.cpu0.timesIdled 131866 # Number of times that the entire CPU went into an idle state and unscheduled itself
872 system.cpu0.idleCycles 5115510 # Total number of cycles that the CPU has spent unscheduled due to idling
873 system.cpu0.quiesceCycles 5443972636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
874 system.cpu0.committedInsts 106532386 # Number of Instructions Simulated
875 system.cpu0.committedOps 129073652 # Number of Ops (including micro ops) Simulated
876 system.cpu0.cpi 1.978816 # CPI: Cycles Per Instruction
877 system.cpu0.cpi_total 1.978816 # CPI: Total CPI of All Threads
878 system.cpu0.ipc 0.505353 # IPC: Instructions Per Cycle
879 system.cpu0.ipc_total 0.505353 # IPC: Total IPC of All Threads
880 system.cpu0.int_regfile_reads 146797472 # number of integer regfile reads
881 system.cpu0.int_regfile_writes 83857123 # number of integer regfile writes
882 system.cpu0.fp_regfile_reads 9583 # number of floating regfile reads
883 system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
884 system.cpu0.cc_regfile_reads 477737826 # number of cc regfile reads
885 system.cpu0.cc_regfile_writes 51222601 # number of cc regfile writes
886 system.cpu0.misc_regfile_reads 282455977 # number of misc regfile reads
887 system.cpu0.misc_regfile_writes 1264842 # number of misc regfile writes
888 system.cpu0.dcache.tags.replacements 752726 # number of replacements
889 system.cpu0.dcache.tags.tagsinuse 494.858519 # Cycle average of tags in use
890 system.cpu0.dcache.tags.total_refs 38773458 # Total number of references to valid blocks.
891 system.cpu0.dcache.tags.sampled_refs 753238 # Sample count of references to valid blocks.
892 system.cpu0.dcache.tags.avg_refs 51.475706 # Average number of references to valid blocks.
893 system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
894 system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.858519 # Average occupied blocks per requestor
895 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966521 # Average percentage of cache occupancy
896 system.cpu0.dcache.tags.occ_percent::total 0.966521 # Average percentage of cache occupancy
897 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
898 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
899 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
900 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
901 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
902 system.cpu0.dcache.tags.tag_accesses 83704103 # Number of tag accesses
903 system.cpu0.dcache.tags.data_accesses 83704103 # Number of data accesses
904 system.cpu0.dcache.ReadReq_hits::cpu0.data 22086605 # number of ReadReq hits
905 system.cpu0.dcache.ReadReq_hits::total 22086605 # number of ReadReq hits
906 system.cpu0.dcache.WriteReq_hits::cpu0.data 15435818 # number of WriteReq hits
907 system.cpu0.dcache.WriteReq_hits::total 15435818 # number of WriteReq hits
908 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316186 # number of SoftPFReq hits
909 system.cpu0.dcache.SoftPFReq_hits::total 316186 # number of SoftPFReq hits
910 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 372593 # number of LoadLockedReq hits
911 system.cpu0.dcache.LoadLockedReq_hits::total 372593 # number of LoadLockedReq hits
912 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370988 # number of StoreCondReq hits
913 system.cpu0.dcache.StoreCondReq_hits::total 370988 # number of StoreCondReq hits
914 system.cpu0.dcache.demand_hits::cpu0.data 37522423 # number of demand (read+write) hits
915 system.cpu0.dcache.demand_hits::total 37522423 # number of demand (read+write) hits
916 system.cpu0.dcache.overall_hits::cpu0.data 37838609 # number of overall hits
917 system.cpu0.dcache.overall_hits::total 37838609 # number of overall hits
918 system.cpu0.dcache.ReadReq_misses::cpu0.data 688506 # number of ReadReq misses
919 system.cpu0.dcache.ReadReq_misses::total 688506 # number of ReadReq misses
920 system.cpu0.dcache.WriteReq_misses::cpu0.data 1977745 # number of WriteReq misses
921 system.cpu0.dcache.WriteReq_misses::total 1977745 # number of WriteReq misses
922 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 154100 # number of SoftPFReq misses
923 system.cpu0.dcache.SoftPFReq_misses::total 154100 # number of SoftPFReq misses
924 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25656 # number of LoadLockedReq misses
925 system.cpu0.dcache.LoadLockedReq_misses::total 25656 # number of LoadLockedReq misses
926 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20273 # number of StoreCondReq misses
927 system.cpu0.dcache.StoreCondReq_misses::total 20273 # number of StoreCondReq misses
928 system.cpu0.dcache.demand_misses::cpu0.data 2666251 # number of demand (read+write) misses
929 system.cpu0.dcache.demand_misses::total 2666251 # number of demand (read+write) misses
930 system.cpu0.dcache.overall_misses::cpu0.data 2820351 # number of overall misses
931 system.cpu0.dcache.overall_misses::total 2820351 # number of overall misses
932 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9974637500 # number of ReadReq miss cycles
933 system.cpu0.dcache.ReadReq_miss_latency::total 9974637500 # number of ReadReq miss cycles
934 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36928416860 # number of WriteReq miss cycles
935 system.cpu0.dcache.WriteReq_miss_latency::total 36928416860 # number of WriteReq miss cycles
936 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417346500 # number of LoadLockedReq miss cycles
937 system.cpu0.dcache.LoadLockedReq_miss_latency::total 417346500 # number of LoadLockedReq miss cycles
938 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 525290500 # number of StoreCondReq miss cycles
939 system.cpu0.dcache.StoreCondReq_miss_latency::total 525290500 # number of StoreCondReq miss cycles
940 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 179000 # number of StoreCondFailReq miss cycles
941 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 179000 # number of StoreCondFailReq miss cycles
942 system.cpu0.dcache.demand_miss_latency::cpu0.data 46903054360 # number of demand (read+write) miss cycles
943 system.cpu0.dcache.demand_miss_latency::total 46903054360 # number of demand (read+write) miss cycles
944 system.cpu0.dcache.overall_miss_latency::cpu0.data 46903054360 # number of overall miss cycles
945 system.cpu0.dcache.overall_miss_latency::total 46903054360 # number of overall miss cycles
946 system.cpu0.dcache.ReadReq_accesses::cpu0.data 22775111 # number of ReadReq accesses(hits+misses)
947 system.cpu0.dcache.ReadReq_accesses::total 22775111 # number of ReadReq accesses(hits+misses)
948 system.cpu0.dcache.WriteReq_accesses::cpu0.data 17413563 # number of WriteReq accesses(hits+misses)
949 system.cpu0.dcache.WriteReq_accesses::total 17413563 # number of WriteReq accesses(hits+misses)
950 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470286 # number of SoftPFReq accesses(hits+misses)
951 system.cpu0.dcache.SoftPFReq_accesses::total 470286 # number of SoftPFReq accesses(hits+misses)
952 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 398249 # number of LoadLockedReq accesses(hits+misses)
953 system.cpu0.dcache.LoadLockedReq_accesses::total 398249 # number of LoadLockedReq accesses(hits+misses)
954 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391261 # number of StoreCondReq accesses(hits+misses)
955 system.cpu0.dcache.StoreCondReq_accesses::total 391261 # number of StoreCondReq accesses(hits+misses)
956 system.cpu0.dcache.demand_accesses::cpu0.data 40188674 # number of demand (read+write) accesses
957 system.cpu0.dcache.demand_accesses::total 40188674 # number of demand (read+write) accesses
958 system.cpu0.dcache.overall_accesses::cpu0.data 40658960 # number of overall (read+write) accesses
959 system.cpu0.dcache.overall_accesses::total 40658960 # number of overall (read+write) accesses
960 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030231 # miss rate for ReadReq accesses
961 system.cpu0.dcache.ReadReq_miss_rate::total 0.030231 # miss rate for ReadReq accesses
962 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113575 # miss rate for WriteReq accesses
963 system.cpu0.dcache.WriteReq_miss_rate::total 0.113575 # miss rate for WriteReq accesses
964 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327673 # miss rate for SoftPFReq accesses
965 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327673 # miss rate for SoftPFReq accesses
966 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064422 # miss rate for LoadLockedReq accesses
967 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064422 # miss rate for LoadLockedReq accesses
968 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051815 # miss rate for StoreCondReq accesses
969 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051815 # miss rate for StoreCondReq accesses
970 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066343 # miss rate for demand accesses
971 system.cpu0.dcache.demand_miss_rate::total 0.066343 # miss rate for demand accesses
972 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069366 # miss rate for overall accesses
973 system.cpu0.dcache.overall_miss_rate::total 0.069366 # miss rate for overall accesses
974 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671 # average ReadReq miss latency
975 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671 # average ReadReq miss latency
976 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897 # average WriteReq miss latency
977 system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897 # average WriteReq miss latency
978 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16267.013564 # average LoadLockedReq miss latency
979 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564 # average LoadLockedReq miss latency
980 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007 # average StoreCondReq miss latency
981 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007 # average StoreCondReq miss latency
982 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
983 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
984 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443 # average overall miss latency
985 system.cpu0.dcache.demand_avg_miss_latency::total 17591.387443 # average overall miss latency
986 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849 # average overall miss latency
987 system.cpu0.dcache.overall_avg_miss_latency::total 16630.218849 # average overall miss latency
988 system.cpu0.dcache.blocked_cycles::no_mshrs 989 # number of cycles access was blocked
989 system.cpu0.dcache.blocked_cycles::no_targets 5684279 # number of cycles access was blocked
990 system.cpu0.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
991 system.cpu0.dcache.blocked::no_targets 212555 # number of cycles access was blocked
992 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.019231 # average number of cycles each access was blocked
993 system.cpu0.dcache.avg_blocked_cycles::no_targets 26.742627 # average number of cycles each access was blocked
994 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
995 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
996 system.cpu0.dcache.writebacks::writebacks 752726 # number of writebacks
997 system.cpu0.dcache.writebacks::total 752726 # number of writebacks
998 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276877 # number of ReadReq MSHR hits
999 system.cpu0.dcache.ReadReq_mshr_hits::total 276877 # number of ReadReq MSHR hits
1000 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1641015 # number of WriteReq MSHR hits
1001 system.cpu0.dcache.WriteReq_mshr_hits::total 1641015 # number of WriteReq MSHR hits
1002 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18966 # number of LoadLockedReq MSHR hits
1003 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18966 # number of LoadLockedReq MSHR hits
1004 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1917892 # number of demand (read+write) MSHR hits
1005 system.cpu0.dcache.demand_mshr_hits::total 1917892 # number of demand (read+write) MSHR hits
1006 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1917892 # number of overall MSHR hits
1007 system.cpu0.dcache.overall_mshr_hits::total 1917892 # number of overall MSHR hits
1008 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411629 # number of ReadReq MSHR misses
1009 system.cpu0.dcache.ReadReq_mshr_misses::total 411629 # number of ReadReq MSHR misses
1010 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336730 # number of WriteReq MSHR misses
1011 system.cpu0.dcache.WriteReq_mshr_misses::total 336730 # number of WriteReq MSHR misses
1012 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107461 # number of SoftPFReq MSHR misses
1013 system.cpu0.dcache.SoftPFReq_mshr_misses::total 107461 # number of SoftPFReq MSHR misses
1014 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6690 # number of LoadLockedReq MSHR misses
1015 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6690 # number of LoadLockedReq MSHR misses
1016 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20273 # number of StoreCondReq MSHR misses
1017 system.cpu0.dcache.StoreCondReq_mshr_misses::total 20273 # number of StoreCondReq MSHR misses
1018 system.cpu0.dcache.demand_mshr_misses::cpu0.data 748359 # number of demand (read+write) MSHR misses
1019 system.cpu0.dcache.demand_mshr_misses::total 748359 # number of demand (read+write) MSHR misses
1020 system.cpu0.dcache.overall_mshr_misses::cpu0.data 855820 # number of overall MSHR misses
1021 system.cpu0.dcache.overall_mshr_misses::total 855820 # number of overall MSHR misses
1022 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
1023 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31816 # number of ReadReq MSHR uncacheable
1024 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
1025 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1026 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
1027 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60315 # number of overall MSHR uncacheable misses
1028 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149646500 # number of ReadReq MSHR miss cycles
1029 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149646500 # number of ReadReq MSHR miss cycles
1030 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7737247391 # number of WriteReq MSHR miss cycles
1031 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7737247391 # number of WriteReq MSHR miss cycles
1032 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800196500 # number of SoftPFReq MSHR miss cycles
1033 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800196500 # number of SoftPFReq MSHR miss cycles
1034 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108932500 # number of LoadLockedReq MSHR miss cycles
1035 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108932500 # number of LoadLockedReq MSHR miss cycles
1036 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 505022500 # number of StoreCondReq MSHR miss cycles
1037 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 505022500 # number of StoreCondReq MSHR miss cycles
1038 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondFailReq MSHR miss cycles
1039 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 174000 # number of StoreCondFailReq MSHR miss cycles
1040 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12886893891 # number of demand (read+write) MSHR miss cycles
1041 system.cpu0.dcache.demand_mshr_miss_latency::total 12886893891 # number of demand (read+write) MSHR miss cycles
1042 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14687090391 # number of overall MSHR miss cycles
1043 system.cpu0.dcache.overall_mshr_miss_latency::total 14687090391 # number of overall MSHR miss cycles
1044 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623903000 # number of ReadReq MSHR uncacheable cycles
1045 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623903000 # number of ReadReq MSHR uncacheable cycles
1046 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395425500 # number of WriteReq MSHR uncacheable cycles
1047 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395425500 # number of WriteReq MSHR uncacheable cycles
1048 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12019328500 # number of overall MSHR uncacheable cycles
1049 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019328500 # number of overall MSHR uncacheable cycles
1050 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018074 # mshr miss rate for ReadReq accesses
1051 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018074 # mshr miss rate for ReadReq accesses
1052 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019337 # mshr miss rate for WriteReq accesses
1053 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019337 # mshr miss rate for WriteReq accesses
1054 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228501 # mshr miss rate for SoftPFReq accesses
1055 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228501 # mshr miss rate for SoftPFReq accesses
1056 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for LoadLockedReq accesses
1057 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016799 # mshr miss rate for LoadLockedReq accesses
1058 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051815 # mshr miss rate for StoreCondReq accesses
1059 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051815 # mshr miss rate for StoreCondReq accesses
1060 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018621 # mshr miss rate for demand accesses
1061 system.cpu0.dcache.demand_mshr_miss_rate::total 0.018621 # mshr miss rate for demand accesses
1062 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021049 # mshr miss rate for overall accesses
1063 system.cpu0.dcache.overall_mshr_miss_rate::total 0.021049 # mshr miss rate for overall accesses
1064 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12510.407430 # average ReadReq mshr miss latency
1065 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430 # average ReadReq mshr miss latency
1066 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22977.600425 # average WriteReq mshr miss latency
1067 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22977.600425 # average WriteReq mshr miss latency
1068 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16752.091456 # average SoftPFReq mshr miss latency
1069 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.091456 # average SoftPFReq mshr miss latency
1070 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16282.884903 # average LoadLockedReq mshr miss latency
1071 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903 # average LoadLockedReq mshr miss latency
1072 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24911.088640 # average StoreCondReq mshr miss latency
1073 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24911.088640 # average StoreCondReq mshr miss latency
1074 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1075 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1076 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17220.202992 # average overall mshr miss latency
1077 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17220.202992 # average overall mshr miss latency
1078 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17161.424588 # average overall mshr miss latency
1079 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17161.424588 # average overall mshr miss latency
1080 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208194.084737 # average ReadReq mshr uncacheable latency
1081 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208194.084737 # average ReadReq mshr uncacheable latency
1082 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189319.818239 # average WriteReq mshr uncacheable latency
1083 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189319.818239 # average WriteReq mshr uncacheable latency
1084 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199275.942966 # average overall mshr uncacheable latency
1085 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966 # average overall mshr uncacheable latency
1086 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1087 system.cpu0.icache.tags.replacements 1311471 # number of replacements
1088 system.cpu0.icache.tags.tagsinuse 511.728689 # Cycle average of tags in use
1089 system.cpu0.icache.tags.total_refs 72677991 # Total number of references to valid blocks.
1090 system.cpu0.icache.tags.sampled_refs 1311983 # Sample count of references to valid blocks.
1091 system.cpu0.icache.tags.avg_refs 55.395528 # Average number of references to valid blocks.
1092 system.cpu0.icache.tags.warmup_cycle 8207383000 # Cycle when the warmup percentage was hit.
1093 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728689 # Average occupied blocks per requestor
1094 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy
1095 system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy
1096 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1097 system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
1098 system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
1099 system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
1100 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1101 system.cpu0.icache.tags.tag_accesses 149404895 # Number of tag accesses
1102 system.cpu0.icache.tags.data_accesses 149404895 # Number of data accesses
1103 system.cpu0.icache.ReadReq_hits::cpu0.inst 72677991 # number of ReadReq hits
1104 system.cpu0.icache.ReadReq_hits::total 72677991 # number of ReadReq hits
1105 system.cpu0.icache.demand_hits::cpu0.inst 72677991 # number of demand (read+write) hits
1106 system.cpu0.icache.demand_hits::total 72677991 # number of demand (read+write) hits
1107 system.cpu0.icache.overall_hits::cpu0.inst 72677991 # number of overall hits
1108 system.cpu0.icache.overall_hits::total 72677991 # number of overall hits
1109 system.cpu0.icache.ReadReq_misses::cpu0.inst 1368448 # number of ReadReq misses
1110 system.cpu0.icache.ReadReq_misses::total 1368448 # number of ReadReq misses
1111 system.cpu0.icache.demand_misses::cpu0.inst 1368448 # number of demand (read+write) misses
1112 system.cpu0.icache.demand_misses::total 1368448 # number of demand (read+write) misses
1113 system.cpu0.icache.overall_misses::cpu0.inst 1368448 # number of overall misses
1114 system.cpu0.icache.overall_misses::total 1368448 # number of overall misses
1115 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14924586060 # number of ReadReq miss cycles
1116 system.cpu0.icache.ReadReq_miss_latency::total 14924586060 # number of ReadReq miss cycles
1117 system.cpu0.icache.demand_miss_latency::cpu0.inst 14924586060 # number of demand (read+write) miss cycles
1118 system.cpu0.icache.demand_miss_latency::total 14924586060 # number of demand (read+write) miss cycles
1119 system.cpu0.icache.overall_miss_latency::cpu0.inst 14924586060 # number of overall miss cycles
1120 system.cpu0.icache.overall_miss_latency::total 14924586060 # number of overall miss cycles
1121 system.cpu0.icache.ReadReq_accesses::cpu0.inst 74046439 # number of ReadReq accesses(hits+misses)
1122 system.cpu0.icache.ReadReq_accesses::total 74046439 # number of ReadReq accesses(hits+misses)
1123 system.cpu0.icache.demand_accesses::cpu0.inst 74046439 # number of demand (read+write) accesses
1124 system.cpu0.icache.demand_accesses::total 74046439 # number of demand (read+write) accesses
1125 system.cpu0.icache.overall_accesses::cpu0.inst 74046439 # number of overall (read+write) accesses
1126 system.cpu0.icache.overall_accesses::total 74046439 # number of overall (read+write) accesses
1127 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018481 # miss rate for ReadReq accesses
1128 system.cpu0.icache.ReadReq_miss_rate::total 0.018481 # miss rate for ReadReq accesses
1129 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018481 # miss rate for demand accesses
1130 system.cpu0.icache.demand_miss_rate::total 0.018481 # miss rate for demand accesses
1131 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018481 # miss rate for overall accesses
1132 system.cpu0.icache.overall_miss_rate::total 0.018481 # miss rate for overall accesses
1133 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506 # average ReadReq miss latency
1134 system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506 # average ReadReq miss latency
1135 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
1136 system.cpu0.icache.demand_avg_miss_latency::total 10906.213506 # average overall miss latency
1137 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
1138 system.cpu0.icache.overall_avg_miss_latency::total 10906.213506 # average overall miss latency
1139 system.cpu0.icache.blocked_cycles::no_mshrs 1977903 # number of cycles access was blocked
1140 system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked
1141 system.cpu0.icache.blocked::no_mshrs 120515 # number of cycles access was blocked
1142 system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked
1143 system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.412090 # average number of cycles each access was blocked
1144 system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked
1145 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1146 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1147 system.cpu0.icache.writebacks::writebacks 1311471 # number of writebacks
1148 system.cpu0.icache.writebacks::total 1311471 # number of writebacks
1149 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56430 # number of ReadReq MSHR hits
1150 system.cpu0.icache.ReadReq_mshr_hits::total 56430 # number of ReadReq MSHR hits
1151 system.cpu0.icache.demand_mshr_hits::cpu0.inst 56430 # number of demand (read+write) MSHR hits
1152 system.cpu0.icache.demand_mshr_hits::total 56430 # number of demand (read+write) MSHR hits
1153 system.cpu0.icache.overall_mshr_hits::cpu0.inst 56430 # number of overall MSHR hits
1154 system.cpu0.icache.overall_mshr_hits::total 56430 # number of overall MSHR hits
1155 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312018 # number of ReadReq MSHR misses
1156 system.cpu0.icache.ReadReq_mshr_misses::total 1312018 # number of ReadReq MSHR misses
1157 system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312018 # number of demand (read+write) MSHR misses
1158 system.cpu0.icache.demand_mshr_misses::total 1312018 # number of demand (read+write) MSHR misses
1159 system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312018 # number of overall MSHR misses
1160 system.cpu0.icache.overall_mshr_misses::total 1312018 # number of overall MSHR misses
1161 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1162 system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
1163 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1164 system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
1165 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13396366068 # number of ReadReq MSHR miss cycles
1166 system.cpu0.icache.ReadReq_mshr_miss_latency::total 13396366068 # number of ReadReq MSHR miss cycles
1167 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13396366068 # number of demand (read+write) MSHR miss cycles
1168 system.cpu0.icache.demand_mshr_miss_latency::total 13396366068 # number of demand (read+write) MSHR miss cycles
1169 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13396366068 # number of overall MSHR miss cycles
1170 system.cpu0.icache.overall_mshr_miss_latency::total 13396366068 # number of overall MSHR miss cycles
1171 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles
1172 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles
1173 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles
1174 system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles
1175 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for ReadReq accesses
1176 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017719 # mshr miss rate for ReadReq accesses
1177 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for demand accesses
1178 system.cpu0.icache.demand_mshr_miss_rate::total 0.017719 # mshr miss rate for demand accesses
1179 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for overall accesses
1180 system.cpu0.icache.overall_mshr_miss_rate::total 0.017719 # mshr miss rate for overall accesses
1181 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average ReadReq mshr miss latency
1182 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10210.504786 # average ReadReq mshr miss latency
1183 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
1184 system.cpu0.icache.demand_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
1185 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
1186 system.cpu0.icache.overall_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
1187 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency
1188 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency
1189 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency
1190 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency
1191 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1192 system.cpu0.l2cache.prefetcher.num_hwpf_issued 1932548 # number of hwpf issued
1193 system.cpu0.l2cache.prefetcher.pfIdentified 1935408 # number of prefetch candidates identified
1194 system.cpu0.l2cache.prefetcher.pfBufferHit 2604 # number of redundant prefetches already in prefetch queue
1195 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1196 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1197 system.cpu0.l2cache.prefetcher.pfSpanPage 246016 # number of prefetches not generated due to page crossing
1198 system.cpu0.l2cache.tags.replacements 282767 # number of replacements
1199 system.cpu0.l2cache.tags.tagsinuse 16108.615116 # Cycle average of tags in use
1200 system.cpu0.l2cache.tags.total_refs 3429175 # Total number of references to valid blocks.
1201 system.cpu0.l2cache.tags.sampled_refs 298912 # Sample count of references to valid blocks.
1202 system.cpu0.l2cache.tags.avg_refs 11.472189 # Average number of references to valid blocks.
1203 system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1204 system.cpu0.l2cache.tags.occ_blocks::writebacks 14681.579143 # Average occupied blocks per requestor
1205 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.440463 # Average occupied blocks per requestor
1206 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.496999 # Average occupied blocks per requestor
1207 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1415.098510 # Average occupied blocks per requestor
1208 system.cpu0.l2cache.tags.occ_percent::writebacks 0.896092 # Average percentage of cache occupancy
1209 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000698 # Average percentage of cache occupancy
1210 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy
1211 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086371 # Average percentage of cache occupancy
1212 system.cpu0.l2cache.tags.occ_percent::total 0.983192 # Average percentage of cache occupancy
1213 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id
1214 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
1215 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15155 # Occupied blocks per task id
1216 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
1217 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 298 # Occupied blocks per task id
1218 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
1219 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
1220 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
1221 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
1222 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
1223 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
1224 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id
1225 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4586 # Occupied blocks per task id
1226 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7902 # Occupied blocks per task id
1227 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2036 # Occupied blocks per task id
1228 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id
1229 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
1230 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924988 # Percentage of cache occupancy per task id
1231 system.cpu0.l2cache.tags.tag_accesses 69610425 # Number of tag accesses
1232 system.cpu0.l2cache.tags.data_accesses 69610425 # Number of data accesses
1233 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60495 # number of ReadReq hits
1234 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13905 # number of ReadReq hits
1235 system.cpu0.l2cache.ReadReq_hits::total 74400 # number of ReadReq hits
1236 system.cpu0.l2cache.WritebackDirty_hits::writebacks 507703 # number of WritebackDirty hits
1237 system.cpu0.l2cache.WritebackDirty_hits::total 507703 # number of WritebackDirty hits
1238 system.cpu0.l2cache.WritebackClean_hits::writebacks 1523854 # number of WritebackClean hits
1239 system.cpu0.l2cache.WritebackClean_hits::total 1523854 # number of WritebackClean hits
1240 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 206993 # number of ReadExReq hits
1241 system.cpu0.l2cache.ReadExReq_hits::total 206993 # number of ReadExReq hits
1242 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258247 # number of ReadCleanReq hits
1243 system.cpu0.l2cache.ReadCleanReq_hits::total 1258247 # number of ReadCleanReq hits
1244 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 428473 # number of ReadSharedReq hits
1245 system.cpu0.l2cache.ReadSharedReq_hits::total 428473 # number of ReadSharedReq hits
1246 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60495 # number of demand (read+write) hits
1247 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13905 # number of demand (read+write) hits
1248 system.cpu0.l2cache.demand_hits::cpu0.inst 1258247 # number of demand (read+write) hits
1249 system.cpu0.l2cache.demand_hits::cpu0.data 635466 # number of demand (read+write) hits
1250 system.cpu0.l2cache.demand_hits::total 1968113 # number of demand (read+write) hits
1251 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60495 # number of overall hits
1252 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13905 # number of overall hits
1253 system.cpu0.l2cache.overall_hits::cpu0.inst 1258247 # number of overall hits
1254 system.cpu0.l2cache.overall_hits::cpu0.data 635466 # number of overall hits
1255 system.cpu0.l2cache.overall_hits::total 1968113 # number of overall hits
1256 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 354 # number of ReadReq misses
1257 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 125 # number of ReadReq misses
1258 system.cpu0.l2cache.ReadReq_misses::total 479 # number of ReadReq misses
1259 system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
1260 system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
1261 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55429 # number of UpgradeReq misses
1262 system.cpu0.l2cache.UpgradeReq_misses::total 55429 # number of UpgradeReq misses
1263 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20273 # number of SCUpgradeReq misses
1264 system.cpu0.l2cache.SCUpgradeReq_misses::total 20273 # number of SCUpgradeReq misses
1265 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74521 # number of ReadExReq misses
1266 system.cpu0.l2cache.ReadExReq_misses::total 74521 # number of ReadExReq misses
1267 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 53742 # number of ReadCleanReq misses
1268 system.cpu0.l2cache.ReadCleanReq_misses::total 53742 # number of ReadCleanReq misses
1269 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97171 # number of ReadSharedReq misses
1270 system.cpu0.l2cache.ReadSharedReq_misses::total 97171 # number of ReadSharedReq misses
1271 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 354 # number of demand (read+write) misses
1272 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 125 # number of demand (read+write) misses
1273 system.cpu0.l2cache.demand_misses::cpu0.inst 53742 # number of demand (read+write) misses
1274 system.cpu0.l2cache.demand_misses::cpu0.data 171692 # number of demand (read+write) misses
1275 system.cpu0.l2cache.demand_misses::total 225913 # number of demand (read+write) misses
1276 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 354 # number of overall misses
1277 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 125 # number of overall misses
1278 system.cpu0.l2cache.overall_misses::cpu0.inst 53742 # number of overall misses
1279 system.cpu0.l2cache.overall_misses::cpu0.data 171692 # number of overall misses
1280 system.cpu0.l2cache.overall_misses::total 225913 # number of overall misses
1281 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11980000 # number of ReadReq miss cycles
1282 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3266000 # number of ReadReq miss cycles
1283 system.cpu0.l2cache.ReadReq_miss_latency::total 15246000 # number of ReadReq miss cycles
1284 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 178815000 # number of UpgradeReq miss cycles
1285 system.cpu0.l2cache.UpgradeReq_miss_latency::total 178815000 # number of UpgradeReq miss cycles
1286 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41943500 # number of SCUpgradeReq miss cycles
1287 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41943500 # number of SCUpgradeReq miss cycles
1288 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 166500 # number of SCUpgradeFailReq miss cycles
1289 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 166500 # number of SCUpgradeFailReq miss cycles
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1292 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3752300498 # number of ReadCleanReq miss cycles
1293 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3752300498 # number of ReadCleanReq miss cycles
1294 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3420930498 # number of ReadSharedReq miss cycles
1295 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3420930498 # number of ReadSharedReq miss cycles
1296 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11980000 # number of demand (read+write) miss cycles
1297 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3266000 # number of demand (read+write) miss cycles
1298 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3752300498 # number of demand (read+write) miss cycles
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1301 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11980000 # number of overall miss cycles
1302 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3266000 # number of overall miss cycles
1303 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3752300498 # number of overall miss cycles
1304 system.cpu0.l2cache.overall_miss_latency::cpu0.data 7518411495 # number of overall miss cycles
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1306 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60849 # number of ReadReq accesses(hits+misses)
1307 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14030 # number of ReadReq accesses(hits+misses)
1308 system.cpu0.l2cache.ReadReq_accesses::total 74879 # number of ReadReq accesses(hits+misses)
1309 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507704 # number of WritebackDirty accesses(hits+misses)
1310 system.cpu0.l2cache.WritebackDirty_accesses::total 507704 # number of WritebackDirty accesses(hits+misses)
1311 system.cpu0.l2cache.WritebackClean_accesses::writebacks 1523854 # number of WritebackClean accesses(hits+misses)
1312 system.cpu0.l2cache.WritebackClean_accesses::total 1523854 # number of WritebackClean accesses(hits+misses)
1313 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55429 # number of UpgradeReq accesses(hits+misses)
1314 system.cpu0.l2cache.UpgradeReq_accesses::total 55429 # number of UpgradeReq accesses(hits+misses)
1315 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20273 # number of SCUpgradeReq accesses(hits+misses)
1316 system.cpu0.l2cache.SCUpgradeReq_accesses::total 20273 # number of SCUpgradeReq accesses(hits+misses)
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1318 system.cpu0.l2cache.ReadExReq_accesses::total 281514 # number of ReadExReq accesses(hits+misses)
1319 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1311989 # number of ReadCleanReq accesses(hits+misses)
1320 system.cpu0.l2cache.ReadCleanReq_accesses::total 1311989 # number of ReadCleanReq accesses(hits+misses)
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1322 system.cpu0.l2cache.ReadSharedReq_accesses::total 525644 # number of ReadSharedReq accesses(hits+misses)
1323 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60849 # number of demand (read+write) accesses
1324 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14030 # number of demand (read+write) accesses
1325 system.cpu0.l2cache.demand_accesses::cpu0.inst 1311989 # number of demand (read+write) accesses
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1328 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60849 # number of overall (read+write) accesses
1329 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14030 # number of overall (read+write) accesses
1330 system.cpu0.l2cache.overall_accesses::cpu0.inst 1311989 # number of overall (read+write) accesses
1331 system.cpu0.l2cache.overall_accesses::cpu0.data 807158 # number of overall (read+write) accesses
1332 system.cpu0.l2cache.overall_accesses::total 2194026 # number of overall (read+write) accesses
1333 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for ReadReq accesses
1334 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.008909 # miss rate for ReadReq accesses
1335 system.cpu0.l2cache.ReadReq_miss_rate::total 0.006397 # miss rate for ReadReq accesses
1336 system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
1337 system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
1338 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1339 system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1340 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1341 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1342 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.264715 # miss rate for ReadExReq accesses
1343 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.264715 # miss rate for ReadExReq accesses
1344 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040962 # miss rate for ReadCleanReq accesses
1345 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040962 # miss rate for ReadCleanReq accesses
1346 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184861 # miss rate for ReadSharedReq accesses
1347 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184861 # miss rate for ReadSharedReq accesses
1348 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for demand accesses
1349 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.008909 # miss rate for demand accesses
1350 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040962 # miss rate for demand accesses
1351 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.212712 # miss rate for demand accesses
1352 system.cpu0.l2cache.demand_miss_rate::total 0.102967 # miss rate for demand accesses
1353 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for overall accesses
1354 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.008909 # miss rate for overall accesses
1355 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040962 # miss rate for overall accesses
1356 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.212712 # miss rate for overall accesses
1357 system.cpu0.l2cache.overall_miss_rate::total 0.102967 # miss rate for overall accesses
1358 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average ReadReq miss latency
1359 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26128 # average ReadReq miss latency
1360 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31828.810021 # average ReadReq miss latency
1361 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3226.018871 # average UpgradeReq miss latency
1362 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3226.018871 # average UpgradeReq miss latency
1363 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2068.934050 # average SCUpgradeReq miss latency
1364 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2068.934050 # average SCUpgradeReq miss latency
1365 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1366 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1367 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54984.246011 # average ReadExReq miss latency
1368 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54984.246011 # average ReadExReq miss latency
1369 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69820.633732 # average ReadCleanReq miss latency
1370 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69820.633732 # average ReadCleanReq miss latency
1371 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35205.261837 # average ReadSharedReq miss latency
1372 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35205.261837 # average ReadSharedReq miss latency
1373 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
1374 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
1375 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
1376 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
1377 system.cpu0.l2cache.demand_avg_miss_latency::total 49957.098498 # average overall miss latency
1378 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
1379 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
1380 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
1381 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
1382 system.cpu0.l2cache.overall_avg_miss_latency::total 49957.098498 # average overall miss latency
1383 system.cpu0.l2cache.blocked_cycles::no_mshrs 204 # number of cycles access was blocked
1384 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1385 system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
1386 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1387 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1388 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1389 system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1390 system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1391 system.cpu0.l2cache.unused_prefetches 10407 # number of HardPF blocks evicted w/o reference
1392 system.cpu0.l2cache.writebacks::writebacks 233202 # number of writebacks
1393 system.cpu0.l2cache.writebacks::total 233202 # number of writebacks
1394 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
1395 system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1396 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32963 # number of ReadExReq MSHR hits
1397 system.cpu0.l2cache.ReadExReq_mshr_hits::total 32963 # number of ReadExReq MSHR hits
1398 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits
1399 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits
1400 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 774 # number of ReadSharedReq MSHR hits
1401 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 774 # number of ReadSharedReq MSHR hits
1402 system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
1403 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits
1404 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33737 # number of demand (read+write) MSHR hits
1405 system.cpu0.l2cache.demand_mshr_hits::total 33780 # number of demand (read+write) MSHR hits
1406 system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
1407 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits
1408 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33737 # number of overall MSHR hits
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1410 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 353 # number of ReadReq MSHR misses
1411 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 125 # number of ReadReq MSHR misses
1412 system.cpu0.l2cache.ReadReq_mshr_misses::total 478 # number of ReadReq MSHR misses
1413 system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
1414 system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
1415 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262414 # number of HardPFReq MSHR misses
1416 system.cpu0.l2cache.HardPFReq_mshr_misses::total 262414 # number of HardPFReq MSHR misses
1417 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55429 # number of UpgradeReq MSHR misses
1418 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55429 # number of UpgradeReq MSHR misses
1419 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20273 # number of SCUpgradeReq MSHR misses
1420 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20273 # number of SCUpgradeReq MSHR misses
1421 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41558 # number of ReadExReq MSHR misses
1422 system.cpu0.l2cache.ReadExReq_mshr_misses::total 41558 # number of ReadExReq MSHR misses
1423 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 53700 # number of ReadCleanReq MSHR misses
1424 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 53700 # number of ReadCleanReq MSHR misses
1425 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96397 # number of ReadSharedReq MSHR misses
1426 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96397 # number of ReadSharedReq MSHR misses
1427 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 353 # number of demand (read+write) MSHR misses
1428 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 125 # number of demand (read+write) MSHR misses
1429 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53700 # number of demand (read+write) MSHR misses
1430 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137955 # number of demand (read+write) MSHR misses
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1432 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 353 # number of overall MSHR misses
1433 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 125 # number of overall MSHR misses
1434 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53700 # number of overall MSHR misses
1435 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137955 # number of overall MSHR misses
1436 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262414 # number of overall MSHR misses
1437 system.cpu0.l2cache.overall_mshr_misses::total 454547 # number of overall MSHR misses
1438 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1439 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
1440 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34819 # number of ReadReq MSHR uncacheable
1441 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
1442 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1443 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1444 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
1445 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63318 # number of overall MSHR uncacheable misses
1446 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of ReadReq MSHR miss cycles
1447 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2516000 # number of ReadReq MSHR miss cycles
1448 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12357000 # number of ReadReq MSHR miss cycles
1449 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of HardPFReq MSHR miss cycles
1450 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 22141788258 # number of HardPFReq MSHR miss cycles
1451 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1433561500 # number of UpgradeReq MSHR miss cycles
1452 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1433561500 # number of UpgradeReq MSHR miss cycles
1453 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 351805000 # number of SCUpgradeReq MSHR miss cycles
1454 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 351805000 # number of SCUpgradeReq MSHR miss cycles
1455 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 136500 # number of SCUpgradeFailReq MSHR miss cycles
1456 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 136500 # number of SCUpgradeFailReq MSHR miss cycles
1457 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2493972500 # number of ReadExReq MSHR miss cycles
1458 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2493972500 # number of ReadExReq MSHR miss cycles
1459 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3428273498 # number of ReadCleanReq MSHR miss cycles
1460 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3428273498 # number of ReadCleanReq MSHR miss cycles
1461 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2782772498 # number of ReadSharedReq MSHR miss cycles
1462 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2782772498 # number of ReadSharedReq MSHR miss cycles
1463 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of demand (read+write) MSHR miss cycles
1464 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2516000 # number of demand (read+write) MSHR miss cycles
1465 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3428273498 # number of demand (read+write) MSHR miss cycles
1466 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5276744998 # number of demand (read+write) MSHR miss cycles
1467 system.cpu0.l2cache.demand_mshr_miss_latency::total 8717375496 # number of demand (read+write) MSHR miss cycles
1468 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of overall MSHR miss cycles
1469 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2516000 # number of overall MSHR miss cycles
1470 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3428273498 # number of overall MSHR miss cycles
1471 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5276744998 # number of overall MSHR miss cycles
1472 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of overall MSHR miss cycles
1473 system.cpu0.l2cache.overall_mshr_miss_latency::total 30859163754 # number of overall MSHR miss cycles
1474 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398052500 # number of ReadReq MSHR uncacheable cycles
1475 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369072500 # number of ReadReq MSHR uncacheable cycles
1476 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6767125000 # number of ReadReq MSHR uncacheable cycles
1477 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178546465 # number of WriteReq MSHR uncacheable cycles
1478 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178546465 # number of WriteReq MSHR uncacheable cycles
1479 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398052500 # number of overall MSHR uncacheable cycles
1480 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547618965 # number of overall MSHR uncacheable cycles
1481 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945671465 # number of overall MSHR uncacheable cycles
1482 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for ReadReq accesses
1483 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for ReadReq accesses
1484 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006384 # mshr miss rate for ReadReq accesses
1485 system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
1486 system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
1487 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1488 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1489 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1490 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1491 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1492 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1493 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147623 # mshr miss rate for ReadExReq accesses
1494 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147623 # mshr miss rate for ReadExReq accesses
1495 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for ReadCleanReq accesses
1496 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040930 # mshr miss rate for ReadCleanReq accesses
1497 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.183388 # mshr miss rate for ReadSharedReq accesses
1498 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.183388 # mshr miss rate for ReadSharedReq accesses
1499 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for demand accesses
1500 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for demand accesses
1501 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for demand accesses
1502 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for demand accesses
1503 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.087571 # mshr miss rate for demand accesses
1504 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for overall accesses
1505 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for overall accesses
1506 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for overall accesses
1507 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for overall accesses
1508 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1509 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207175 # mshr miss rate for overall accesses
1510 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average ReadReq mshr miss latency
1511 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average ReadReq mshr miss latency
1512 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435 # average ReadReq mshr miss latency
1513 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average HardPFReq mshr miss latency
1514 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169 # average HardPFReq mshr miss latency
1515 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966 # average UpgradeReq mshr miss latency
1516 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966 # average UpgradeReq mshr miss latency
1517 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412 # average SCUpgradeReq mshr miss latency
1518 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412 # average SCUpgradeReq mshr miss latency
1519 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1520 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1521 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907 # average ReadExReq mshr miss latency
1522 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907 # average ReadExReq mshr miss latency
1523 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average ReadCleanReq mshr miss latency
1524 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702 # average ReadCleanReq mshr miss latency
1525 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003 # average ReadSharedReq mshr miss latency
1526 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003 # average ReadSharedReq mshr miss latency
1527 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
1528 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
1529 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
1530 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
1531 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112 # average overall mshr miss latency
1532 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
1533 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
1534 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
1535 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
1536 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average overall mshr miss latency
1537 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433 # average overall mshr miss latency
1538 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency
1539 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942 # average ReadReq mshr uncacheable latency
1540 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489 # average ReadReq mshr uncacheable latency
1541 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518 # average WriteReq mshr uncacheable latency
1542 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518 # average WriteReq mshr uncacheable latency
1543 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency
1544 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407 # average overall mshr uncacheable latency
1545 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189 # average overall mshr uncacheable latency
1546 system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1547 system.cpu0.toL2Bus.snoop_filter.tot_requests 4281853 # Total number of requests made to the snoop filter.
1548 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162712 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1549 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32662 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1550 system.cpu0.toL2Bus.snoop_filter.tot_snoops 328300 # Total number of snoops made to the snoop filter.
1551 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1552 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3848 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1553 system.cpu0.toL2Bus.trans_dist::ReadReq 121117 # Transaction distribution
1554 system.cpu0.toL2Bus.trans_dist::ReadResp 2006967 # Transaction distribution
1555 system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
1556 system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
1557 system.cpu0.toL2Bus.trans_dist::WritebackDirty 741466 # Transaction distribution
1558 system.cpu0.toL2Bus.trans_dist::WritebackClean 1556492 # Transaction distribution
1559 system.cpu0.toL2Bus.trans_dist::CleanEvict 207602 # Transaction distribution
1560 system.cpu0.toL2Bus.trans_dist::HardPFReq 320187 # Transaction distribution
1561 system.cpu0.toL2Bus.trans_dist::UpgradeReq 85477 # Transaction distribution
1562 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42629 # Transaction distribution
1563 system.cpu0.toL2Bus.trans_dist::UpgradeResp 113152 # Transaction distribution
1564 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
1565 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
1566 system.cpu0.toL2Bus.trans_dist::ReadExReq 299842 # Transaction distribution
1567 system.cpu0.toL2Bus.trans_dist::ReadExResp 296502 # Transaction distribution
1568 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312018 # Transaction distribution
1569 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 596340 # Transaction distribution
1570 system.cpu0.toL2Bus.trans_dist::InvalidateReq 3402 # Transaction distribution
1571 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3941483 # Packet count per connected master and slave (bytes)
1572 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739757 # Packet count per connected master and slave (bytes)
1573 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30823 # Packet count per connected master and slave (bytes)
1574 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130322 # Packet count per connected master and slave (bytes)
1575 system.cpu0.toL2Bus.pkt_count::total 6842385 # Packet count per connected master and slave (bytes)
1576 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167949424 # Cumulative packet size per connected master and slave (bytes)
1577 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104071122 # Cumulative packet size per connected master and slave (bytes)
1578 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56120 # Cumulative packet size per connected master and slave (bytes)
1579 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243396 # Cumulative packet size per connected master and slave (bytes)
1580 system.cpu0.toL2Bus.pkt_size::total 272320062 # Cumulative packet size per connected master and slave (bytes)
1581 system.cpu0.toL2Bus.snoops 1018529 # Total snoops (count)
1582 system.cpu0.toL2Bus.snoop_fanout::samples 3250936 # Request fanout histogram
1583 system.cpu0.toL2Bus.snoop_fanout::mean 0.119239 # Request fanout histogram
1584 system.cpu0.toL2Bus.snoop_fanout::stdev 0.327701 # Request fanout histogram
1585 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1586 system.cpu0.toL2Bus.snoop_fanout::0 2867147 88.19% 88.19% # Request fanout histogram
1587 system.cpu0.toL2Bus.snoop_fanout::1 379941 11.69% 99.88% # Request fanout histogram
1588 system.cpu0.toL2Bus.snoop_fanout::2 3848 0.12% 100.00% # Request fanout histogram
1589 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1590 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1591 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1592 system.cpu0.toL2Bus.snoop_fanout::total 3250936 # Request fanout histogram
1593 system.cpu0.toL2Bus.reqLayer0.occupancy 4282821452 # Layer occupancy (ticks)
1594 system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1595 system.cpu0.toL2Bus.snoopLayer0.occupancy 113625688 # Layer occupancy (ticks)
1596 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1597 system.cpu0.toL2Bus.respLayer0.occupancy 1971630792 # Layer occupancy (ticks)
1598 system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1599 system.cpu0.toL2Bus.respLayer1.occupancy 1296047217 # Layer occupancy (ticks)
1600 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1601 system.cpu0.toL2Bus.respLayer2.occupancy 16802481 # Layer occupancy (ticks)
1602 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1603 system.cpu0.toL2Bus.respLayer3.occupancy 69515913 # Layer occupancy (ticks)
1604 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1605 system.cpu1.branchPred.lookups 3871087 # Number of BP lookups
1606 system.cpu1.branchPred.condPredicted 2220502 # Number of conditional branches predicted
1607 system.cpu1.branchPred.condIncorrect 213805 # Number of conditional branches incorrect
1608 system.cpu1.branchPred.BTBLookups 1955914 # Number of BTB lookups
1609 system.cpu1.branchPred.BTBHits 1266404 # Number of BTB hits
1610 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1611 system.cpu1.branchPred.BTBHitPct 64.747428 # BTB Hit Percentage
1612 system.cpu1.branchPred.usedRAS 774472 # Number of times the RAS was used to get a target.
1613 system.cpu1.branchPred.RASInCorrect 5638 # Number of incorrect RAS predictions.
1614 system.cpu1.branchPred.indirectLookups 216728 # Number of indirect predictor lookups.
1615 system.cpu1.branchPred.indirectHits 192718 # Number of indirect target hits.
1616 system.cpu1.branchPred.indirectMisses 24010 # Number of indirect misses.
1617 system.cpu1.branchPredindirectMispredicted 5536 # Number of mispredicted indirect branches.
1618 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1619 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1620 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1621 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1622 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1623 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1624 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1625 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1626 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1627 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1628 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1629 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1630 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1631 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1632 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1633 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1634 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1635 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1636 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1637 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1638 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1639 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1640 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1641 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1642 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1643 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1644 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1645 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1646 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1647 system.cpu1.dtb.walker.walks 15135 # Table walker walks requested
1648 system.cpu1.dtb.walker.walksShort 15135 # Table walker walks initiated with short descriptors
1649 system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8000 # Level at which table walker walks with short descriptors terminate
1650 system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3062 # Level at which table walker walks with short descriptors terminate
1651 system.cpu1.dtb.walker.walksSquashedBefore 4073 # Table walks squashed before starting
1652 system.cpu1.dtb.walker.walkWaitTime::samples 11062 # Table walker wait (enqueue to first request) latency
1653 system.cpu1.dtb.walker.walkWaitTime::mean 636.232146 # Table walker wait (enqueue to first request) latency
1654 system.cpu1.dtb.walker.walkWaitTime::stdev 3393.246458 # Table walker wait (enqueue to first request) latency
1655 system.cpu1.dtb.walker.walkWaitTime::0-4095 10520 95.10% 95.10% # Table walker wait (enqueue to first request) latency
1656 system.cpu1.dtb.walker.walkWaitTime::4096-8191 182 1.65% 96.75% # Table walker wait (enqueue to first request) latency
1657 system.cpu1.dtb.walker.walkWaitTime::8192-12287 208 1.88% 98.63% # Table walker wait (enqueue to first request) latency
1658 system.cpu1.dtb.walker.walkWaitTime::12288-16383 44 0.40% 99.02% # Table walker wait (enqueue to first request) latency
1659 system.cpu1.dtb.walker.walkWaitTime::16384-20479 10 0.09% 99.11% # Table walker wait (enqueue to first request) latency
1660 system.cpu1.dtb.walker.walkWaitTime::20480-24575 20 0.18% 99.29% # Table walker wait (enqueue to first request) latency
1661 system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.04% 99.33% # Table walker wait (enqueue to first request) latency
1662 system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.57% 99.90% # Table walker wait (enqueue to first request) latency
1663 system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.05% 99.95% # Table walker wait (enqueue to first request) latency
1664 system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
1665 system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
1666 system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
1667 system.cpu1.dtb.walker.walkWaitTime::total 11062 # Table walker wait (enqueue to first request) latency
1668 system.cpu1.dtb.walker.walkCompletionTime::samples 3287 # Table walker service (enqueue to completion) latency
1669 system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726 # Table walker service (enqueue to completion) latency
1670 system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277 # Table walker service (enqueue to completion) latency
1671 system.cpu1.dtb.walker.walkCompletionTime::stdev 7252.269841 # Table walker service (enqueue to completion) latency
1672 system.cpu1.dtb.walker.walkCompletionTime::0-16383 2804 85.31% 85.31% # Table walker service (enqueue to completion) latency
1673 system.cpu1.dtb.walker.walkCompletionTime::16384-32767 438 13.33% 98.63% # Table walker service (enqueue to completion) latency
1674 system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.06% 99.70% # Table walker service (enqueue to completion) latency
1675 system.cpu1.dtb.walker.walkCompletionTime::49152-65535 8 0.24% 99.94% # Table walker service (enqueue to completion) latency
1676 system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
1677 system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
1678 system.cpu1.dtb.walker.walkCompletionTime::total 3287 # Table walker service (enqueue to completion) latency
1679 system.cpu1.dtb.walker.walksPending::samples 78326908560 # Table walker pending requests distribution
1680 system.cpu1.dtb.walker.walksPending::mean 0.188289 # Table walker pending requests distribution
1681 system.cpu1.dtb.walker.walksPending::stdev 0.393350 # Table walker pending requests distribution
1682 system.cpu1.dtb.walker.walksPending::0 63608298256 81.21% 81.21% # Table walker pending requests distribution
1683 system.cpu1.dtb.walker.walksPending::1 14703547304 18.77% 99.98% # Table walker pending requests distribution
1684 system.cpu1.dtb.walker.walksPending::2 10074500 0.01% 99.99% # Table walker pending requests distribution
1685 system.cpu1.dtb.walker.walksPending::3 1868000 0.00% 100.00% # Table walker pending requests distribution
1686 system.cpu1.dtb.walker.walksPending::4 997000 0.00% 100.00% # Table walker pending requests distribution
1687 system.cpu1.dtb.walker.walksPending::5 536500 0.00% 100.00% # Table walker pending requests distribution
1688 system.cpu1.dtb.walker.walksPending::6 1004000 0.00% 100.00% # Table walker pending requests distribution
1689 system.cpu1.dtb.walker.walksPending::7 156000 0.00% 100.00% # Table walker pending requests distribution
1690 system.cpu1.dtb.walker.walksPending::8 32000 0.00% 100.00% # Table walker pending requests distribution
1691 system.cpu1.dtb.walker.walksPending::9 91000 0.00% 100.00% # Table walker pending requests distribution
1692 system.cpu1.dtb.walker.walksPending::10 15500 0.00% 100.00% # Table walker pending requests distribution
1693 system.cpu1.dtb.walker.walksPending::11 43500 0.00% 100.00% # Table walker pending requests distribution
1694 system.cpu1.dtb.walker.walksPending::12 105500 0.00% 100.00% # Table walker pending requests distribution
1695 system.cpu1.dtb.walker.walksPending::13 9000 0.00% 100.00% # Table walker pending requests distribution
1696 system.cpu1.dtb.walker.walksPending::14 4500 0.00% 100.00% # Table walker pending requests distribution
1697 system.cpu1.dtb.walker.walksPending::15 126000 0.00% 100.00% # Table walker pending requests distribution
1698 system.cpu1.dtb.walker.walksPending::total 78326908560 # Table walker pending requests distribution
1699 system.cpu1.dtb.walker.walkPageSizes::4K 1232 71.42% 71.42% # Table walker page sizes translated
1700 system.cpu1.dtb.walker.walkPageSizes::1M 493 28.58% 100.00% # Table walker page sizes translated
1701 system.cpu1.dtb.walker.walkPageSizes::total 1725 # Table walker page sizes translated
1702 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15135 # Table walker requests started/completed, data/inst
1703 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1704 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15135 # Table walker requests started/completed, data/inst
1705 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1725 # Table walker requests started/completed, data/inst
1706 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1707 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1725 # Table walker requests started/completed, data/inst
1708 system.cpu1.dtb.walker.walkRequestOrigin::total 16860 # Table walker requests started/completed, data/inst
1709 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1710 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1711 system.cpu1.dtb.read_hits 3481626 # DTB read hits
1712 system.cpu1.dtb.read_misses 13250 # DTB read misses
1713 system.cpu1.dtb.write_hits 2942267 # DTB write hits
1714 system.cpu1.dtb.write_misses 1885 # DTB write misses
1715 system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1716 system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1717 system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1718 system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1719 system.cpu1.dtb.flush_entries 1665 # Number of entries that have been flushed from TLB
1720 system.cpu1.dtb.align_faults 44 # Number of TLB faults due to alignment restrictions
1721 system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
1722 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1723 system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
1724 system.cpu1.dtb.read_accesses 3494876 # DTB read accesses
1725 system.cpu1.dtb.write_accesses 2944152 # DTB write accesses
1726 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1727 system.cpu1.dtb.hits 6423893 # DTB hits
1728 system.cpu1.dtb.misses 15135 # DTB misses
1729 system.cpu1.dtb.accesses 6439028 # DTB accesses
1730 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1731 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1732 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1733 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1734 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1735 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1736 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1737 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1738 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1739 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1740 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1741 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1742 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1743 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1744 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1745 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1746 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1747 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1748 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1749 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1750 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1751 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1752 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1753 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1754 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1755 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1756 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1757 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1758 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1759 system.cpu1.itb.walker.walks 5379 # Table walker walks requested
1760 system.cpu1.itb.walker.walksShort 5379 # Table walker walks initiated with short descriptors
1761 system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2691 # Level at which table walker walks with short descriptors terminate
1762 system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2153 # Level at which table walker walks with short descriptors terminate
1763 system.cpu1.itb.walker.walksSquashedBefore 535 # Table walks squashed before starting
1764 system.cpu1.itb.walker.walkWaitTime::samples 4844 # Table walker wait (enqueue to first request) latency
1765 system.cpu1.itb.walker.walkWaitTime::mean 218.414533 # Table walker wait (enqueue to first request) latency
1766 system.cpu1.itb.walker.walkWaitTime::stdev 1692.156629 # Table walker wait (enqueue to first request) latency
1767 system.cpu1.itb.walker.walkWaitTime::0-2047 4709 97.21% 97.21% # Table walker wait (enqueue to first request) latency
1768 system.cpu1.itb.walker.walkWaitTime::2048-4095 42 0.87% 98.08% # Table walker wait (enqueue to first request) latency
1769 system.cpu1.itb.walker.walkWaitTime::4096-6143 42 0.87% 98.95% # Table walker wait (enqueue to first request) latency
1770 system.cpu1.itb.walker.walkWaitTime::6144-8191 13 0.27% 99.22% # Table walker wait (enqueue to first request) latency
1771 system.cpu1.itb.walker.walkWaitTime::8192-10239 10 0.21% 99.42% # Table walker wait (enqueue to first request) latency
1772 system.cpu1.itb.walker.walkWaitTime::10240-12287 7 0.14% 99.57% # Table walker wait (enqueue to first request) latency
1773 system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.08% 99.65% # Table walker wait (enqueue to first request) latency
1774 system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.10% 99.75% # Table walker wait (enqueue to first request) latency
1775 system.cpu1.itb.walker.walkWaitTime::16384-18431 2 0.04% 99.79% # Table walker wait (enqueue to first request) latency
1776 system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.83% # Table walker wait (enqueue to first request) latency
1777 system.cpu1.itb.walker.walkWaitTime::26624-28671 6 0.12% 99.96% # Table walker wait (enqueue to first request) latency
1778 system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency
1779 system.cpu1.itb.walker.walkWaitTime::total 4844 # Table walker wait (enqueue to first request) latency
1780 system.cpu1.itb.walker.walkCompletionTime::samples 1373 # Table walker service (enqueue to completion) latency
1781 system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752 # Table walker service (enqueue to completion) latency
1782 system.cpu1.itb.walker.walkCompletionTime::gmean 9997.704100 # Table walker service (enqueue to completion) latency
1783 system.cpu1.itb.walker.walkCompletionTime::stdev 5248.867098 # Table walker service (enqueue to completion) latency
1784 system.cpu1.itb.walker.walkCompletionTime::0-8191 278 20.25% 20.25% # Table walker service (enqueue to completion) latency
1785 system.cpu1.itb.walker.walkCompletionTime::8192-16383 1006 73.27% 93.52% # Table walker service (enqueue to completion) latency
1786 system.cpu1.itb.walker.walkCompletionTime::16384-24575 56 4.08% 97.60% # Table walker service (enqueue to completion) latency
1787 system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 1.17% 98.76% # Table walker service (enqueue to completion) latency
1788 system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.66% 99.42% # Table walker service (enqueue to completion) latency
1789 system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.36% 99.78% # Table walker service (enqueue to completion) latency
1790 system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.93% # Table walker service (enqueue to completion) latency
1791 system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
1792 system.cpu1.itb.walker.walkCompletionTime::total 1373 # Table walker service (enqueue to completion) latency
1793 system.cpu1.itb.walker.walksPending::samples 18192386416 # Table walker pending requests distribution
1794 system.cpu1.itb.walker.walksPending::mean 0.925541 # Table walker pending requests distribution
1795 system.cpu1.itb.walker.walksPending::stdev 0.262684 # Table walker pending requests distribution
1796 system.cpu1.itb.walker.walksPending::0 1355392264 7.45% 7.45% # Table walker pending requests distribution
1797 system.cpu1.itb.walker.walksPending::1 16836194152 92.55% 100.00% # Table walker pending requests distribution
1798 system.cpu1.itb.walker.walksPending::2 800000 0.00% 100.00% # Table walker pending requests distribution
1799 system.cpu1.itb.walker.walksPending::total 18192386416 # Table walker pending requests distribution
1800 system.cpu1.itb.walker.walkPageSizes::4K 695 82.94% 82.94% # Table walker page sizes translated
1801 system.cpu1.itb.walker.walkPageSizes::1M 143 17.06% 100.00% # Table walker page sizes translated
1802 system.cpu1.itb.walker.walkPageSizes::total 838 # Table walker page sizes translated
1803 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1804 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5379 # Table walker requests started/completed, data/inst
1805 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5379 # Table walker requests started/completed, data/inst
1806 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1807 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 838 # Table walker requests started/completed, data/inst
1808 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 838 # Table walker requests started/completed, data/inst
1809 system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst
1810 system.cpu1.itb.inst_hits 6965528 # ITB inst hits
1811 system.cpu1.itb.inst_misses 5379 # ITB inst misses
1812 system.cpu1.itb.read_hits 0 # DTB read hits
1813 system.cpu1.itb.read_misses 0 # DTB read misses
1814 system.cpu1.itb.write_hits 0 # DTB write hits
1815 system.cpu1.itb.write_misses 0 # DTB write misses
1816 system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1817 system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1818 system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1819 system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1820 system.cpu1.itb.flush_entries 902 # Number of entries that have been flushed from TLB
1821 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1822 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1823 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1824 system.cpu1.itb.perms_faults 384 # Number of TLB faults due to permissions restrictions
1825 system.cpu1.itb.read_accesses 0 # DTB read accesses
1826 system.cpu1.itb.write_accesses 0 # DTB write accesses
1827 system.cpu1.itb.inst_accesses 6970907 # ITB inst accesses
1828 system.cpu1.itb.hits 6965528 # DTB hits
1829 system.cpu1.itb.misses 5379 # DTB misses
1830 system.cpu1.itb.accesses 6970907 # DTB accesses
1831 system.cpu1.numCycles 32092744 # number of cpu cycles simulated
1832 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1833 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1834 system.cpu1.fetch.icacheStallCycles 7782299 # Number of cycles fetch is stalled on an Icache miss
1835 system.cpu1.fetch.Insts 20640770 # Number of instructions fetch has processed
1836 system.cpu1.fetch.Branches 3871087 # Number of branches that fetch encountered
1837 system.cpu1.fetch.predictedBranches 2233594 # Number of branches that fetch has predicted taken
1838 system.cpu1.fetch.Cycles 22614955 # Number of cycles fetch has run and was not squashing or blocked
1839 system.cpu1.fetch.SquashCycles 645830 # Number of cycles fetch has spent squashing
1840 system.cpu1.fetch.TlbCycles 74008 # Number of cycles fetch has spent waiting for tlb
1841 system.cpu1.fetch.MiscStallCycles 29636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1842 system.cpu1.fetch.PendingTrapStallCycles 160010 # Number of stall cycles due to pending traps
1843 system.cpu1.fetch.PendingQuiesceStallCycles 275842 # Number of stall cycles due to pending quiesce instructions
1844 system.cpu1.fetch.IcacheWaitRetryStallCycles 16624 # Number of stall cycles due to full MSHR
1845 system.cpu1.fetch.CacheLines 6964682 # Number of cache lines fetched
1846 system.cpu1.fetch.IcacheSquashes 92359 # Number of outstanding Icache misses that were squashed
1847 system.cpu1.fetch.ItlbSquashes 1934 # Number of outstanding ITLB misses that were squashed
1848 system.cpu1.fetch.rateDist::samples 31276289 # Number of instructions fetched each cycle (Total)
1849 system.cpu1.fetch.rateDist::mean 0.805380 # Number of instructions fetched each cycle (Total)
1850 system.cpu1.fetch.rateDist::stdev 1.188121 # Number of instructions fetched each cycle (Total)
1851 system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1852 system.cpu1.fetch.rateDist::0 19613481 62.71% 62.71% # Number of instructions fetched each cycle (Total)
1853 system.cpu1.fetch.rateDist::1 4233968 13.54% 76.25% # Number of instructions fetched each cycle (Total)
1854 system.cpu1.fetch.rateDist::2 1331194 4.26% 80.50% # Number of instructions fetched each cycle (Total)
1855 system.cpu1.fetch.rateDist::3 6097646 19.50% 100.00% # Number of instructions fetched each cycle (Total)
1856 system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1857 system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1858 system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1859 system.cpu1.fetch.rateDist::total 31276289 # Number of instructions fetched each cycle (Total)
1860 system.cpu1.fetch.branchRate 0.120622 # Number of branch fetches per cycle
1861 system.cpu1.fetch.rate 0.643160 # Number of inst fetches per cycle
1862 system.cpu1.decode.IdleCycles 6336736 # Number of cycles decode is idle
1863 system.cpu1.decode.BlockedCycles 16565133 # Number of cycles decode is blocked
1864 system.cpu1.decode.RunCycles 7246187 # Number of cycles decode is running
1865 system.cpu1.decode.UnblockCycles 914830 # Number of cycles decode is unblocking
1866 system.cpu1.decode.SquashCycles 213403 # Number of cycles decode is squashing
1867 system.cpu1.decode.BranchResolved 597831 # Number of times decode resolved a branch
1868 system.cpu1.decode.BranchMispred 111765 # Number of times decode detected a branch misprediction
1869 system.cpu1.decode.DecodedInsts 19357447 # Number of instructions handled by decode
1870 system.cpu1.decode.SquashedInsts 835377 # Number of squashed instructions handled by decode
1871 system.cpu1.rename.SquashCycles 213403 # Number of cycles rename is squashing
1872 system.cpu1.rename.IdleCycles 7521212 # Number of cycles rename is idle
1873 system.cpu1.rename.BlockCycles 2374588 # Number of cycles rename is blocking
1874 system.cpu1.rename.serializeStallCycles 11566982 # count of cycles rename stalled for serializing inst
1875 system.cpu1.rename.RunCycles 6962571 # Number of cycles rename is running
1876 system.cpu1.rename.UnblockCycles 2637533 # Number of cycles rename is unblocking
1877 system.cpu1.rename.RenamedInsts 18397316 # Number of instructions processed by rename
1878 system.cpu1.rename.SquashedInsts 130089 # Number of squashed instructions processed by rename
1879 system.cpu1.rename.ROBFullEvents 214163 # Number of times rename has blocked due to ROB full
1880 system.cpu1.rename.IQFullEvents 27812 # Number of times rename has blocked due to IQ full
1881 system.cpu1.rename.LQFullEvents 12950 # Number of times rename has blocked due to LQ full
1882 system.cpu1.rename.SQFullEvents 1772414 # Number of times rename has blocked due to SQ full
1883 system.cpu1.rename.RenamedOperands 18194678 # Number of destination operands rename has renamed
1884 system.cpu1.rename.RenameLookups 86130501 # Number of register rename lookups that rename has made
1885 system.cpu1.rename.int_rename_lookups 21182613 # Number of integer rename lookups
1886 system.cpu1.rename.fp_rename_lookups 5 # Number of floating rename lookups
1887 system.cpu1.rename.CommittedMaps 16531195 # Number of HB maps that are committed
1888 system.cpu1.rename.UndoneMaps 1663483 # Number of HB maps that are undone due to squashing
1889 system.cpu1.rename.serializingInsts 369349 # count of serializing insts renamed
1890 system.cpu1.rename.tempSerializingInsts 301926 # count of temporary serializing insts renamed
1891 system.cpu1.rename.skidInsts 2462039 # count of insts added to the skid buffer
1892 system.cpu1.memDep0.insertedLoads 3681622 # Number of loads inserted to the mem dependence unit.
1893 system.cpu1.memDep0.insertedStores 3198899 # Number of stores inserted to the mem dependence unit.
1894 system.cpu1.memDep0.conflictingLoads 554263 # Number of conflicting loads.
1895 system.cpu1.memDep0.conflictingStores 453752 # Number of conflicting stores.
1896 system.cpu1.iq.iqInstsAdded 17730825 # Number of instructions added to the IQ (excludes non-spec)
1897 system.cpu1.iq.iqNonSpecInstsAdded 507077 # Number of non-speculative instructions added to the IQ
1898 system.cpu1.iq.iqInstsIssued 17704327 # Number of instructions issued
1899 system.cpu1.iq.iqSquashedInstsIssued 59995 # Number of squashed instructions issued
1900 system.cpu1.iq.iqSquashedInstsExamined 1478553 # Number of squashed instructions iterated over during squash; mainly for profiling
1901 system.cpu1.iq.iqSquashedOperandsExamined 3387139 # Number of squashed operands that are examined and possibly removed from graph
1902 system.cpu1.iq.iqSquashedNonSpecRemoved 37397 # Number of squashed non-spec instructions that were removed
1903 system.cpu1.iq.issued_per_cycle::samples 31276289 # Number of insts issued each cycle
1904 system.cpu1.iq.issued_per_cycle::mean 0.566062 # Number of insts issued each cycle
1905 system.cpu1.iq.issued_per_cycle::stdev 0.918538 # Number of insts issued each cycle
1906 system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1907 system.cpu1.iq.issued_per_cycle::0 20752127 66.35% 66.35% # Number of insts issued each cycle
1908 system.cpu1.iq.issued_per_cycle::1 5297030 16.94% 83.29% # Number of insts issued each cycle
1909 system.cpu1.iq.issued_per_cycle::2 3493708 11.17% 94.46% # Number of insts issued each cycle
1910 system.cpu1.iq.issued_per_cycle::3 1513821 4.84% 99.30% # Number of insts issued each cycle
1911 system.cpu1.iq.issued_per_cycle::4 219597 0.70% 100.00% # Number of insts issued each cycle
1912 system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle
1913 system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1914 system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1915 system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1916 system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1917 system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1918 system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1919 system.cpu1.iq.issued_per_cycle::total 31276289 # Number of insts issued each cycle
1920 system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1921 system.cpu1.iq.fu_full::IntAlu 1110256 27.87% 27.87% # attempts to use FU when none available
1922 system.cpu1.iq.fu_full::IntMult 673 0.02% 27.89% # attempts to use FU when none available
1923 system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.89% # attempts to use FU when none available
1924 system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.89% # attempts to use FU when none available
1925 system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.89% # attempts to use FU when none available
1926 system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.89% # attempts to use FU when none available
1927 system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.89% # attempts to use FU when none available
1928 system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.89% # attempts to use FU when none available
1929 system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
1930 system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.89% # attempts to use FU when none available
1931 system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.89% # attempts to use FU when none available
1932 system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.89% # attempts to use FU when none available
1933 system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.89% # attempts to use FU when none available
1934 system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.89% # attempts to use FU when none available
1935 system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.89% # attempts to use FU when none available
1936 system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.89% # attempts to use FU when none available
1937 system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.89% # attempts to use FU when none available
1938 system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.89% # attempts to use FU when none available
1939 system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.89% # attempts to use FU when none available
1940 system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.89% # attempts to use FU when none available
1941 system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.89% # attempts to use FU when none available
1942 system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.89% # attempts to use FU when none available
1943 system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.89% # attempts to use FU when none available
1944 system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.89% # attempts to use FU when none available
1945 system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.89% # attempts to use FU when none available
1946 system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.89% # attempts to use FU when none available
1947 system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.89% # attempts to use FU when none available
1948 system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.89% # attempts to use FU when none available
1949 system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
1950 system.cpu1.iq.fu_full::MemRead 1321373 33.17% 61.07% # attempts to use FU when none available
1951 system.cpu1.iq.fu_full::MemWrite 1550767 38.93% 100.00% # attempts to use FU when none available
1952 system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1953 system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1954 system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
1955 system.cpu1.iq.FU_type_0::IntAlu 10922763 61.70% 61.70% # Type of FU issued
1956 system.cpu1.iq.FU_type_0::IntMult 25931 0.15% 61.84% # Type of FU issued
1957 system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued
1958 system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued
1959 system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued
1960 system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued
1961 system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued
1962 system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued
1963 system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued
1964 system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued
1965 system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued
1966 system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued
1967 system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued
1968 system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued
1969 system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued
1970 system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued
1971 system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued
1972 system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued
1973 system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued
1974 system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued
1975 system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued
1976 system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued
1977 system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued
1978 system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued
1979 system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued
1980 system.cpu1.iq.FU_type_0::SimdFloatMisc 3184 0.02% 61.86% # Type of FU issued
1981 system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
1982 system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
1983 system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
1984 system.cpu1.iq.FU_type_0::MemRead 3652522 20.63% 82.49% # Type of FU issued
1985 system.cpu1.iq.FU_type_0::MemWrite 3099903 17.51% 100.00% # Type of FU issued
1986 system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1987 system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1988 system.cpu1.iq.FU_type_0::total 17704327 # Type of FU issued
1989 system.cpu1.iq.rate 0.551661 # Inst issue rate
1990 system.cpu1.iq.fu_busy_cnt 3983069 # FU busy when requested
1991 system.cpu1.iq.fu_busy_rate 0.224977 # FU busy rate (busy events/executed inst)
1992 system.cpu1.iq.int_inst_queue_reads 70728007 # Number of integer instruction queue reads
1993 system.cpu1.iq.int_inst_queue_writes 19724904 # Number of integer instruction queue writes
1994 system.cpu1.iq.int_inst_queue_wakeup_accesses 17354196 # Number of integer instruction queue wakeup accesses
1995 system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1996 system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
1997 system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1998 system.cpu1.iq.int_alu_accesses 21687372 # Number of integer alu accesses
1999 system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2000 system.cpu1.iew.lsq.thread0.forwLoads 71019 # Number of loads that had data forwarded from stores
2001 system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2002 system.cpu1.iew.lsq.thread0.squashedLoads 284912 # Number of loads squashed
2003 system.cpu1.iew.lsq.thread0.ignoredResponses 435 # Number of memory responses ignored because the instruction is squashed
2004 system.cpu1.iew.lsq.thread0.memOrderViolation 8471 # Number of memory ordering violations
2005 system.cpu1.iew.lsq.thread0.squashedStores 200526 # Number of stores squashed
2006 system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2007 system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2008 system.cpu1.iew.lsq.thread0.rescheduledLoads 36020 # Number of loads that were rescheduled
2009 system.cpu1.iew.lsq.thread0.cacheBlocked 53245 # Number of times an access to memory failed due to the cache being blocked
2010 system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2011 system.cpu1.iew.iewSquashCycles 213403 # Number of cycles IEW is squashing
2012 system.cpu1.iew.iewBlockCycles 522979 # Number of cycles IEW is blocking
2013 system.cpu1.iew.iewUnblockCycles 149253 # Number of cycles IEW is unblocking
2014 system.cpu1.iew.iewDispatchedInsts 18243784 # Number of instructions dispatched to IQ
2015 system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016 system.cpu1.iew.iewDispLoadInsts 3681622 # Number of dispatched load instructions
2017 system.cpu1.iew.iewDispStoreInsts 3198899 # Number of dispatched store instructions
2018 system.cpu1.iew.iewDispNonSpecInsts 268198 # Number of dispatched non-speculative instructions
2019 system.cpu1.iew.iewIQFullEvents 4775 # Number of times the IQ has become full, causing a stall
2020 system.cpu1.iew.iewLSQFullEvents 139704 # Number of times the LSQ has become full, causing a stall
2021 system.cpu1.iew.memOrderViolationEvents 8471 # Number of memory order violations
2022 system.cpu1.iew.predictedTakenIncorrect 19696 # Number of branches that were predicted taken incorrectly
2023 system.cpu1.iew.predictedNotTakenIncorrect 91512 # Number of branches that were predicted not taken incorrectly
2024 system.cpu1.iew.branchMispredicts 111208 # Number of branch mispredicts detected at execute
2025 system.cpu1.iew.iewExecutedInsts 17534609 # Number of executed instructions
2026 system.cpu1.iew.iewExecLoadInsts 3585774 # Number of load instructions executed
2027 system.cpu1.iew.iewExecSquashedInsts 154586 # Number of squashed instructions skipped in execute
2028 system.cpu1.iew.exec_swp 0 # number of swp insts executed
2029 system.cpu1.iew.exec_nop 5882 # number of nop insts executed
2030 system.cpu1.iew.exec_refs 6645326 # number of memory reference insts executed
2031 system.cpu1.iew.exec_branches 2522938 # Number of branches executed
2032 system.cpu1.iew.exec_stores 3059552 # Number of stores executed
2033 system.cpu1.iew.exec_rate 0.546373 # Inst execution rate
2034 system.cpu1.iew.wb_sent 17440127 # cumulative count of insts sent to commit
2035 system.cpu1.iew.wb_count 17354196 # cumulative count of insts written-back
2036 system.cpu1.iew.wb_producers 8664228 # num instructions producing a value
2037 system.cpu1.iew.wb_consumers 13427268 # num instructions consuming a value
2038 system.cpu1.iew.wb_rate 0.540751 # insts written-back per cycle
2039 system.cpu1.iew.wb_fanout 0.645271 # average fanout of values written-back
2040 system.cpu1.commit.commitSquashedInsts 1321053 # The number of squashed insts skipped by commit
2041 system.cpu1.commit.commitNonSpecStalls 469680 # The number of times commit has been forced to stall to communicate backwards
2042 system.cpu1.commit.branchMispredicts 104293 # The number of times a branch was mispredicted
2043 system.cpu1.commit.committed_per_cycle::samples 30960244 # Number of insts commited each cycle
2044 system.cpu1.commit.committed_per_cycle::mean 0.541417 # Number of insts commited each cycle
2045 system.cpu1.commit.committed_per_cycle::stdev 1.301399 # Number of insts commited each cycle
2046 system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2047 system.cpu1.commit.committed_per_cycle::0 22892252 73.94% 73.94% # Number of insts commited each cycle
2048 system.cpu1.commit.committed_per_cycle::1 4806577 15.52% 89.47% # Number of insts commited each cycle
2049 system.cpu1.commit.committed_per_cycle::2 1404802 4.54% 94.00% # Number of insts commited each cycle
2050 system.cpu1.commit.committed_per_cycle::3 524965 1.70% 95.70% # Number of insts commited each cycle
2051 system.cpu1.commit.committed_per_cycle::4 440442 1.42% 97.12% # Number of insts commited each cycle
2052 system.cpu1.commit.committed_per_cycle::5 285091 0.92% 98.04% # Number of insts commited each cycle
2053 system.cpu1.commit.committed_per_cycle::6 183452 0.59% 98.63% # Number of insts commited each cycle
2054 system.cpu1.commit.committed_per_cycle::7 97903 0.32% 98.95% # Number of insts commited each cycle
2055 system.cpu1.commit.committed_per_cycle::8 324760 1.05% 100.00% # Number of insts commited each cycle
2056 system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2057 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2058 system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2059 system.cpu1.commit.committed_per_cycle::total 30960244 # Number of insts commited each cycle
2060 system.cpu1.commit.committedInsts 13688085 # Number of instructions committed
2061 system.cpu1.commit.committedOps 16762412 # Number of ops (including micro ops) committed
2062 system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2063 system.cpu1.commit.refs 6395083 # Number of memory references committed
2064 system.cpu1.commit.loads 3396710 # Number of loads committed
2065 system.cpu1.commit.membars 189727 # Number of memory barriers committed
2066 system.cpu1.commit.branches 2413565 # Number of branches committed
2067 system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
2068 system.cpu1.commit.int_insts 14968527 # Number of committed integer instructions.
2069 system.cpu1.commit.function_calls 408976 # Number of function calls committed.
2070 system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2071 system.cpu1.commit.op_class_0::IntAlu 10339164 61.68% 61.68% # Class of committed instruction
2072 system.cpu1.commit.op_class_0::IntMult 24981 0.15% 61.83% # Class of committed instruction
2073 system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.83% # Class of committed instruction
2074 system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.83% # Class of committed instruction
2075 system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.83% # Class of committed instruction
2076 system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.83% # Class of committed instruction
2077 system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.83% # Class of committed instruction
2078 system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.83% # Class of committed instruction
2079 system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.83% # Class of committed instruction
2080 system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.83% # Class of committed instruction
2081 system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.83% # Class of committed instruction
2082 system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.83% # Class of committed instruction
2083 system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.83% # Class of committed instruction
2084 system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.83% # Class of committed instruction
2085 system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.83% # Class of committed instruction
2086 system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.83% # Class of committed instruction
2087 system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.83% # Class of committed instruction
2088 system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.83% # Class of committed instruction
2089 system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.83% # Class of committed instruction
2090 system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.83% # Class of committed instruction
2091 system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.83% # Class of committed instruction
2092 system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.83% # Class of committed instruction
2093 system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.83% # Class of committed instruction
2094 system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.83% # Class of committed instruction
2095 system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.83% # Class of committed instruction
2096 system.cpu1.commit.op_class_0::SimdFloatMisc 3184 0.02% 61.85% # Class of committed instruction
2097 system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.85% # Class of committed instruction
2098 system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.85% # Class of committed instruction
2099 system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.85% # Class of committed instruction
2100 system.cpu1.commit.op_class_0::MemRead 3396710 20.26% 82.11% # Class of committed instruction
2101 system.cpu1.commit.op_class_0::MemWrite 2998373 17.89% 100.00% # Class of committed instruction
2102 system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2103 system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2104 system.cpu1.commit.op_class_0::total 16762412 # Class of committed instruction
2105 system.cpu1.commit.bw_lim_events 324760 # number cycles where commit BW limit reached
2106 system.cpu1.rob.rob_reads 47828529 # The number of ROB reads
2107 system.cpu1.rob.rob_writes 36474807 # The number of ROB writes
2108 system.cpu1.timesIdled 47199 # Number of times that the entire CPU went into an idle state and unscheduled itself
2109 system.cpu1.idleCycles 816455 # Total number of cycles that the CPU has spent unscheduled due to idling
2110 system.cpu1.quiesceCycles 5622120065 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2111 system.cpu1.committedInsts 13685021 # Number of Instructions Simulated
2112 system.cpu1.committedOps 16759348 # Number of Ops (including micro ops) Simulated
2113 system.cpu1.cpi 2.345100 # CPI: Cycles Per Instruction
2114 system.cpu1.cpi_total 2.345100 # CPI: Total CPI of All Threads
2115 system.cpu1.ipc 0.426421 # IPC: Instructions Per Cycle
2116 system.cpu1.ipc_total 0.426421 # IPC: Total IPC of All Threads
2117 system.cpu1.int_regfile_reads 19625898 # number of integer regfile reads
2118 system.cpu1.int_regfile_writes 11372751 # number of integer regfile writes
2119 system.cpu1.cc_regfile_reads 63035720 # number of cc regfile reads
2120 system.cpu1.cc_regfile_writes 5356524 # number of cc regfile writes
2121 system.cpu1.misc_regfile_reads 45569068 # number of misc regfile reads
2122 system.cpu1.misc_regfile_writes 348886 # number of misc regfile writes
2123 system.cpu1.dcache.tags.replacements 147018 # number of replacements
2124 system.cpu1.dcache.tags.tagsinuse 469.878055 # Cycle average of tags in use
2125 system.cpu1.dcache.tags.total_refs 5728782 # Total number of references to valid blocks.
2126 system.cpu1.dcache.tags.sampled_refs 147355 # Sample count of references to valid blocks.
2127 system.cpu1.dcache.tags.avg_refs 38.877418 # Average number of references to valid blocks.
2128 system.cpu1.dcache.tags.warmup_cycle 104643213000 # Cycle when the warmup percentage was hit.
2129 system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.878055 # Average occupied blocks per requestor
2130 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917731 # Average percentage of cache occupancy
2131 system.cpu1.dcache.tags.occ_percent::total 0.917731 # Average percentage of cache occupancy
2132 system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
2133 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id
2134 system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2135 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id
2136 system.cpu1.dcache.tags.tag_accesses 12638529 # Number of tag accesses
2137 system.cpu1.dcache.tags.data_accesses 12638529 # Number of data accesses
2138 system.cpu1.dcache.ReadReq_hits::cpu1.data 3017876 # number of ReadReq hits
2139 system.cpu1.dcache.ReadReq_hits::total 3017876 # number of ReadReq hits
2140 system.cpu1.dcache.WriteReq_hits::cpu1.data 2482754 # number of WriteReq hits
2141 system.cpu1.dcache.WriteReq_hits::total 2482754 # number of WriteReq hits
2142 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41945 # number of SoftPFReq hits
2143 system.cpu1.dcache.SoftPFReq_hits::total 41945 # number of SoftPFReq hits
2144 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69025 # number of LoadLockedReq hits
2145 system.cpu1.dcache.LoadLockedReq_hits::total 69025 # number of LoadLockedReq hits
2146 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61066 # number of StoreCondReq hits
2147 system.cpu1.dcache.StoreCondReq_hits::total 61066 # number of StoreCondReq hits
2148 system.cpu1.dcache.demand_hits::cpu1.data 5500630 # number of demand (read+write) hits
2149 system.cpu1.dcache.demand_hits::total 5500630 # number of demand (read+write) hits
2150 system.cpu1.dcache.overall_hits::cpu1.data 5542575 # number of overall hits
2151 system.cpu1.dcache.overall_hits::total 5542575 # number of overall hits
2152 system.cpu1.dcache.ReadReq_misses::cpu1.data 174243 # number of ReadReq misses
2153 system.cpu1.dcache.ReadReq_misses::total 174243 # number of ReadReq misses
2154 system.cpu1.dcache.WriteReq_misses::cpu1.data 312530 # number of WriteReq misses
2155 system.cpu1.dcache.WriteReq_misses::total 312530 # number of WriteReq misses
2156 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23398 # number of SoftPFReq misses
2157 system.cpu1.dcache.SoftPFReq_misses::total 23398 # number of SoftPFReq misses
2158 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17766 # number of LoadLockedReq misses
2159 system.cpu1.dcache.LoadLockedReq_misses::total 17766 # number of LoadLockedReq misses
2160 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23154 # number of StoreCondReq misses
2161 system.cpu1.dcache.StoreCondReq_misses::total 23154 # number of StoreCondReq misses
2162 system.cpu1.dcache.demand_misses::cpu1.data 486773 # number of demand (read+write) misses
2163 system.cpu1.dcache.demand_misses::total 486773 # number of demand (read+write) misses
2164 system.cpu1.dcache.overall_misses::cpu1.data 510171 # number of overall misses
2165 system.cpu1.dcache.overall_misses::total 510171 # number of overall misses
2166 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3329111500 # number of ReadReq miss cycles
2167 system.cpu1.dcache.ReadReq_miss_latency::total 3329111500 # number of ReadReq miss cycles
2168 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11702941948 # number of WriteReq miss cycles
2169 system.cpu1.dcache.WriteReq_miss_latency::total 11702941948 # number of WriteReq miss cycles
2170 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 365873000 # number of LoadLockedReq miss cycles
2171 system.cpu1.dcache.LoadLockedReq_miss_latency::total 365873000 # number of LoadLockedReq miss cycles
2172 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 624012000 # number of StoreCondReq miss cycles
2173 system.cpu1.dcache.StoreCondReq_miss_latency::total 624012000 # number of StoreCondReq miss cycles
2174 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1848000 # number of StoreCondFailReq miss cycles
2175 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1848000 # number of StoreCondFailReq miss cycles
2176 system.cpu1.dcache.demand_miss_latency::cpu1.data 15032053448 # number of demand (read+write) miss cycles
2177 system.cpu1.dcache.demand_miss_latency::total 15032053448 # number of demand (read+write) miss cycles
2178 system.cpu1.dcache.overall_miss_latency::cpu1.data 15032053448 # number of overall miss cycles
2179 system.cpu1.dcache.overall_miss_latency::total 15032053448 # number of overall miss cycles
2180 system.cpu1.dcache.ReadReq_accesses::cpu1.data 3192119 # number of ReadReq accesses(hits+misses)
2181 system.cpu1.dcache.ReadReq_accesses::total 3192119 # number of ReadReq accesses(hits+misses)
2182 system.cpu1.dcache.WriteReq_accesses::cpu1.data 2795284 # number of WriteReq accesses(hits+misses)
2183 system.cpu1.dcache.WriteReq_accesses::total 2795284 # number of WriteReq accesses(hits+misses)
2184 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65343 # number of SoftPFReq accesses(hits+misses)
2185 system.cpu1.dcache.SoftPFReq_accesses::total 65343 # number of SoftPFReq accesses(hits+misses)
2186 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86791 # number of LoadLockedReq accesses(hits+misses)
2187 system.cpu1.dcache.LoadLockedReq_accesses::total 86791 # number of LoadLockedReq accesses(hits+misses)
2188 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84220 # number of StoreCondReq accesses(hits+misses)
2189 system.cpu1.dcache.StoreCondReq_accesses::total 84220 # number of StoreCondReq accesses(hits+misses)
2190 system.cpu1.dcache.demand_accesses::cpu1.data 5987403 # number of demand (read+write) accesses
2191 system.cpu1.dcache.demand_accesses::total 5987403 # number of demand (read+write) accesses
2192 system.cpu1.dcache.overall_accesses::cpu1.data 6052746 # number of overall (read+write) accesses
2193 system.cpu1.dcache.overall_accesses::total 6052746 # number of overall (read+write) accesses
2194 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054585 # miss rate for ReadReq accesses
2195 system.cpu1.dcache.ReadReq_miss_rate::total 0.054585 # miss rate for ReadReq accesses
2196 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111806 # miss rate for WriteReq accesses
2197 system.cpu1.dcache.WriteReq_miss_rate::total 0.111806 # miss rate for WriteReq accesses
2198 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358080 # miss rate for SoftPFReq accesses
2199 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358080 # miss rate for SoftPFReq accesses
2200 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.204699 # miss rate for LoadLockedReq accesses
2201 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.204699 # miss rate for LoadLockedReq accesses
2202 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274923 # miss rate for StoreCondReq accesses
2203 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274923 # miss rate for StoreCondReq accesses
2204 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081300 # miss rate for demand accesses
2205 system.cpu1.dcache.demand_miss_rate::total 0.081300 # miss rate for demand accesses
2206 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084288 # miss rate for overall accesses
2207 system.cpu1.dcache.overall_miss_rate::total 0.084288 # miss rate for overall accesses
2208 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997 # average ReadReq miss latency
2209 system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997 # average ReadReq miss latency
2210 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435 # average WriteReq miss latency
2211 system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435 # average WriteReq miss latency
2212 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775 # average LoadLockedReq miss latency
2213 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775 # average LoadLockedReq miss latency
2214 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312 # average StoreCondReq miss latency
2215 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312 # average StoreCondReq miss latency
2216 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2217 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2218 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763 # average overall miss latency
2219 system.cpu1.dcache.demand_avg_miss_latency::total 30881.033763 # average overall miss latency
2220 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252 # average overall miss latency
2221 system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252 # average overall miss latency
2222 system.cpu1.dcache.blocked_cycles::no_mshrs 465 # number of cycles access was blocked
2223 system.cpu1.dcache.blocked_cycles::no_targets 1794947 # number of cycles access was blocked
2224 system.cpu1.dcache.blocked::no_mshrs 35 # number of cycles access was blocked
2225 system.cpu1.dcache.blocked::no_targets 29761 # number of cycles access was blocked
2226 system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.285714 # average number of cycles each access was blocked
2227 system.cpu1.dcache.avg_blocked_cycles::no_targets 60.312053 # average number of cycles each access was blocked
2228 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2229 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2230 system.cpu1.dcache.writebacks::writebacks 147018 # number of writebacks
2231 system.cpu1.dcache.writebacks::total 147018 # number of writebacks
2232 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 60609 # number of ReadReq MSHR hits
2233 system.cpu1.dcache.ReadReq_mshr_hits::total 60609 # number of ReadReq MSHR hits
2234 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 234531 # number of WriteReq MSHR hits
2235 system.cpu1.dcache.WriteReq_mshr_hits::total 234531 # number of WriteReq MSHR hits
2236 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12556 # number of LoadLockedReq MSHR hits
2237 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12556 # number of LoadLockedReq MSHR hits
2238 system.cpu1.dcache.demand_mshr_hits::cpu1.data 295140 # number of demand (read+write) MSHR hits
2239 system.cpu1.dcache.demand_mshr_hits::total 295140 # number of demand (read+write) MSHR hits
2240 system.cpu1.dcache.overall_mshr_hits::cpu1.data 295140 # number of overall MSHR hits
2241 system.cpu1.dcache.overall_mshr_hits::total 295140 # number of overall MSHR hits
2242 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113634 # number of ReadReq MSHR misses
2243 system.cpu1.dcache.ReadReq_mshr_misses::total 113634 # number of ReadReq MSHR misses
2244 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77999 # number of WriteReq MSHR misses
2245 system.cpu1.dcache.WriteReq_mshr_misses::total 77999 # number of WriteReq MSHR misses
2246 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22718 # number of SoftPFReq MSHR misses
2247 system.cpu1.dcache.SoftPFReq_mshr_misses::total 22718 # number of SoftPFReq MSHR misses
2248 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5210 # number of LoadLockedReq MSHR misses
2249 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5210 # number of LoadLockedReq MSHR misses
2250 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23154 # number of StoreCondReq MSHR misses
2251 system.cpu1.dcache.StoreCondReq_mshr_misses::total 23154 # number of StoreCondReq MSHR misses
2252 system.cpu1.dcache.demand_mshr_misses::cpu1.data 191633 # number of demand (read+write) MSHR misses
2253 system.cpu1.dcache.demand_mshr_misses::total 191633 # number of demand (read+write) MSHR misses
2254 system.cpu1.dcache.overall_mshr_misses::cpu1.data 214351 # number of overall MSHR misses
2255 system.cpu1.dcache.overall_mshr_misses::total 214351 # number of overall MSHR misses
2256 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
2257 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3075 # number of ReadReq MSHR uncacheable
2258 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
2259 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2419 # number of WriteReq MSHR uncacheable
2260 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5494 # number of overall MSHR uncacheable misses
2261 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5494 # number of overall MSHR uncacheable misses
2262 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1698407500 # number of ReadReq MSHR miss cycles
2263 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1698407500 # number of ReadReq MSHR miss cycles
2264 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2883249956 # number of WriteReq MSHR miss cycles
2265 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2883249956 # number of WriteReq MSHR miss cycles
2266 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 419765000 # number of SoftPFReq MSHR miss cycles
2267 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 419765000 # number of SoftPFReq MSHR miss cycles
2268 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 102736000 # number of LoadLockedReq MSHR miss cycles
2269 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 102736000 # number of LoadLockedReq MSHR miss cycles
2270 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 600876000 # number of StoreCondReq MSHR miss cycles
2271 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 600876000 # number of StoreCondReq MSHR miss cycles
2272 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles
2273 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles
2274 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4581657456 # number of demand (read+write) MSHR miss cycles
2275 system.cpu1.dcache.demand_mshr_miss_latency::total 4581657456 # number of demand (read+write) MSHR miss cycles
2276 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5001422456 # number of overall MSHR miss cycles
2277 system.cpu1.dcache.overall_mshr_miss_latency::total 5001422456 # number of overall MSHR miss cycles
2278 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 438427500 # number of ReadReq MSHR uncacheable cycles
2279 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 438427500 # number of ReadReq MSHR uncacheable cycles
2280 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301840000 # number of WriteReq MSHR uncacheable cycles
2281 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301840000 # number of WriteReq MSHR uncacheable cycles
2282 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 740267500 # number of overall MSHR uncacheable cycles
2283 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 740267500 # number of overall MSHR uncacheable cycles
2284 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035598 # mshr miss rate for ReadReq accesses
2285 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035598 # mshr miss rate for ReadReq accesses
2286 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027904 # mshr miss rate for WriteReq accesses
2287 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027904 # mshr miss rate for WriteReq accesses
2288 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.347673 # mshr miss rate for SoftPFReq accesses
2289 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.347673 # mshr miss rate for SoftPFReq accesses
2290 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060029 # mshr miss rate for LoadLockedReq accesses
2291 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060029 # mshr miss rate for LoadLockedReq accesses
2292 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274923 # mshr miss rate for StoreCondReq accesses
2293 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274923 # mshr miss rate for StoreCondReq accesses
2294 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for demand accesses
2295 system.cpu1.dcache.demand_mshr_miss_rate::total 0.032006 # mshr miss rate for demand accesses
2296 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035414 # mshr miss rate for overall accesses
2297 system.cpu1.dcache.overall_mshr_miss_rate::total 0.035414 # mshr miss rate for overall accesses
2298 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883 # average ReadReq mshr miss latency
2299 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883 # average ReadReq mshr miss latency
2300 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36965.216939 # average WriteReq mshr miss latency
2301 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36965.216939 # average WriteReq mshr miss latency
2302 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.198697 # average SoftPFReq mshr miss latency
2303 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18477.198697 # average SoftPFReq mshr miss latency
2304 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19719.001919 # average LoadLockedReq mshr miss latency
2305 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19719.001919 # average LoadLockedReq mshr miss latency
2306 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25951.282716 # average StoreCondReq mshr miss latency
2307 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25951.282716 # average StoreCondReq mshr miss latency
2308 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2309 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2310 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350 # average overall mshr miss latency
2311 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350 # average overall mshr miss latency
2312 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23332.862716 # average overall mshr miss latency
2313 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23332.862716 # average overall mshr miss latency
2314 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142578.048780 # average ReadReq mshr uncacheable latency
2315 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142578.048780 # average ReadReq mshr uncacheable latency
2316 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124778.834229 # average WriteReq mshr uncacheable latency
2317 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124778.834229 # average WriteReq mshr uncacheable latency
2318 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134741.081179 # average overall mshr uncacheable latency
2319 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134741.081179 # average overall mshr uncacheable latency
2320 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2321 system.cpu1.icache.tags.replacements 532644 # number of replacements
2322 system.cpu1.icache.tags.tagsinuse 499.385087 # Cycle average of tags in use
2323 system.cpu1.icache.tags.total_refs 6412298 # Total number of references to valid blocks.
2324 system.cpu1.icache.tags.sampled_refs 533156 # Sample count of references to valid blocks.
2325 system.cpu1.icache.tags.avg_refs 12.027058 # Average number of references to valid blocks.
2326 system.cpu1.icache.tags.warmup_cycle 79429210500 # Cycle when the warmup percentage was hit.
2327 system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.385087 # Average occupied blocks per requestor
2328 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975361 # Average percentage of cache occupancy
2329 system.cpu1.icache.tags.occ_percent::total 0.975361 # Average percentage of cache occupancy
2330 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2331 system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
2332 system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
2333 system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
2334 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2335 system.cpu1.icache.tags.tag_accesses 14462114 # Number of tag accesses
2336 system.cpu1.icache.tags.data_accesses 14462114 # Number of data accesses
2337 system.cpu1.icache.ReadReq_hits::cpu1.inst 6412298 # number of ReadReq hits
2338 system.cpu1.icache.ReadReq_hits::total 6412298 # number of ReadReq hits
2339 system.cpu1.icache.demand_hits::cpu1.inst 6412298 # number of demand (read+write) hits
2340 system.cpu1.icache.demand_hits::total 6412298 # number of demand (read+write) hits
2341 system.cpu1.icache.overall_hits::cpu1.inst 6412298 # number of overall hits
2342 system.cpu1.icache.overall_hits::total 6412298 # number of overall hits
2343 system.cpu1.icache.ReadReq_misses::cpu1.inst 552179 # number of ReadReq misses
2344 system.cpu1.icache.ReadReq_misses::total 552179 # number of ReadReq misses
2345 system.cpu1.icache.demand_misses::cpu1.inst 552179 # number of demand (read+write) misses
2346 system.cpu1.icache.demand_misses::total 552179 # number of demand (read+write) misses
2347 system.cpu1.icache.overall_misses::cpu1.inst 552179 # number of overall misses
2348 system.cpu1.icache.overall_misses::total 552179 # number of overall misses
2349 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5065871620 # number of ReadReq miss cycles
2350 system.cpu1.icache.ReadReq_miss_latency::total 5065871620 # number of ReadReq miss cycles
2351 system.cpu1.icache.demand_miss_latency::cpu1.inst 5065871620 # number of demand (read+write) miss cycles
2352 system.cpu1.icache.demand_miss_latency::total 5065871620 # number of demand (read+write) miss cycles
2353 system.cpu1.icache.overall_miss_latency::cpu1.inst 5065871620 # number of overall miss cycles
2354 system.cpu1.icache.overall_miss_latency::total 5065871620 # number of overall miss cycles
2355 system.cpu1.icache.ReadReq_accesses::cpu1.inst 6964477 # number of ReadReq accesses(hits+misses)
2356 system.cpu1.icache.ReadReq_accesses::total 6964477 # number of ReadReq accesses(hits+misses)
2357 system.cpu1.icache.demand_accesses::cpu1.inst 6964477 # number of demand (read+write) accesses
2358 system.cpu1.icache.demand_accesses::total 6964477 # number of demand (read+write) accesses
2359 system.cpu1.icache.overall_accesses::cpu1.inst 6964477 # number of overall (read+write) accesses
2360 system.cpu1.icache.overall_accesses::total 6964477 # number of overall (read+write) accesses
2361 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079285 # miss rate for ReadReq accesses
2362 system.cpu1.icache.ReadReq_miss_rate::total 0.079285 # miss rate for ReadReq accesses
2363 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079285 # miss rate for demand accesses
2364 system.cpu1.icache.demand_miss_rate::total 0.079285 # miss rate for demand accesses
2365 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079285 # miss rate for overall accesses
2366 system.cpu1.icache.overall_miss_rate::total 0.079285 # miss rate for overall accesses
2367 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9174.328651 # average ReadReq miss latency
2368 system.cpu1.icache.ReadReq_avg_miss_latency::total 9174.328651 # average ReadReq miss latency
2369 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
2370 system.cpu1.icache.demand_avg_miss_latency::total 9174.328651 # average overall miss latency
2371 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
2372 system.cpu1.icache.overall_avg_miss_latency::total 9174.328651 # average overall miss latency
2373 system.cpu1.icache.blocked_cycles::no_mshrs 470749 # number of cycles access was blocked
2374 system.cpu1.icache.blocked_cycles::no_targets 422 # number of cycles access was blocked
2375 system.cpu1.icache.blocked::no_mshrs 34696 # number of cycles access was blocked
2376 system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
2377 system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.567818 # average number of cycles each access was blocked
2378 system.cpu1.icache.avg_blocked_cycles::no_targets 105.500000 # average number of cycles each access was blocked
2379 system.cpu1.icache.fast_writes 0 # number of fast writes performed
2380 system.cpu1.icache.cache_copies 0 # number of cache copies performed
2381 system.cpu1.icache.writebacks::writebacks 532644 # number of writebacks
2382 system.cpu1.icache.writebacks::total 532644 # number of writebacks
2383 system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19019 # number of ReadReq MSHR hits
2384 system.cpu1.icache.ReadReq_mshr_hits::total 19019 # number of ReadReq MSHR hits
2385 system.cpu1.icache.demand_mshr_hits::cpu1.inst 19019 # number of demand (read+write) MSHR hits
2386 system.cpu1.icache.demand_mshr_hits::total 19019 # number of demand (read+write) MSHR hits
2387 system.cpu1.icache.overall_mshr_hits::cpu1.inst 19019 # number of overall MSHR hits
2388 system.cpu1.icache.overall_mshr_hits::total 19019 # number of overall MSHR hits
2389 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 533160 # number of ReadReq MSHR misses
2390 system.cpu1.icache.ReadReq_mshr_misses::total 533160 # number of ReadReq MSHR misses
2391 system.cpu1.icache.demand_mshr_misses::cpu1.inst 533160 # number of demand (read+write) MSHR misses
2392 system.cpu1.icache.demand_mshr_misses::total 533160 # number of demand (read+write) MSHR misses
2393 system.cpu1.icache.overall_mshr_misses::cpu1.inst 533160 # number of overall MSHR misses
2394 system.cpu1.icache.overall_mshr_misses::total 533160 # number of overall MSHR misses
2395 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2396 system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2397 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2398 system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
2399 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4631400380 # number of ReadReq MSHR miss cycles
2400 system.cpu1.icache.ReadReq_mshr_miss_latency::total 4631400380 # number of ReadReq MSHR miss cycles
2401 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4631400380 # number of demand (read+write) MSHR miss cycles
2402 system.cpu1.icache.demand_mshr_miss_latency::total 4631400380 # number of demand (read+write) MSHR miss cycles
2403 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4631400380 # number of overall MSHR miss cycles
2404 system.cpu1.icache.overall_mshr_miss_latency::total 4631400380 # number of overall MSHR miss cycles
2405 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13655000 # number of ReadReq MSHR uncacheable cycles
2406 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13655000 # number of ReadReq MSHR uncacheable cycles
2407 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13655000 # number of overall MSHR uncacheable cycles
2408 system.cpu1.icache.overall_mshr_uncacheable_latency::total 13655000 # number of overall MSHR uncacheable cycles
2409 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for ReadReq accesses
2410 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076554 # mshr miss rate for ReadReq accesses
2411 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for demand accesses
2412 system.cpu1.icache.demand_mshr_miss_rate::total 0.076554 # mshr miss rate for demand accesses
2413 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for overall accesses
2414 system.cpu1.icache.overall_mshr_miss_rate::total 0.076554 # mshr miss rate for overall accesses
2415 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average ReadReq mshr miss latency
2416 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8686.698890 # average ReadReq mshr miss latency
2417 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
2418 system.cpu1.icache.demand_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
2419 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
2420 system.cpu1.icache.overall_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
2421 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average ReadReq mshr uncacheable latency
2422 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133872.549020 # average ReadReq mshr uncacheable latency
2423 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average overall mshr uncacheable latency
2424 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133872.549020 # average overall mshr uncacheable latency
2425 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2426 system.cpu1.l2cache.prefetcher.num_hwpf_issued 119604 # number of hwpf issued
2427 system.cpu1.l2cache.prefetcher.pfIdentified 120343 # number of prefetch candidates identified
2428 system.cpu1.l2cache.prefetcher.pfBufferHit 669 # number of redundant prefetches already in prefetch queue
2429 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2430 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2431 system.cpu1.l2cache.prefetcher.pfSpanPage 49745 # number of prefetches not generated due to page crossing
2432 system.cpu1.l2cache.tags.replacements 36294 # number of replacements
2433 system.cpu1.l2cache.tags.tagsinuse 15213.941609 # Cycle average of tags in use
2434 system.cpu1.l2cache.tags.total_refs 1184366 # Total number of references to valid blocks.
2435 system.cpu1.l2cache.tags.sampled_refs 51460 # Sample count of references to valid blocks.
2436 system.cpu1.l2cache.tags.avg_refs 23.015274 # Average number of references to valid blocks.
2437 system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2438 system.cpu1.l2cache.tags.occ_blocks::writebacks 14744.109202 # Average occupied blocks per requestor
2439 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.751628 # Average occupied blocks per requestor
2440 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 4.727886 # Average occupied blocks per requestor
2441 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 454.352894 # Average occupied blocks per requestor
2442 system.cpu1.l2cache.tags.occ_percent::writebacks 0.899909 # Average percentage of cache occupancy
2443 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000656 # Average percentage of cache occupancy
2444 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000289 # Average percentage of cache occupancy
2445 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027731 # Average percentage of cache occupancy
2446 system.cpu1.l2cache.tags.occ_percent::total 0.928585 # Average percentage of cache occupancy
2447 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 946 # Occupied blocks per task id
2448 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id
2449 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14156 # Occupied blocks per task id
2450 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id
2451 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
2452 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 319 # Occupied blocks per task id
2453 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
2454 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
2455 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
2456 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 800 # Occupied blocks per task id
2457 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2726 # Occupied blocks per task id
2458 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10630 # Occupied blocks per task id
2459 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057739 # Percentage of cache occupancy per task id
2460 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id
2461 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864014 # Percentage of cache occupancy per task id
2462 system.cpu1.l2cache.tags.tag_accesses 23534667 # Number of tag accesses
2463 system.cpu1.l2cache.tags.data_accesses 23534667 # Number of data accesses
2464 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 11642 # number of ReadReq hits
2465 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5450 # number of ReadReq hits
2466 system.cpu1.l2cache.ReadReq_hits::total 17092 # number of ReadReq hits
2467 system.cpu1.l2cache.WritebackDirty_hits::writebacks 91128 # number of WritebackDirty hits
2468 system.cpu1.l2cache.WritebackDirty_hits::total 91128 # number of WritebackDirty hits
2469 system.cpu1.l2cache.WritebackClean_hits::writebacks 577481 # number of WritebackClean hits
2470 system.cpu1.l2cache.WritebackClean_hits::total 577481 # number of WritebackClean hits
2471 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16562 # number of ReadExReq hits
2472 system.cpu1.l2cache.ReadExReq_hits::total 16562 # number of ReadExReq hits
2473 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 522608 # number of ReadCleanReq hits
2474 system.cpu1.l2cache.ReadCleanReq_hits::total 522608 # number of ReadCleanReq hits
2475 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77065 # number of ReadSharedReq hits
2476 system.cpu1.l2cache.ReadSharedReq_hits::total 77065 # number of ReadSharedReq hits
2477 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 11642 # number of demand (read+write) hits
2478 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5450 # number of demand (read+write) hits
2479 system.cpu1.l2cache.demand_hits::cpu1.inst 522608 # number of demand (read+write) hits
2480 system.cpu1.l2cache.demand_hits::cpu1.data 93627 # number of demand (read+write) hits
2481 system.cpu1.l2cache.demand_hits::total 633327 # number of demand (read+write) hits
2482 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 11642 # number of overall hits
2483 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5450 # number of overall hits
2484 system.cpu1.l2cache.overall_hits::cpu1.inst 522608 # number of overall hits
2485 system.cpu1.l2cache.overall_hits::cpu1.data 93627 # number of overall hits
2486 system.cpu1.l2cache.overall_hits::total 633327 # number of overall hits
2487 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses
2488 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses
2489 system.cpu1.l2cache.ReadReq_misses::total 742 # number of ReadReq misses
2490 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29194 # number of UpgradeReq misses
2491 system.cpu1.l2cache.UpgradeReq_misses::total 29194 # number of UpgradeReq misses
2492 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23153 # number of SCUpgradeReq misses
2493 system.cpu1.l2cache.SCUpgradeReq_misses::total 23153 # number of SCUpgradeReq misses
2494 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
2495 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
2496 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32879 # number of ReadExReq misses
2497 system.cpu1.l2cache.ReadExReq_misses::total 32879 # number of ReadExReq misses
2498 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10546 # number of ReadCleanReq misses
2499 system.cpu1.l2cache.ReadCleanReq_misses::total 10546 # number of ReadCleanReq misses
2500 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64491 # number of ReadSharedReq misses
2501 system.cpu1.l2cache.ReadSharedReq_misses::total 64491 # number of ReadSharedReq misses
2502 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses
2503 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses
2504 system.cpu1.l2cache.demand_misses::cpu1.inst 10546 # number of demand (read+write) misses
2505 system.cpu1.l2cache.demand_misses::cpu1.data 97370 # number of demand (read+write) misses
2506 system.cpu1.l2cache.demand_misses::total 108658 # number of demand (read+write) misses
2507 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses
2508 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses
2509 system.cpu1.l2cache.overall_misses::cpu1.inst 10546 # number of overall misses
2510 system.cpu1.l2cache.overall_misses::cpu1.data 97370 # number of overall misses
2511 system.cpu1.l2cache.overall_misses::total 108658 # number of overall misses
2512 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10388000 # number of ReadReq miss cycles
2513 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5548000 # number of ReadReq miss cycles
2514 system.cpu1.l2cache.ReadReq_miss_latency::total 15936000 # number of ReadReq miss cycles
2515 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 61302500 # number of UpgradeReq miss cycles
2516 system.cpu1.l2cache.UpgradeReq_miss_latency::total 61302500 # number of UpgradeReq miss cycles
2517 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 60199500 # number of SCUpgradeReq miss cycles
2518 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 60199500 # number of SCUpgradeReq miss cycles
2519 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1803000 # number of SCUpgradeFailReq miss cycles
2520 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1803000 # number of SCUpgradeFailReq miss cycles
2521 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1873781500 # number of ReadExReq miss cycles
2522 system.cpu1.l2cache.ReadExReq_miss_latency::total 1873781500 # number of ReadExReq miss cycles
2523 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 637936000 # number of ReadCleanReq miss cycles
2524 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 637936000 # number of ReadCleanReq miss cycles
2525 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1490442997 # number of ReadSharedReq miss cycles
2526 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1490442997 # number of ReadSharedReq miss cycles
2527 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10388000 # number of demand (read+write) miss cycles
2528 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5548000 # number of demand (read+write) miss cycles
2529 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 637936000 # number of demand (read+write) miss cycles
2530 system.cpu1.l2cache.demand_miss_latency::cpu1.data 3364224497 # number of demand (read+write) miss cycles
2531 system.cpu1.l2cache.demand_miss_latency::total 4018096497 # number of demand (read+write) miss cycles
2532 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10388000 # number of overall miss cycles
2533 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5548000 # number of overall miss cycles
2534 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 637936000 # number of overall miss cycles
2535 system.cpu1.l2cache.overall_miss_latency::cpu1.data 3364224497 # number of overall miss cycles
2536 system.cpu1.l2cache.overall_miss_latency::total 4018096497 # number of overall miss cycles
2537 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12114 # number of ReadReq accesses(hits+misses)
2538 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 5720 # number of ReadReq accesses(hits+misses)
2539 system.cpu1.l2cache.ReadReq_accesses::total 17834 # number of ReadReq accesses(hits+misses)
2540 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91128 # number of WritebackDirty accesses(hits+misses)
2541 system.cpu1.l2cache.WritebackDirty_accesses::total 91128 # number of WritebackDirty accesses(hits+misses)
2542 system.cpu1.l2cache.WritebackClean_accesses::writebacks 577481 # number of WritebackClean accesses(hits+misses)
2543 system.cpu1.l2cache.WritebackClean_accesses::total 577481 # number of WritebackClean accesses(hits+misses)
2544 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29194 # number of UpgradeReq accesses(hits+misses)
2545 system.cpu1.l2cache.UpgradeReq_accesses::total 29194 # number of UpgradeReq accesses(hits+misses)
2546 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23153 # number of SCUpgradeReq accesses(hits+misses)
2547 system.cpu1.l2cache.SCUpgradeReq_accesses::total 23153 # number of SCUpgradeReq accesses(hits+misses)
2548 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
2549 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
2550 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49441 # number of ReadExReq accesses(hits+misses)
2551 system.cpu1.l2cache.ReadExReq_accesses::total 49441 # number of ReadExReq accesses(hits+misses)
2552 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 533154 # number of ReadCleanReq accesses(hits+misses)
2553 system.cpu1.l2cache.ReadCleanReq_accesses::total 533154 # number of ReadCleanReq accesses(hits+misses)
2554 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141556 # number of ReadSharedReq accesses(hits+misses)
2555 system.cpu1.l2cache.ReadSharedReq_accesses::total 141556 # number of ReadSharedReq accesses(hits+misses)
2556 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12114 # number of demand (read+write) accesses
2557 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 5720 # number of demand (read+write) accesses
2558 system.cpu1.l2cache.demand_accesses::cpu1.inst 533154 # number of demand (read+write) accesses
2559 system.cpu1.l2cache.demand_accesses::cpu1.data 190997 # number of demand (read+write) accesses
2560 system.cpu1.l2cache.demand_accesses::total 741985 # number of demand (read+write) accesses
2561 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12114 # number of overall (read+write) accesses
2562 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 5720 # number of overall (read+write) accesses
2563 system.cpu1.l2cache.overall_accesses::cpu1.inst 533154 # number of overall (read+write) accesses
2564 system.cpu1.l2cache.overall_accesses::cpu1.data 190997 # number of overall (read+write) accesses
2565 system.cpu1.l2cache.overall_accesses::total 741985 # number of overall (read+write) accesses
2566 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for ReadReq accesses
2567 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047203 # miss rate for ReadReq accesses
2568 system.cpu1.l2cache.ReadReq_miss_rate::total 0.041606 # miss rate for ReadReq accesses
2569 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2570 system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2571 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2572 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2573 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2574 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2575 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.665015 # miss rate for ReadExReq accesses
2576 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.665015 # miss rate for ReadExReq accesses
2577 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019780 # miss rate for ReadCleanReq accesses
2578 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019780 # miss rate for ReadCleanReq accesses
2579 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.455586 # miss rate for ReadSharedReq accesses
2580 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.455586 # miss rate for ReadSharedReq accesses
2581 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for demand accesses
2582 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047203 # miss rate for demand accesses
2583 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019780 # miss rate for demand accesses
2584 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509799 # miss rate for demand accesses
2585 system.cpu1.l2cache.demand_miss_rate::total 0.146442 # miss rate for demand accesses
2586 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for overall accesses
2587 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047203 # miss rate for overall accesses
2588 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019780 # miss rate for overall accesses
2589 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509799 # miss rate for overall accesses
2590 system.cpu1.l2cache.overall_miss_rate::total 0.146442 # miss rate for overall accesses
2591 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average ReadReq miss latency
2592 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20548.148148 # average ReadReq miss latency
2593 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21477.088949 # average ReadReq miss latency
2594 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2099.832157 # average UpgradeReq miss latency
2595 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2099.832157 # average UpgradeReq miss latency
2596 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2600.073425 # average SCUpgradeReq miss latency
2597 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2600.073425 # average SCUpgradeReq miss latency
2598 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1803000 # average SCUpgradeFailReq miss latency
2599 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1803000 # average SCUpgradeFailReq miss latency
2600 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56990.221722 # average ReadExReq miss latency
2601 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56990.221722 # average ReadExReq miss latency
2602 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60490.802200 # average ReadCleanReq miss latency
2603 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60490.802200 # average ReadCleanReq miss latency
2604 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23110.868137 # average ReadSharedReq miss latency
2605 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23110.868137 # average ReadSharedReq miss latency
2606 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average overall miss latency
2607 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
2608 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
2609 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34550.934549 # average overall miss latency
2610 system.cpu1.l2cache.demand_avg_miss_latency::total 36979.297401 # average overall miss latency
2611 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average overall miss latency
2612 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
2613 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
2614 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34550.934549 # average overall miss latency
2615 system.cpu1.l2cache.overall_avg_miss_latency::total 36979.297401 # average overall miss latency
2616 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2617 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2618 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2619 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2620 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2621 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2622 system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2623 system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2624 system.cpu1.l2cache.unused_prefetches 518 # number of HardPF blocks evicted w/o reference
2625 system.cpu1.l2cache.writebacks::writebacks 29343 # number of writebacks
2626 system.cpu1.l2cache.writebacks::total 29343 # number of writebacks
2627 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1270 # number of ReadExReq MSHR hits
2628 system.cpu1.l2cache.ReadExReq_mshr_hits::total 1270 # number of ReadExReq MSHR hits
2629 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits
2630 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
2631 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 29 # number of ReadSharedReq MSHR hits
2632 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 29 # number of ReadSharedReq MSHR hits
2633 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
2634 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1299 # number of demand (read+write) MSHR hits
2635 system.cpu1.l2cache.demand_mshr_hits::total 1302 # number of demand (read+write) MSHR hits
2636 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
2637 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1299 # number of overall MSHR hits
2638 system.cpu1.l2cache.overall_mshr_hits::total 1302 # number of overall MSHR hits
2639 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses
2640 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 270 # number of ReadReq MSHR misses
2641 system.cpu1.l2cache.ReadReq_mshr_misses::total 742 # number of ReadReq MSHR misses
2642 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21229 # number of HardPFReq MSHR misses
2643 system.cpu1.l2cache.HardPFReq_mshr_misses::total 21229 # number of HardPFReq MSHR misses
2644 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29194 # number of UpgradeReq MSHR misses
2645 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29194 # number of UpgradeReq MSHR misses
2646 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23153 # number of SCUpgradeReq MSHR misses
2647 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23153 # number of SCUpgradeReq MSHR misses
2648 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2649 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2650 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31609 # number of ReadExReq MSHR misses
2651 system.cpu1.l2cache.ReadExReq_mshr_misses::total 31609 # number of ReadExReq MSHR misses
2652 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10543 # number of ReadCleanReq MSHR misses
2653 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10543 # number of ReadCleanReq MSHR misses
2654 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64462 # number of ReadSharedReq MSHR misses
2655 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64462 # number of ReadSharedReq MSHR misses
2656 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses
2657 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 270 # number of demand (read+write) MSHR misses
2658 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10543 # number of demand (read+write) MSHR misses
2659 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96071 # number of demand (read+write) MSHR misses
2660 system.cpu1.l2cache.demand_mshr_misses::total 107356 # number of demand (read+write) MSHR misses
2661 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses
2662 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 270 # number of overall MSHR misses
2663 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10543 # number of overall MSHR misses
2664 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96071 # number of overall MSHR misses
2665 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21229 # number of overall MSHR misses
2666 system.cpu1.l2cache.overall_mshr_misses::total 128585 # number of overall MSHR misses
2667 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2668 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
2669 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3177 # number of ReadReq MSHR uncacheable
2670 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
2671 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2419 # number of WriteReq MSHR uncacheable
2672 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2673 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5494 # number of overall MSHR uncacheable misses
2674 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5596 # number of overall MSHR uncacheable misses
2675 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of ReadReq MSHR miss cycles
2676 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3928000 # number of ReadReq MSHR miss cycles
2677 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11484000 # number of ReadReq MSHR miss cycles
2678 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1356296825 # number of HardPFReq MSHR miss cycles
2679 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1356296825 # number of HardPFReq MSHR miss cycles
2680 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 583735000 # number of UpgradeReq MSHR miss cycles
2681 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 583735000 # number of UpgradeReq MSHR miss cycles
2682 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 426936499 # number of SCUpgradeReq MSHR miss cycles
2683 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 426936499 # number of SCUpgradeReq MSHR miss cycles
2684 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1695000 # number of SCUpgradeFailReq MSHR miss cycles
2685 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1695000 # number of SCUpgradeFailReq MSHR miss cycles
2686 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1581842500 # number of ReadExReq MSHR miss cycles
2687 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1581842500 # number of ReadExReq MSHR miss cycles
2688 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 574617500 # number of ReadCleanReq MSHR miss cycles
2689 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 574617500 # number of ReadCleanReq MSHR miss cycles
2690 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1102358997 # number of ReadSharedReq MSHR miss cycles
2691 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1102358997 # number of ReadSharedReq MSHR miss cycles
2692 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of demand (read+write) MSHR miss cycles
2693 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3928000 # number of demand (read+write) MSHR miss cycles
2694 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 574617500 # number of demand (read+write) MSHR miss cycles
2695 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2684201497 # number of demand (read+write) MSHR miss cycles
2696 system.cpu1.l2cache.demand_mshr_miss_latency::total 3270302997 # number of demand (read+write) MSHR miss cycles
2697 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of overall MSHR miss cycles
2698 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3928000 # number of overall MSHR miss cycles
2699 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 574617500 # number of overall MSHR miss cycles
2700 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2684201497 # number of overall MSHR miss cycles
2701 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1356296825 # number of overall MSHR miss cycles
2702 system.cpu1.l2cache.overall_mshr_miss_latency::total 4626599822 # number of overall MSHR miss cycles
2703 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12890000 # number of ReadReq MSHR uncacheable cycles
2704 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 413788000 # number of ReadReq MSHR uncacheable cycles
2705 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 426678000 # number of ReadReq MSHR uncacheable cycles
2706 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 283458994 # number of WriteReq MSHR uncacheable cycles
2707 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 283458994 # number of WriteReq MSHR uncacheable cycles
2708 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12890000 # number of overall MSHR uncacheable cycles
2709 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 697246994 # number of overall MSHR uncacheable cycles
2710 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 710136994 # number of overall MSHR uncacheable cycles
2711 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for ReadReq accesses
2712 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for ReadReq accesses
2713 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041606 # mshr miss rate for ReadReq accesses
2714 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2715 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2716 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2717 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2718 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2719 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2720 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2721 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2722 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639328 # mshr miss rate for ReadExReq accesses
2723 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639328 # mshr miss rate for ReadExReq accesses
2724 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for ReadCleanReq accesses
2725 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019775 # mshr miss rate for ReadCleanReq accesses
2726 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.455382 # mshr miss rate for ReadSharedReq accesses
2727 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.455382 # mshr miss rate for ReadSharedReq accesses
2728 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for demand accesses
2729 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for demand accesses
2730 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for demand accesses
2731 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for demand accesses
2732 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.144688 # mshr miss rate for demand accesses
2733 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for overall accesses
2734 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for overall accesses
2735 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for overall accesses
2736 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for overall accesses
2737 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2738 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173299 # mshr miss rate for overall accesses
2739 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average ReadReq mshr miss latency
2740 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average ReadReq mshr miss latency
2741 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15477.088949 # average ReadReq mshr miss latency
2742 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average HardPFReq mshr miss latency
2743 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63888.870178 # average HardPFReq mshr miss latency
2744 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19995.033226 # average UpgradeReq mshr miss latency
2745 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19995.033226 # average UpgradeReq mshr miss latency
2746 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18439.791776 # average SCUpgradeReq mshr miss latency
2747 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18439.791776 # average SCUpgradeReq mshr miss latency
2748 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1695000 # average SCUpgradeFailReq mshr miss latency
2749 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1695000 # average SCUpgradeFailReq mshr miss latency
2750 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50044.053909 # average ReadExReq mshr miss latency
2751 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50044.053909 # average ReadExReq mshr miss latency
2752 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average ReadCleanReq mshr miss latency
2753 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54502.276392 # average ReadCleanReq mshr miss latency
2754 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17100.912119 # average ReadSharedReq mshr miss latency
2755 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17100.912119 # average ReadSharedReq mshr miss latency
2756 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
2757 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
2758 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
2759 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
2760 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30462.228446 # average overall mshr miss latency
2761 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
2762 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
2763 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
2764 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
2765 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average overall mshr miss latency
2766 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35980.867302 # average overall mshr miss latency
2767 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average ReadReq mshr uncacheable latency
2768 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134565.203252 # average ReadReq mshr uncacheable latency
2769 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134302.171860 # average ReadReq mshr uncacheable latency
2770 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117180.237288 # average WriteReq mshr uncacheable latency
2771 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117180.237288 # average WriteReq mshr uncacheable latency
2772 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average overall mshr uncacheable latency
2773 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126910.628686 # average overall mshr uncacheable latency
2774 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126900.820944 # average overall mshr uncacheable latency
2775 system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2776 system.cpu1.toL2Bus.snoop_filter.tot_requests 1463686 # Total number of requests made to the snoop filter.
2777 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 739552 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2778 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2779 system.cpu1.toL2Bus.snoop_filter.tot_snoops 170999 # Total number of snoops made to the snoop filter.
2780 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169235 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2781 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1764 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2782 system.cpu1.toL2Bus.trans_dist::ReadReq 24298 # Transaction distribution
2783 system.cpu1.toL2Bus.trans_dist::ReadResp 736701 # Transaction distribution
2784 system.cpu1.toL2Bus.trans_dist::WriteReq 2419 # Transaction distribution
2785 system.cpu1.toL2Bus.trans_dist::WriteResp 2419 # Transaction distribution
2786 system.cpu1.toL2Bus.trans_dist::WritebackDirty 121677 # Transaction distribution
2787 system.cpu1.toL2Bus.trans_dist::WritebackClean 588534 # Transaction distribution
2788 system.cpu1.toL2Bus.trans_dist::CleanEvict 90826 # Transaction distribution
2789 system.cpu1.toL2Bus.trans_dist::HardPFReq 26224 # Transaction distribution
2790 system.cpu1.toL2Bus.trans_dist::UpgradeReq 69999 # Transaction distribution
2791 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41335 # Transaction distribution
2792 system.cpu1.toL2Bus.trans_dist::UpgradeResp 85194 # Transaction distribution
2793 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
2794 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
2795 system.cpu1.toL2Bus.trans_dist::ReadExReq 56383 # Transaction distribution
2796 system.cpu1.toL2Bus.trans_dist::ReadExResp 54101 # Transaction distribution
2797 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 533160 # Transaction distribution
2798 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 217797 # Transaction distribution
2799 system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
2800 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1599162 # Packet count per connected master and slave (bytes)
2801 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 719912 # Packet count per connected master and slave (bytes)
2802 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12717 # Packet count per connected master and slave (bytes)
2803 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26238 # Packet count per connected master and slave (bytes)
2804 system.cpu1.toL2Bus.pkt_count::total 2358029 # Packet count per connected master and slave (bytes)
2805 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 68212704 # Cumulative packet size per connected master and slave (bytes)
2806 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24362994 # Cumulative packet size per connected master and slave (bytes)
2807 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 22880 # Cumulative packet size per connected master and slave (bytes)
2808 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48456 # Cumulative packet size per connected master and slave (bytes)
2809 system.cpu1.toL2Bus.pkt_size::total 92647034 # Cumulative packet size per connected master and slave (bytes)
2810 system.cpu1.toL2Bus.snoops 368307 # Total snoops (count)
2811 system.cpu1.toL2Bus.snoop_fanout::samples 1093026 # Request fanout histogram
2812 system.cpu1.toL2Bus.snoop_fanout::mean 0.175061 # Request fanout histogram
2813 system.cpu1.toL2Bus.snoop_fanout::stdev 0.384243 # Request fanout histogram
2814 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2815 system.cpu1.toL2Bus.snoop_fanout::0 903444 82.66% 82.66% # Request fanout histogram
2816 system.cpu1.toL2Bus.snoop_fanout::1 187818 17.18% 99.84% # Request fanout histogram
2817 system.cpu1.toL2Bus.snoop_fanout::2 1764 0.16% 100.00% # Request fanout histogram
2818 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2819 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2820 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2821 system.cpu1.toL2Bus.snoop_fanout::total 1093026 # Request fanout histogram
2822 system.cpu1.toL2Bus.reqLayer0.occupancy 1422321490 # Layer occupancy (ticks)
2823 system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2824 system.cpu1.toL2Bus.snoopLayer0.occupancy 79991516 # Layer occupancy (ticks)
2825 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2826 system.cpu1.toL2Bus.respLayer0.occupancy 799908367 # Layer occupancy (ticks)
2827 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2828 system.cpu1.toL2Bus.respLayer1.occupancy 318043852 # Layer occupancy (ticks)
2829 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2830 system.cpu1.toL2Bus.respLayer2.occupancy 6997998 # Layer occupancy (ticks)
2831 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2832 system.cpu1.toL2Bus.respLayer3.occupancy 14133980 # Layer occupancy (ticks)
2833 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2834 system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
2835 system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
2836 system.iobus.trans_dist::WriteReq 59424 # Transaction distribution
2837 system.iobus.trans_dist::WriteResp 59424 # Transaction distribution
2838 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes)
2839 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2840 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2841 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2842 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2843 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2844 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2845 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2846 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2847 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2848 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2849 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2850 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2851 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2852 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2853 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2854 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2855 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2856 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2857 system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes)
2858 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
2859 system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
2860 system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes)
2861 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes)
2862 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2863 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2864 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2865 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2866 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2867 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2868 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2869 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2870 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2871 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2872 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2873 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2874 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2875 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2876 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2877 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2878 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2879 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2880 system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes)
2881 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
2882 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2883 system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
2884 system.iobus.reqLayer0.occupancy 40405500 # Layer occupancy (ticks)
2885 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2886 system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
2887 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2888 system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
2889 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2890 system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
2891 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2892 system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2893 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2894 system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks)
2895 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2896 system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
2897 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2898 system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2899 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2900 system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2901 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2902 system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2903 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2904 system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2905 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2906 system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
2907 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2908 system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2909 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2910 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
2911 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2912 system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2913 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2914 system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2915 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2916 system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2917 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2918 system.iobus.reqLayer23.occupancy 6085500 # Layer occupancy (ticks)
2919 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2920 system.iobus.reqLayer24.occupancy 34122000 # Layer occupancy (ticks)
2921 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2922 system.iobus.reqLayer25.occupancy 187170938 # Layer occupancy (ticks)
2923 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2924 system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
2925 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2926 system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2927 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2928 system.iocache.tags.replacements 36458 # number of replacements
2929 system.iocache.tags.tagsinuse 14.550737 # Cycle average of tags in use
2930 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2931 system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2932 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2933 system.iocache.tags.warmup_cycle 256092273000 # Cycle when the warmup percentage was hit.
2934 system.iocache.tags.occ_blocks::realview.ide 14.550737 # Average occupied blocks per requestor
2935 system.iocache.tags.occ_percent::realview.ide 0.909421 # Average percentage of cache occupancy
2936 system.iocache.tags.occ_percent::total 0.909421 # Average percentage of cache occupancy
2937 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2938 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2939 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2940 system.iocache.tags.tag_accesses 328284 # Number of tag accesses
2941 system.iocache.tags.data_accesses 328284 # Number of data accesses
2942 system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2943 system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2944 system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2945 system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2946 system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2947 system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2948 system.iocache.overall_misses::realview.ide 252 # number of overall misses
2949 system.iocache.overall_misses::total 252 # number of overall misses
2950 system.iocache.ReadReq_miss_latency::realview.ide 32570877 # number of ReadReq miss cycles
2951 system.iocache.ReadReq_miss_latency::total 32570877 # number of ReadReq miss cycles
2952 system.iocache.WriteLineReq_miss_latency::realview.ide 4577184061 # number of WriteLineReq miss cycles
2953 system.iocache.WriteLineReq_miss_latency::total 4577184061 # number of WriteLineReq miss cycles
2954 system.iocache.demand_miss_latency::realview.ide 32570877 # number of demand (read+write) miss cycles
2955 system.iocache.demand_miss_latency::total 32570877 # number of demand (read+write) miss cycles
2956 system.iocache.overall_miss_latency::realview.ide 32570877 # number of overall miss cycles
2957 system.iocache.overall_miss_latency::total 32570877 # number of overall miss cycles
2958 system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2959 system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2960 system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2961 system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2962 system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2963 system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2964 system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2965 system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2966 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2967 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2968 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2969 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2970 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2971 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2972 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2973 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2974 system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905 # average ReadReq miss latency
2975 system.iocache.ReadReq_avg_miss_latency::total 129249.511905 # average ReadReq miss latency
2976 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536 # average WriteLineReq miss latency
2977 system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536 # average WriteLineReq miss latency
2978 system.iocache.demand_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
2979 system.iocache.demand_avg_miss_latency::total 129249.511905 # average overall miss latency
2980 system.iocache.overall_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
2981 system.iocache.overall_avg_miss_latency::total 129249.511905 # average overall miss latency
2982 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2983 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2984 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2985 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2986 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2987 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2988 system.iocache.fast_writes 0 # number of fast writes performed
2989 system.iocache.cache_copies 0 # number of cache copies performed
2990 system.iocache.writebacks::writebacks 36206 # number of writebacks
2991 system.iocache.writebacks::total 36206 # number of writebacks
2992 system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
2993 system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2994 system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2995 system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2996 system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
2997 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
2998 system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
2999 system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
3000 system.iocache.ReadReq_mshr_miss_latency::realview.ide 19970877 # number of ReadReq MSHR miss cycles
3001 system.iocache.ReadReq_mshr_miss_latency::total 19970877 # number of ReadReq MSHR miss cycles
3002 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764245413 # number of WriteLineReq MSHR miss cycles
3003 system.iocache.WriteLineReq_mshr_miss_latency::total 2764245413 # number of WriteLineReq MSHR miss cycles
3004 system.iocache.demand_mshr_miss_latency::realview.ide 19970877 # number of demand (read+write) MSHR miss cycles
3005 system.iocache.demand_mshr_miss_latency::total 19970877 # number of demand (read+write) MSHR miss cycles
3006 system.iocache.overall_mshr_miss_latency::realview.ide 19970877 # number of overall MSHR miss cycles
3007 system.iocache.overall_mshr_miss_latency::total 19970877 # number of overall MSHR miss cycles
3008 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3009 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3010 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3011 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3012 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3013 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3014 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3015 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3016 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79249.511905 # average ReadReq mshr miss latency
3017 system.iocache.ReadReq_avg_mshr_miss_latency::total 79249.511905 # average ReadReq mshr miss latency
3018 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76309.778407 # average WriteLineReq mshr miss latency
3019 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76309.778407 # average WriteLineReq mshr miss latency
3020 system.iocache.demand_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
3021 system.iocache.demand_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
3022 system.iocache.overall_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
3023 system.iocache.overall_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
3024 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3025 system.l2c.tags.replacements 130481 # number of replacements
3026 system.l2c.tags.tagsinuse 63162.524815 # Cycle average of tags in use
3027 system.l2c.tags.total_refs 437656 # Total number of references to valid blocks.
3028 system.l2c.tags.sampled_refs 194611 # Sample count of references to valid blocks.
3029 system.l2c.tags.avg_refs 2.248876 # Average number of references to valid blocks.
3030 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3031 system.l2c.tags.occ_blocks::writebacks 13531.746388 # Average occupied blocks per requestor
3032 system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.289436 # Average occupied blocks per requestor
3033 system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065903 # Average occupied blocks per requestor
3034 system.l2c.tags.occ_blocks::cpu0.inst 8160.706658 # Average occupied blocks per requestor
3035 system.l2c.tags.occ_blocks::cpu0.data 2775.310647 # Average occupied blocks per requestor
3036 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33971.574296 # Average occupied blocks per requestor
3037 system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.602927 # Average occupied blocks per requestor
3038 system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909521 # Average occupied blocks per requestor
3039 system.l2c.tags.occ_blocks::cpu1.inst 1734.289932 # Average occupied blocks per requestor
3040 system.l2c.tags.occ_blocks::cpu1.data 612.780861 # Average occupied blocks per requestor
3041 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2352.248246 # Average occupied blocks per requestor
3042 system.l2c.tags.occ_percent::writebacks 0.206478 # Average percentage of cache occupancy
3043 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000264 # Average percentage of cache occupancy
3044 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
3045 system.l2c.tags.occ_percent::cpu0.inst 0.124523 # Average percentage of cache occupancy
3046 system.l2c.tags.occ_percent::cpu0.data 0.042348 # Average percentage of cache occupancy
3047 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.518365 # Average percentage of cache occupancy
3048 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy
3049 system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
3050 system.l2c.tags.occ_percent::cpu1.inst 0.026463 # Average percentage of cache occupancy
3051 system.l2c.tags.occ_percent::cpu1.data 0.009350 # Average percentage of cache occupancy
3052 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035892 # Average percentage of cache occupancy
3053 system.l2c.tags.occ_percent::total 0.963784 # Average percentage of cache occupancy
3054 system.l2c.tags.occ_task_id_blocks::1022 30783 # Occupied blocks per task id
3055 system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
3056 system.l2c.tags.occ_task_id_blocks::1024 33327 # Occupied blocks per task id
3057 system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
3058 system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id
3059 system.l2c.tags.age_task_id_blocks_1022::3 5989 # Occupied blocks per task id
3060 system.l2c.tags.age_task_id_blocks_1022::4 24666 # Occupied blocks per task id
3061 system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
3062 system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
3063 system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
3064 system.l2c.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id
3065 system.l2c.tags.age_task_id_blocks_1024::3 4321 # Occupied blocks per task id
3066 system.l2c.tags.age_task_id_blocks_1024::4 28334 # Occupied blocks per task id
3067 system.l2c.tags.occ_task_id_percent::1022 0.469711 # Percentage of cache occupancy per task id
3068 system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
3069 system.l2c.tags.occ_task_id_percent::1024 0.508530 # Percentage of cache occupancy per task id
3070 system.l2c.tags.tag_accesses 6042349 # Number of tag accesses
3071 system.l2c.tags.data_accesses 6042349 # Number of data accesses
3072 system.l2c.WritebackDirty_hits::writebacks 262546 # number of WritebackDirty hits
3073 system.l2c.WritebackDirty_hits::total 262546 # number of WritebackDirty hits
3074 system.l2c.UpgradeReq_hits::cpu0.data 32542 # number of UpgradeReq hits
3075 system.l2c.UpgradeReq_hits::cpu1.data 2076 # number of UpgradeReq hits
3076 system.l2c.UpgradeReq_hits::total 34618 # number of UpgradeReq hits
3077 system.l2c.SCUpgradeReq_hits::cpu0.data 2163 # number of SCUpgradeReq hits
3078 system.l2c.SCUpgradeReq_hits::cpu1.data 775 # number of SCUpgradeReq hits
3079 system.l2c.SCUpgradeReq_hits::total 2938 # number of SCUpgradeReq hits
3080 system.l2c.ReadExReq_hits::cpu0.data 3848 # number of ReadExReq hits
3081 system.l2c.ReadExReq_hits::cpu1.data 1021 # number of ReadExReq hits
3082 system.l2c.ReadExReq_hits::total 4869 # number of ReadExReq hits
3083 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 186 # number of ReadSharedReq hits
3084 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits
3085 system.l2c.ReadSharedReq_hits::cpu0.inst 34162 # number of ReadSharedReq hits
3086 system.l2c.ReadSharedReq_hits::cpu0.data 48429 # number of ReadSharedReq hits
3087 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46477 # number of ReadSharedReq hits
3088 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits
3089 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
3090 system.l2c.ReadSharedReq_hits::cpu1.inst 7717 # number of ReadSharedReq hits
3091 system.l2c.ReadSharedReq_hits::cpu1.data 5261 # number of ReadSharedReq hits
3092 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3686 # number of ReadSharedReq hits
3093 system.l2c.ReadSharedReq_hits::total 146069 # number of ReadSharedReq hits
3094 system.l2c.demand_hits::cpu0.dtb.walker 186 # number of demand (read+write) hits
3095 system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits
3096 system.l2c.demand_hits::cpu0.inst 34162 # number of demand (read+write) hits
3097 system.l2c.demand_hits::cpu0.data 52277 # number of demand (read+write) hits
3098 system.l2c.demand_hits::cpu0.l2cache.prefetcher 46477 # number of demand (read+write) hits
3099 system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
3100 system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
3101 system.l2c.demand_hits::cpu1.inst 7717 # number of demand (read+write) hits
3102 system.l2c.demand_hits::cpu1.data 6282 # number of demand (read+write) hits
3103 system.l2c.demand_hits::cpu1.l2cache.prefetcher 3686 # number of demand (read+write) hits
3104 system.l2c.demand_hits::total 150938 # number of demand (read+write) hits
3105 system.l2c.overall_hits::cpu0.dtb.walker 186 # number of overall hits
3106 system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits
3107 system.l2c.overall_hits::cpu0.inst 34162 # number of overall hits
3108 system.l2c.overall_hits::cpu0.data 52277 # number of overall hits
3109 system.l2c.overall_hits::cpu0.l2cache.prefetcher 46477 # number of overall hits
3110 system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
3111 system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
3112 system.l2c.overall_hits::cpu1.inst 7717 # number of overall hits
3113 system.l2c.overall_hits::cpu1.data 6282 # number of overall hits
3114 system.l2c.overall_hits::cpu1.l2cache.prefetcher 3686 # number of overall hits
3115 system.l2c.overall_hits::total 150938 # number of overall hits
3116 system.l2c.UpgradeReq_misses::cpu0.data 9567 # number of UpgradeReq misses
3117 system.l2c.UpgradeReq_misses::cpu1.data 2216 # number of UpgradeReq misses
3118 system.l2c.UpgradeReq_misses::total 11783 # number of UpgradeReq misses
3119 system.l2c.SCUpgradeReq_misses::cpu0.data 708 # number of SCUpgradeReq misses
3120 system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # number of SCUpgradeReq misses
3121 system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses
3122 system.l2c.ReadExReq_misses::cpu0.data 11710 # number of ReadExReq misses
3123 system.l2c.ReadExReq_misses::cpu1.data 8783 # number of ReadExReq misses
3124 system.l2c.ReadExReq_misses::total 20493 # number of ReadExReq misses
3125 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses
3126 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
3127 system.l2c.ReadSharedReq_misses::cpu0.inst 19538 # number of ReadSharedReq misses
3128 system.l2c.ReadSharedReq_misses::cpu0.data 9228 # number of ReadSharedReq misses
3129 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134710 # number of ReadSharedReq misses
3130 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses
3131 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
3132 system.l2c.ReadSharedReq_misses::cpu1.inst 2825 # number of ReadSharedReq misses
3133 system.l2c.ReadSharedReq_misses::cpu1.data 1059 # number of ReadSharedReq misses
3134 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6993 # number of ReadSharedReq misses
3135 system.l2c.ReadSharedReq_misses::total 174391 # number of ReadSharedReq misses
3136 system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses
3137 system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
3138 system.l2c.demand_misses::cpu0.inst 19538 # number of demand (read+write) misses
3139 system.l2c.demand_misses::cpu0.data 20938 # number of demand (read+write) misses
3140 system.l2c.demand_misses::cpu0.l2cache.prefetcher 134710 # number of demand (read+write) misses
3141 system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses
3142 system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
3143 system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses
3144 system.l2c.demand_misses::cpu1.data 9842 # number of demand (read+write) misses
3145 system.l2c.demand_misses::cpu1.l2cache.prefetcher 6993 # number of demand (read+write) misses
3146 system.l2c.demand_misses::total 194884 # number of demand (read+write) misses
3147 system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses
3148 system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
3149 system.l2c.overall_misses::cpu0.inst 19538 # number of overall misses
3150 system.l2c.overall_misses::cpu0.data 20938 # number of overall misses
3151 system.l2c.overall_misses::cpu0.l2cache.prefetcher 134710 # number of overall misses
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3156 system.l2c.overall_misses::cpu1.l2cache.prefetcher 6993 # number of overall misses
3157 system.l2c.overall_misses::total 194884 # number of overall misses
3158 system.l2c.UpgradeReq_miss_latency::cpu0.data 21715500 # number of UpgradeReq miss cycles
3159 system.l2c.UpgradeReq_miss_latency::cpu1.data 4407500 # number of UpgradeReq miss cycles
3160 system.l2c.UpgradeReq_miss_latency::total 26123000 # number of UpgradeReq miss cycles
3161 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5011500 # number of SCUpgradeReq miss cycles
3162 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2024500 # number of SCUpgradeReq miss cycles
3163 system.l2c.SCUpgradeReq_miss_latency::total 7036000 # number of SCUpgradeReq miss cycles
3164 system.l2c.ReadExReq_miss_latency::cpu0.data 1773470500 # number of ReadExReq miss cycles
3165 system.l2c.ReadExReq_miss_latency::cpu1.data 1179481000 # number of ReadExReq miss cycles
3166 system.l2c.ReadExReq_miss_latency::total 2952951500 # number of ReadExReq miss cycles
3167 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4090000 # number of ReadSharedReq miss cycles
3168 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles
3169 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2590822501 # number of ReadSharedReq miss cycles
3170 system.l2c.ReadSharedReq_miss_latency::cpu0.data 1287354500 # number of ReadSharedReq miss cycles
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3172 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 838000 # number of ReadSharedReq miss cycles
3173 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles
3174 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 379417500 # number of ReadSharedReq miss cycles
3175 system.l2c.ReadSharedReq_miss_latency::cpu1.data 152189500 # number of ReadSharedReq miss cycles
3176 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of ReadSharedReq miss cycles
3177 system.l2c.ReadSharedReq_miss_latency::total 27002299072 # number of ReadSharedReq miss cycles
3178 system.l2c.demand_miss_latency::cpu0.dtb.walker 4090000 # number of demand (read+write) miss cycles
3179 system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles
3180 system.l2c.demand_miss_latency::cpu0.inst 2590822501 # number of demand (read+write) miss cycles
3181 system.l2c.demand_miss_latency::cpu0.data 3060825000 # number of demand (read+write) miss cycles
3182 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of demand (read+write) miss cycles
3183 system.l2c.demand_miss_latency::cpu1.dtb.walker 838000 # number of demand (read+write) miss cycles
3184 system.l2c.demand_miss_latency::cpu1.itb.walker 132500 # number of demand (read+write) miss cycles
3185 system.l2c.demand_miss_latency::cpu1.inst 379417500 # number of demand (read+write) miss cycles
3186 system.l2c.demand_miss_latency::cpu1.data 1331670500 # number of demand (read+write) miss cycles
3187 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of demand (read+write) miss cycles
3188 system.l2c.demand_miss_latency::total 29955250572 # number of demand (read+write) miss cycles
3189 system.l2c.overall_miss_latency::cpu0.dtb.walker 4090000 # number of overall miss cycles
3190 system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles
3191 system.l2c.overall_miss_latency::cpu0.inst 2590822501 # number of overall miss cycles
3192 system.l2c.overall_miss_latency::cpu0.data 3060825000 # number of overall miss cycles
3193 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of overall miss cycles
3194 system.l2c.overall_miss_latency::cpu1.dtb.walker 838000 # number of overall miss cycles
3195 system.l2c.overall_miss_latency::cpu1.itb.walker 132500 # number of overall miss cycles
3196 system.l2c.overall_miss_latency::cpu1.inst 379417500 # number of overall miss cycles
3197 system.l2c.overall_miss_latency::cpu1.data 1331670500 # number of overall miss cycles
3198 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of overall miss cycles
3199 system.l2c.overall_miss_latency::total 29955250572 # number of overall miss cycles
3200 system.l2c.WritebackDirty_accesses::writebacks 262546 # number of WritebackDirty accesses(hits+misses)
3201 system.l2c.WritebackDirty_accesses::total 262546 # number of WritebackDirty accesses(hits+misses)
3202 system.l2c.UpgradeReq_accesses::cpu0.data 42109 # number of UpgradeReq accesses(hits+misses)
3203 system.l2c.UpgradeReq_accesses::cpu1.data 4292 # number of UpgradeReq accesses(hits+misses)
3204 system.l2c.UpgradeReq_accesses::total 46401 # number of UpgradeReq accesses(hits+misses)
3205 system.l2c.SCUpgradeReq_accesses::cpu0.data 2871 # number of SCUpgradeReq accesses(hits+misses)
3206 system.l2c.SCUpgradeReq_accesses::cpu1.data 2012 # number of SCUpgradeReq accesses(hits+misses)
3207 system.l2c.SCUpgradeReq_accesses::total 4883 # number of SCUpgradeReq accesses(hits+misses)
3208 system.l2c.ReadExReq_accesses::cpu0.data 15558 # number of ReadExReq accesses(hits+misses)
3209 system.l2c.ReadExReq_accesses::cpu1.data 9804 # number of ReadExReq accesses(hits+misses)
3210 system.l2c.ReadExReq_accesses::total 25362 # number of ReadExReq accesses(hits+misses)
3211 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 214 # number of ReadSharedReq accesses(hits+misses)
3212 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 99 # number of ReadSharedReq accesses(hits+misses)
3213 system.l2c.ReadSharedReq_accesses::cpu0.inst 53700 # number of ReadSharedReq accesses(hits+misses)
3214 system.l2c.ReadSharedReq_accesses::cpu0.data 57657 # number of ReadSharedReq accesses(hits+misses)
3215 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 181187 # number of ReadSharedReq accesses(hits+misses)
3216 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 48 # number of ReadSharedReq accesses(hits+misses)
3217 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 14 # number of ReadSharedReq accesses(hits+misses)
3218 system.l2c.ReadSharedReq_accesses::cpu1.inst 10542 # number of ReadSharedReq accesses(hits+misses)
3219 system.l2c.ReadSharedReq_accesses::cpu1.data 6320 # number of ReadSharedReq accesses(hits+misses)
3220 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10679 # number of ReadSharedReq accesses(hits+misses)
3221 system.l2c.ReadSharedReq_accesses::total 320460 # number of ReadSharedReq accesses(hits+misses)
3222 system.l2c.demand_accesses::cpu0.dtb.walker 214 # number of demand (read+write) accesses
3223 system.l2c.demand_accesses::cpu0.itb.walker 99 # number of demand (read+write) accesses
3224 system.l2c.demand_accesses::cpu0.inst 53700 # number of demand (read+write) accesses
3225 system.l2c.demand_accesses::cpu0.data 73215 # number of demand (read+write) accesses
3226 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 181187 # number of demand (read+write) accesses
3227 system.l2c.demand_accesses::cpu1.dtb.walker 48 # number of demand (read+write) accesses
3228 system.l2c.demand_accesses::cpu1.itb.walker 14 # number of demand (read+write) accesses
3229 system.l2c.demand_accesses::cpu1.inst 10542 # number of demand (read+write) accesses
3230 system.l2c.demand_accesses::cpu1.data 16124 # number of demand (read+write) accesses
3231 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10679 # number of demand (read+write) accesses
3232 system.l2c.demand_accesses::total 345822 # number of demand (read+write) accesses
3233 system.l2c.overall_accesses::cpu0.dtb.walker 214 # number of overall (read+write) accesses
3234 system.l2c.overall_accesses::cpu0.itb.walker 99 # number of overall (read+write) accesses
3235 system.l2c.overall_accesses::cpu0.inst 53700 # number of overall (read+write) accesses
3236 system.l2c.overall_accesses::cpu0.data 73215 # number of overall (read+write) accesses
3237 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 181187 # number of overall (read+write) accesses
3238 system.l2c.overall_accesses::cpu1.dtb.walker 48 # number of overall (read+write) accesses
3239 system.l2c.overall_accesses::cpu1.itb.walker 14 # number of overall (read+write) accesses
3240 system.l2c.overall_accesses::cpu1.inst 10542 # number of overall (read+write) accesses
3241 system.l2c.overall_accesses::cpu1.data 16124 # number of overall (read+write) accesses
3242 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10679 # number of overall (read+write) accesses
3243 system.l2c.overall_accesses::total 345822 # number of overall (read+write) accesses
3244 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.227196 # miss rate for UpgradeReq accesses
3245 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.516309 # miss rate for UpgradeReq accesses
3246 system.l2c.UpgradeReq_miss_rate::total 0.253938 # miss rate for UpgradeReq accesses
3247 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.246604 # miss rate for SCUpgradeReq accesses
3248 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.614811 # miss rate for SCUpgradeReq accesses
3249 system.l2c.SCUpgradeReq_miss_rate::total 0.398321 # miss rate for SCUpgradeReq accesses
3250 system.l2c.ReadExReq_miss_rate::cpu0.data 0.752667 # miss rate for ReadExReq accesses
3251 system.l2c.ReadExReq_miss_rate::cpu1.data 0.895859 # miss rate for ReadExReq accesses
3252 system.l2c.ReadExReq_miss_rate::total 0.808020 # miss rate for ReadExReq accesses
3253 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for ReadSharedReq accesses
3254 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses
3255 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.363836 # miss rate for ReadSharedReq accesses
3256 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160050 # miss rate for ReadSharedReq accesses
3257 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for ReadSharedReq accesses
3258 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses
3259 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.071429 # miss rate for ReadSharedReq accesses
3260 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.267976 # miss rate for ReadSharedReq accesses
3261 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167563 # miss rate for ReadSharedReq accesses
3262 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for ReadSharedReq accesses
3263 system.l2c.ReadSharedReq_miss_rate::total 0.544190 # miss rate for ReadSharedReq accesses
3264 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for demand accesses
3265 system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses
3266 system.l2c.demand_miss_rate::cpu0.inst 0.363836 # miss rate for demand accesses
3267 system.l2c.demand_miss_rate::cpu0.data 0.285980 # miss rate for demand accesses
3268 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for demand accesses
3269 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
3270 system.l2c.demand_miss_rate::cpu1.itb.walker 0.071429 # miss rate for demand accesses
3271 system.l2c.demand_miss_rate::cpu1.inst 0.267976 # miss rate for demand accesses
3272 system.l2c.demand_miss_rate::cpu1.data 0.610394 # miss rate for demand accesses
3273 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for demand accesses
3274 system.l2c.demand_miss_rate::total 0.563538 # miss rate for demand accesses
3275 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for overall accesses
3276 system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses
3277 system.l2c.overall_miss_rate::cpu0.inst 0.363836 # miss rate for overall accesses
3278 system.l2c.overall_miss_rate::cpu0.data 0.285980 # miss rate for overall accesses
3279 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for overall accesses
3280 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
3281 system.l2c.overall_miss_rate::cpu1.itb.walker 0.071429 # miss rate for overall accesses
3282 system.l2c.overall_miss_rate::cpu1.inst 0.267976 # miss rate for overall accesses
3283 system.l2c.overall_miss_rate::cpu1.data 0.610394 # miss rate for overall accesses
3284 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for overall accesses
3285 system.l2c.overall_miss_rate::total 0.563538 # miss rate for overall accesses
3286 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2269.833804 # average UpgradeReq miss latency
3287 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1988.944043 # average UpgradeReq miss latency
3288 system.l2c.UpgradeReq_avg_miss_latency::total 2217.007553 # average UpgradeReq miss latency
3289 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7078.389831 # average SCUpgradeReq miss latency
3290 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1636.620857 # average SCUpgradeReq miss latency
3291 system.l2c.SCUpgradeReq_avg_miss_latency::total 3617.480720 # average SCUpgradeReq miss latency
3292 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151449.231426 # average ReadExReq miss latency
3293 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134291.358306 # average ReadExReq miss latency
3294 system.l2c.ReadExReq_avg_miss_latency::total 144095.618016 # average ReadExReq miss latency
3295 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average ReadSharedReq miss latency
3296 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency
3297 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132604.284011 # average ReadSharedReq miss latency
3298 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139505.255743 # average ReadSharedReq miss latency
3299 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average ReadSharedReq miss latency
3300 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average ReadSharedReq miss latency
3301 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 132500 # average ReadSharedReq miss latency
3302 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134307.079646 # average ReadSharedReq miss latency
3303 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143710.576015 # average ReadSharedReq miss latency
3304 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average ReadSharedReq miss latency
3305 system.l2c.ReadSharedReq_avg_miss_latency::total 154837.686991 # average ReadSharedReq miss latency
3306 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average overall miss latency
3307 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
3308 system.l2c.demand_avg_miss_latency::cpu0.inst 132604.284011 # average overall miss latency
3309 system.l2c.demand_avg_miss_latency::cpu0.data 146185.165727 # average overall miss latency
3310 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average overall miss latency
3311 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average overall miss latency
3312 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3313 system.l2c.demand_avg_miss_latency::cpu1.inst 134307.079646 # average overall miss latency
3314 system.l2c.demand_avg_miss_latency::cpu1.data 135304.866897 # average overall miss latency
3315 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average overall miss latency
3316 system.l2c.demand_avg_miss_latency::total 153708.106217 # average overall miss latency
3317 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average overall miss latency
3318 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
3319 system.l2c.overall_avg_miss_latency::cpu0.inst 132604.284011 # average overall miss latency
3320 system.l2c.overall_avg_miss_latency::cpu0.data 146185.165727 # average overall miss latency
3321 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average overall miss latency
3322 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average overall miss latency
3323 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3324 system.l2c.overall_avg_miss_latency::cpu1.inst 134307.079646 # average overall miss latency
3325 system.l2c.overall_avg_miss_latency::cpu1.data 135304.866897 # average overall miss latency
3326 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average overall miss latency
3327 system.l2c.overall_avg_miss_latency::total 153708.106217 # average overall miss latency
3328 system.l2c.blocked_cycles::no_mshrs 1429 # number of cycles access was blocked
3329 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3330 system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
3331 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3332 system.l2c.avg_blocked_cycles::no_mshrs 142.900000 # average number of cycles each access was blocked
3333 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3334 system.l2c.fast_writes 0 # number of fast writes performed
3335 system.l2c.cache_copies 0 # number of cache copies performed
3336 system.l2c.writebacks::writebacks 102119 # number of writebacks
3337 system.l2c.writebacks::total 102119 # number of writebacks
3338 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 10 # number of ReadSharedReq MSHR hits
3339 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 2 # number of ReadSharedReq MSHR hits
3340 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 13 # number of ReadSharedReq MSHR hits
3341 system.l2c.ReadSharedReq_mshr_hits::total 25 # number of ReadSharedReq MSHR hits
3342 system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits
3343 system.l2c.demand_mshr_hits::cpu0.data 2 # number of demand (read+write) MSHR hits
3344 system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits
3345 system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
3346 system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits
3347 system.l2c.overall_mshr_hits::cpu0.data 2 # number of overall MSHR hits
3348 system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits
3349 system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits
3350 system.l2c.CleanEvict_mshr_misses::writebacks 3254 # number of CleanEvict MSHR misses
3351 system.l2c.CleanEvict_mshr_misses::total 3254 # number of CleanEvict MSHR misses
3352 system.l2c.UpgradeReq_mshr_misses::cpu0.data 9567 # number of UpgradeReq MSHR misses
3353 system.l2c.UpgradeReq_mshr_misses::cpu1.data 2216 # number of UpgradeReq MSHR misses
3354 system.l2c.UpgradeReq_mshr_misses::total 11783 # number of UpgradeReq MSHR misses
3355 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 708 # number of SCUpgradeReq MSHR misses
3356 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1237 # number of SCUpgradeReq MSHR misses
3357 system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses
3358 system.l2c.ReadExReq_mshr_misses::cpu0.data 11710 # number of ReadExReq MSHR misses
3359 system.l2c.ReadExReq_mshr_misses::cpu1.data 8783 # number of ReadExReq MSHR misses
3360 system.l2c.ReadExReq_mshr_misses::total 20493 # number of ReadExReq MSHR misses
3361 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadSharedReq MSHR misses
3362 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
3363 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19528 # number of ReadSharedReq MSHR misses
3364 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9226 # number of ReadSharedReq MSHR misses
3365 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of ReadSharedReq MSHR misses
3366 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses
3367 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
3368 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2812 # number of ReadSharedReq MSHR misses
3369 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1059 # number of ReadSharedReq MSHR misses
3370 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of ReadSharedReq MSHR misses
3371 system.l2c.ReadSharedReq_mshr_misses::total 174366 # number of ReadSharedReq MSHR misses
3372 system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses
3373 system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
3374 system.l2c.demand_mshr_misses::cpu0.inst 19528 # number of demand (read+write) MSHR misses
3375 system.l2c.demand_mshr_misses::cpu0.data 20936 # number of demand (read+write) MSHR misses
3376 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of demand (read+write) MSHR misses
3377 system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses
3378 system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
3379 system.l2c.demand_mshr_misses::cpu1.inst 2812 # number of demand (read+write) MSHR misses
3380 system.l2c.demand_mshr_misses::cpu1.data 9842 # number of demand (read+write) MSHR misses
3381 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of demand (read+write) MSHR misses
3382 system.l2c.demand_mshr_misses::total 194859 # number of demand (read+write) MSHR misses
3383 system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses
3384 system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
3385 system.l2c.overall_mshr_misses::cpu0.inst 19528 # number of overall MSHR misses
3386 system.l2c.overall_mshr_misses::cpu0.data 20936 # number of overall MSHR misses
3387 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of overall MSHR misses
3388 system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses
3389 system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
3390 system.l2c.overall_mshr_misses::cpu1.inst 2812 # number of overall MSHR misses
3391 system.l2c.overall_mshr_misses::cpu1.data 9842 # number of overall MSHR misses
3392 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of overall MSHR misses
3393 system.l2c.overall_mshr_misses::total 194859 # number of overall MSHR misses
3394 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
3395 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
3396 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
3397 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3072 # number of ReadReq MSHR uncacheable
3398 system.l2c.ReadReq_mshr_uncacheable::total 37993 # number of ReadReq MSHR uncacheable
3399 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
3400 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
3401 system.l2c.WriteReq_mshr_uncacheable::total 30918 # number of WriteReq MSHR uncacheable
3402 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
3403 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
3404 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
3405 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5491 # number of overall MSHR uncacheable misses
3406 system.l2c.overall_mshr_uncacheable_misses::total 68911 # number of overall MSHR uncacheable misses
3407 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 695501500 # number of UpgradeReq MSHR miss cycles
3408 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 159987500 # number of UpgradeReq MSHR miss cycles
3409 system.l2c.UpgradeReq_mshr_miss_latency::total 855489000 # number of UpgradeReq MSHR miss cycles
3410 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 52831000 # number of SCUpgradeReq MSHR miss cycles
3411 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 91356500 # number of SCUpgradeReq MSHR miss cycles
3412 system.l2c.SCUpgradeReq_mshr_miss_latency::total 144187500 # number of SCUpgradeReq MSHR miss cycles
3413 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1656368005 # number of ReadExReq MSHR miss cycles
3414 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1091646012 # number of ReadExReq MSHR miss cycles
3415 system.l2c.ReadExReq_mshr_miss_latency::total 2748014017 # number of ReadExReq MSHR miss cycles
3416 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of ReadSharedReq MSHR miss cycles
3417 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles
3418 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2394651541 # number of ReadSharedReq MSHR miss cycles
3419 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1194908505 # number of ReadSharedReq MSHR miss cycles
3420 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of ReadSharedReq MSHR miss cycles
3421 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 778000 # number of ReadSharedReq MSHR miss cycles
3422 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122500 # number of ReadSharedReq MSHR miss cycles
3423 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 349721537 # number of ReadSharedReq MSHR miss cycles
3424 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 141598503 # number of ReadSharedReq MSHR miss cycles
3425 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of ReadSharedReq MSHR miss cycles
3426 system.l2c.ReadSharedReq_mshr_miss_latency::total 25255941335 # number of ReadSharedReq MSHR miss cycles
3427 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of demand (read+write) MSHR miss cycles
3428 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles
3429 system.l2c.demand_mshr_miss_latency::cpu0.inst 2394651541 # number of demand (read+write) MSHR miss cycles
3430 system.l2c.demand_mshr_miss_latency::cpu0.data 2851276510 # number of demand (read+write) MSHR miss cycles
3431 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of demand (read+write) MSHR miss cycles
3432 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 778000 # number of demand (read+write) MSHR miss cycles
3433 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) MSHR miss cycles
3434 system.l2c.demand_mshr_miss_latency::cpu1.inst 349721537 # number of demand (read+write) MSHR miss cycles
3435 system.l2c.demand_mshr_miss_latency::cpu1.data 1233244515 # number of demand (read+write) MSHR miss cycles
3436 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of demand (read+write) MSHR miss cycles
3437 system.l2c.demand_mshr_miss_latency::total 28003955352 # number of demand (read+write) MSHR miss cycles
3438 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of overall MSHR miss cycles
3439 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles
3440 system.l2c.overall_mshr_miss_latency::cpu0.inst 2394651541 # number of overall MSHR miss cycles
3441 system.l2c.overall_mshr_miss_latency::cpu0.data 2851276510 # number of overall MSHR miss cycles
3442 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of overall MSHR miss cycles
3443 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 778000 # number of overall MSHR miss cycles
3444 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122500 # number of overall MSHR miss cycles
3445 system.l2c.overall_mshr_miss_latency::cpu1.inst 349721537 # number of overall MSHR miss cycles
3446 system.l2c.overall_mshr_miss_latency::cpu1.data 1233244515 # number of overall MSHR miss cycles
3447 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of overall MSHR miss cycles
3448 system.l2c.overall_mshr_miss_latency::total 28003955352 # number of overall MSHR miss cycles
3449 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343998000 # number of ReadReq MSHR uncacheable cycles
3450 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5796362003 # number of ReadReq MSHR uncacheable cycles
3451 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11053000 # number of ReadReq MSHR uncacheable cycles
3452 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 358428504 # number of ReadReq MSHR uncacheable cycles
3453 system.l2c.ReadReq_mshr_uncacheable_latency::total 6509841507 # number of ReadReq MSHR uncacheable cycles
3454 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4693982535 # number of WriteReq MSHR uncacheable cycles
3455 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 242306006 # number of WriteReq MSHR uncacheable cycles
3456 system.l2c.WriteReq_mshr_uncacheable_latency::total 4936288541 # number of WriteReq MSHR uncacheable cycles
3457 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343998000 # number of overall MSHR uncacheable cycles
3458 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10490344538 # number of overall MSHR uncacheable cycles
3459 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11053000 # number of overall MSHR uncacheable cycles
3460 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 600734510 # number of overall MSHR uncacheable cycles
3461 system.l2c.overall_mshr_uncacheable_latency::total 11446130048 # number of overall MSHR uncacheable cycles
3462 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3463 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3464 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.227196 # mshr miss rate for UpgradeReq accesses
3465 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516309 # mshr miss rate for UpgradeReq accesses
3466 system.l2c.UpgradeReq_mshr_miss_rate::total 0.253938 # mshr miss rate for UpgradeReq accesses
3467 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.246604 # mshr miss rate for SCUpgradeReq accesses
3468 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.614811 # mshr miss rate for SCUpgradeReq accesses
3469 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.398321 # mshr miss rate for SCUpgradeReq accesses
3470 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.752667 # mshr miss rate for ReadExReq accesses
3471 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.895859 # mshr miss rate for ReadExReq accesses
3472 system.l2c.ReadExReq_mshr_miss_rate::total 0.808020 # mshr miss rate for ReadExReq accesses
3473 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for ReadSharedReq accesses
3474 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for ReadSharedReq accesses
3475 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for ReadSharedReq accesses
3476 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.160015 # mshr miss rate for ReadSharedReq accesses
3477 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for ReadSharedReq accesses
3478 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses
3479 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for ReadSharedReq accesses
3480 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for ReadSharedReq accesses
3481 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167563 # mshr miss rate for ReadSharedReq accesses
3482 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for ReadSharedReq accesses
3483 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.544112 # mshr miss rate for ReadSharedReq accesses
3484 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for demand accesses
3485 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for demand accesses
3486 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for demand accesses
3487 system.l2c.demand_mshr_miss_rate::cpu0.data 0.285952 # mshr miss rate for demand accesses
3488 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for demand accesses
3489 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
3490 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for demand accesses
3491 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for demand accesses
3492 system.l2c.demand_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for demand accesses
3493 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for demand accesses
3494 system.l2c.demand_mshr_miss_rate::total 0.563466 # mshr miss rate for demand accesses
3495 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for overall accesses
3496 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for overall accesses
3497 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for overall accesses
3498 system.l2c.overall_mshr_miss_rate::cpu0.data 0.285952 # mshr miss rate for overall accesses
3499 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for overall accesses
3500 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
3501 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for overall accesses
3502 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for overall accesses
3503 system.l2c.overall_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for overall accesses
3504 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for overall accesses
3505 system.l2c.overall_mshr_miss_rate::total 0.563466 # mshr miss rate for overall accesses
3506 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72697.972196 # average UpgradeReq mshr miss latency
3507 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72196.525271 # average UpgradeReq mshr miss latency
3508 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72603.666299 # average UpgradeReq mshr miss latency
3509 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74620.056497 # average SCUpgradeReq mshr miss latency
3510 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050 # average SCUpgradeReq mshr miss latency
3511 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746 # average SCUpgradeReq mshr miss latency
3512 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360 # average ReadExReq mshr miss latency
3513 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391 # average ReadExReq mshr miss latency
3514 system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867 # average ReadExReq mshr miss latency
3515 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average ReadSharedReq mshr miss latency
3516 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
3517 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average ReadSharedReq mshr miss latency
3518 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633 # average ReadSharedReq mshr miss latency
3519 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average ReadSharedReq mshr miss latency
3520 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average ReadSharedReq mshr miss latency
3521 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency
3522 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average ReadSharedReq mshr miss latency
3523 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561 # average ReadSharedReq mshr miss latency
3524 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average ReadSharedReq mshr miss latency
3525 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396 # average ReadSharedReq mshr miss latency
3526 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
3527 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
3528 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
3529 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
3530 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
3531 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
3532 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3533 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
3534 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
3535 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
3536 system.l2c.demand_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
3537 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
3538 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
3539 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
3540 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
3541 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
3542 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
3543 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3544 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
3545 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
3546 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
3547 system.l2c.overall_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
3548 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency
3549 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845 # average ReadReq mshr uncacheable latency
3550 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average ReadReq mshr uncacheable latency
3551 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312 # average ReadReq mshr uncacheable latency
3552 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823 # average ReadReq mshr uncacheable latency
3553 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769 # average WriteReq mshr uncacheable latency
3554 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430 # average WriteReq mshr uncacheable latency
3555 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890 # average WriteReq mshr uncacheable latency
3556 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency
3557 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321 # average overall mshr uncacheable latency
3558 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average overall mshr uncacheable latency
3559 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240 # average overall mshr uncacheable latency
3560 system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895 # average overall mshr uncacheable latency
3561 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3562 system.membus.trans_dist::ReadReq 37993 # Transaction distribution
3563 system.membus.trans_dist::ReadResp 212610 # Transaction distribution
3564 system.membus.trans_dist::WriteReq 30918 # Transaction distribution
3565 system.membus.trans_dist::WriteResp 30918 # Transaction distribution
3566 system.membus.trans_dist::WritebackDirty 138325 # Transaction distribution
3567 system.membus.trans_dist::CleanEvict 16163 # Transaction distribution
3568 system.membus.trans_dist::UpgradeReq 72828 # Transaction distribution
3569 system.membus.trans_dist::SCUpgradeReq 40466 # Transaction distribution
3570 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
3571 system.membus.trans_dist::ReadExReq 40267 # Transaction distribution
3572 system.membus.trans_dist::ReadExResp 20420 # Transaction distribution
3573 system.membus.trans_dist::ReadSharedReq 174618 # Transaction distribution
3574 system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3575 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
3576 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
3577 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
3578 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656523 # Packet count per connected master and slave (bytes)
3579 system.membus.pkt_count_system.l2c.mem_side::total 778231 # Packet count per connected master and slave (bytes)
3580 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
3581 system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
3582 system.membus.pkt_count::total 851180 # Packet count per connected master and slave (bytes)
3583 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
3584 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
3585 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
3586 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19049928 # Cumulative packet size per connected master and slave (bytes)
3587 system.membus.pkt_size_system.l2c.mem_side::total 19240508 # Cumulative packet size per connected master and slave (bytes)
3588 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3589 system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
3590 system.membus.pkt_size::total 21558652 # Cumulative packet size per connected master and slave (bytes)
3591 system.membus.snoops 119912 # Total snoops (count)
3592 system.membus.snoop_fanout::samples 587818 # Request fanout histogram
3593 system.membus.snoop_fanout::mean 1 # Request fanout histogram
3594 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3595 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3596 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3597 system.membus.snoop_fanout::1 587818 100.00% 100.00% # Request fanout histogram
3598 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3599 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3600 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3601 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3602 system.membus.snoop_fanout::total 587818 # Request fanout histogram
3603 system.membus.reqLayer0.occupancy 81915500 # Layer occupancy (ticks)
3604 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3605 system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
3606 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3607 system.membus.reqLayer2.occupancy 11626486 # Layer occupancy (ticks)
3608 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3609 system.membus.reqLayer5.occupancy 1006913072 # Layer occupancy (ticks)
3610 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3611 system.membus.respLayer2.occupancy 1122228815 # Layer occupancy (ticks)
3612 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3613 system.membus.respLayer3.occupancy 1359881 # Layer occupancy (ticks)
3614 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3615 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3616 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3617 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3618 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3619 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3620 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3621 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3622 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3623 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3624 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3625 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3626 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3627 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3628 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3629 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
3630 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3631 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3632 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
3633 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3634 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3635 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
3636 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3637 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3638 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
3639 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3640 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3641 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
3642 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3643 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3644 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
3645 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3646 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3647 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
3648 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3649 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3650 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3651 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3652 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3653 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3654 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3655 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3656 system.toL2Bus.snoop_filter.tot_requests 988623 # Total number of requests made to the snoop filter.
3657 system.toL2Bus.snoop_filter.hit_single_requests 533441 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3658 system.toL2Bus.snoop_filter.hit_multi_requests 142864 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3659 system.toL2Bus.snoop_filter.tot_snoops 21333 # Total number of snoops made to the snoop filter.
3660 system.toL2Bus.snoop_filter.hit_single_snoops 20424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3661 system.toL2Bus.snoop_filter.hit_multi_snoops 909 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3662 system.toL2Bus.trans_dist::ReadReq 37996 # Transaction distribution
3663 system.toL2Bus.trans_dist::ReadResp 474339 # Transaction distribution
3664 system.toL2Bus.trans_dist::WriteReq 30918 # Transaction distribution
3665 system.toL2Bus.trans_dist::WriteResp 30918 # Transaction distribution
3666 system.toL2Bus.trans_dist::WritebackDirty 400884 # Transaction distribution
3667 system.toL2Bus.trans_dist::CleanEvict 117322 # Transaction distribution
3668 system.toL2Bus.trans_dist::UpgradeReq 107373 # Transaction distribution
3669 system.toL2Bus.trans_dist::SCUpgradeReq 43404 # Transaction distribution
3670 system.toL2Bus.trans_dist::UpgradeResp 150777 # Transaction distribution
3671 system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
3672 system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
3673 system.toL2Bus.trans_dist::ReadExReq 50440 # Transaction distribution
3674 system.toL2Bus.trans_dist::ReadExResp 50440 # Transaction distribution
3675 system.toL2Bus.trans_dist::ReadSharedReq 436359 # Transaction distribution
3676 system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
3677 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256848 # Packet count per connected master and slave (bytes)
3678 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 266902 # Packet count per connected master and slave (bytes)
3679 system.toL2Bus.pkt_count::total 1523750 # Packet count per connected master and slave (bytes)
3680 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34918134 # Cumulative packet size per connected master and slave (bytes)
3681 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4292486 # Cumulative packet size per connected master and slave (bytes)
3682 system.toL2Bus.pkt_size::total 39210620 # Cumulative packet size per connected master and slave (bytes)
3683 system.toL2Bus.snoops 443927 # Total snoops (count)
3684 system.toL2Bus.snoop_fanout::samples 909712 # Request fanout histogram
3685 system.toL2Bus.snoop_fanout::mean 0.336026 # Request fanout histogram
3686 system.toL2Bus.snoop_fanout::stdev 0.474459 # Request fanout histogram
3687 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3688 system.toL2Bus.snoop_fanout::0 604934 66.50% 66.50% # Request fanout histogram
3689 system.toL2Bus.snoop_fanout::1 303869 33.40% 99.90% # Request fanout histogram
3690 system.toL2Bus.snoop_fanout::2 909 0.10% 100.00% # Request fanout histogram
3691 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3692 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3693 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3694 system.toL2Bus.snoop_fanout::total 909712 # Request fanout histogram
3695 system.toL2Bus.reqLayer0.occupancy 874582688 # Layer occupancy (ticks)
3696 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3697 system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
3698 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3699 system.toL2Bus.respLayer0.occupancy 652718656 # Layer occupancy (ticks)
3700 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3701 system.toL2Bus.respLayer1.occupancy 208359113 # Layer occupancy (ticks)
3702 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3703 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3704 system.cpu0.kern.inst.quiesce 1876 # number of quiesce instructions executed
3705 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3706 system.cpu1.kern.inst.quiesce 2727 # number of quiesce instructions executed
3708 ---------- End Simulation Statistics ----------
projects / gem5.git / blob